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BugFix:Prevent drv_led_pwm passing a value of 0 to px4_arch_configgpio

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This prevents the meta value of 0 => not used from being passed to
  px4_arch_configgpio. As this would map to PORTA|PIN0 and is not
  the intended configuration.
This commit is contained in:
David Sidrane
2017-01-19 22:18:04 +01:00
committed by Lorenz Meier
parent 3ea5a24924
commit d42f8f4745
1 changed files with 25 additions and 21 deletions
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src/drivers/stm32/drv_led_pwm.cpp
+25 -21
View File
@@ -167,33 +167,37 @@ static void led_pwm_timer_init_timer(unsigned timer)
static void static void
led_pwm_channel_init(unsigned channel) led_pwm_channel_init(unsigned channel)
{ {
unsigned timer = led_pwm_channels[channel].timer_index; /* Only initialize used channels */
/* configure the GPIO first */ if (led_pwm_channels[channel].timer_channel) {
px4_arch_configgpio(led_pwm_channels[channel].gpio_out); unsigned timer = led_pwm_channels[channel].timer_index;
/* configure the channel */ /* configure the GPIO first */
switch (led_pwm_channels[channel].timer_channel) { px4_arch_configgpio(led_pwm_channels[channel].gpio_out);
case 1:
rCCMR1(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) | GTIM_CCMR1_OC1PE;
rCCER(timer) |= GTIM_CCER_CC1E;
break;
case 2: /* configure the channel */
rCCMR1(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC2M_SHIFT) | GTIM_CCMR1_OC2PE; switch (led_pwm_channels[channel].timer_channel) {
rCCER(timer) |= GTIM_CCER_CC2E; case 1:
break; rCCMR1(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) | GTIM_CCMR1_OC1PE;
rCCER(timer) |= GTIM_CCER_CC1E;
break;
case 3: case 2:
rCCMR2(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR2_OC3M_SHIFT) | GTIM_CCMR2_OC3PE; rCCMR1(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC2M_SHIFT) | GTIM_CCMR1_OC2PE;
rCCER(timer) |= GTIM_CCER_CC3E; rCCER(timer) |= GTIM_CCER_CC2E;
break; break;
case 4: case 3:
rCCMR2(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR2_OC4M_SHIFT) | GTIM_CCMR2_OC4PE; rCCMR2(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR2_OC3M_SHIFT) | GTIM_CCMR2_OC3PE;
rCCER(timer) |= GTIM_CCER_CC4E; rCCER(timer) |= GTIM_CCER_CC3E;
break; break;
case 4:
rCCMR2(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR2_OC4M_SHIFT) | GTIM_CCMR2_OC4PE;
rCCER(timer) |= GTIM_CCER_CC4E;
break;
}
} }
} }