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Add LPC32xx memory map and interrupt numbers
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4877 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
Executable → Regular
+183
-61
@@ -1,61 +1,183 @@
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/************************************************************************************
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* arch/arm/src/lpc43xx/chip.h
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*
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* Copyright (C) 2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_MEMORYMAP_H
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#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_MEMORYMAP_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_MEMORYMAP_H */
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/************************************************************************************
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* arch/arm/src/lpc43xx/chip.h
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*
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* Copyright (C) 2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_MEMORYMAP_H
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#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_MEMORYMAP_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Memory Map ***********************************************************************/
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/* See arch/arm/include/lpc43xx/chip.h for the actual sizes of FLASH and SRAM
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* regions
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*/
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#define LPC43_SHADOW_BASE 0x00000000 /* -0x0fffffff: 256Mb shadow area */
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#define LPC43_LOCSRAM_BASE 0x10000000 /* -0x1fffffff: Local SRAM and external memory */
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#define LPC43_AHBSRAM_BASE 0x20000000 /* -0x27ffffff: AHB SRAM */
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#define LPC43_DYCS0_BASE 0x28000000 /* -0x2fffffff: 128Mb dynamic external memory */
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#define LPC43_DYCS1_BASE 0x30000000 /* -0x2fffffff: 256Mb dynamic external memory */
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#define LPC43_PERIPH_BASE 0x40000000 /* -0x5fffffff: Peripherals */
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#define LPC43_DYCS2_BASE 0x60000000 /* -0x6fffffff: 256Mb dynamic external memory */
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#define LPC43_DYCS3_BASE 0x70000000 /* -0x7fffffff: 256Mb dynamic external memory */
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#define LPC43_SPIFI_DATA_BASE 0x80000000 /* -0x87ffffff: 256Mb dynamic external memory */
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#define LPC43_ARM_BASE 0xe0000000 /* -0xe00fffff: ARM private */
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/* Local SRAM Banks and external memory */
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#define LPC43_LOCSRAM_BANK0_BASE (LPC43_LOCSRAM_BASE + 0x00000000)
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#define LPC43_LOCSRAM_BANK1_BASE (LPC43_LOCSRAM_BASE + 0x00080000)
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#define LPC43_ROM_BASE (LPC43_LOCSRAM_BASE + 0x00400000)
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#define LPC43_LOCSRAM_SPIFI_BASE (LPC43_LOCSRAM_BASE + 0x04000000)
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#define LPC43_EXTMEM_CS0_BASE (LPC43_LOCSRAM_BASE + 0x0c000000)
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#define LPC43_EXTMEM_CS1_BASE (LPC43_LOCSRAM_BASE + 0x0d000000)
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#define LPC43_EXTMEM_CS2_BASE (LPC43_LOCSRAM_BASE + 0x0e000000)
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#define LPC43_EXTMEM_CS3_BASE (LPC43_LOCSRAM_BASE + 0x0f000000)
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/* AHB SRAM */
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#define LPC43_AHBSRAM_BANK0_BASE (LPC43_AHBSRAM_BASE)
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#define LPC43_AHBSRAM_BANK1_BASE (LPC43_AHBSRAM_BASE + 0x00008000)
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#define LPC43_AHBSRAM_BANK2_BASE (LPC43_AHBSRAM_BASE + 0x0000c000)
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#define LPC43_AHBSRAM_BITBAND_BASE (LPC43_AHBSRAM_BASE + 0x0000c000)
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/* Peripherals */
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#define LPC43_AHBPERIPH_BASE (LPC43_PERIPH_BASE + 0x00000000)
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#define LPC43_RTCPERIPH_BASE (LPC43_PERIPH_BASE + 0x00040000)
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#define LPC43_CLKPERIPH_BASE (LPC43_PERIPH_BASE + 0x00050000)
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#define LPC43_APB0PERIPH_BASE (LPC43_PERIPH_BASE + 0x00080000)
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#define LPC43_APB1PERIPH_BASE (LPC43_PERIPH_BASE + 0x000a0000)
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#define LPC43_APB2PERIPH_BASE (LPC43_PERIPH_BASE + 0x000c0000)
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#define LPC43_APB3PERIPH_BASE (LPC43_PERIPH_BASE + 0x000e0000)
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#define LPC43_GPIO_BASE (LPC43_PERIPH_BASE + 0x000f4000)
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#define LPC43_SPI_BASE (LPC43_PERIPH_BASE + 0x00100000)
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#define LPC43_SGPIO_BASE (LPC43_PERIPH_BASE + 0x00101000)
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#define LPC43_PERIPH_BITBAND_BASE (LPC43_PERIPH_BASE + 0x02000000)
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/* AHB Peripherals */
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#define LPC43_SCT_BASE (LPC43_AHBPERIPH_BASE + 0x00000000)
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#define LPC43_DMA_BASE (LPC43_AHBPERIPH_BASE + 0x00002000)
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#define LPC43_SPIFI_PERIPH_BASE (LPC43_AHBPERIPH_BASE + 0x00003000)
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#define LPC43_MMCSD_BASE (LPC43_AHBPERIPH_BASE + 0x00004000)
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#define LPC43_EMC_BASE (LPC43_AHBPERIPH_BASE + 0x00005000)
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#define LPC43_USB0_BASE (LPC43_AHBPERIPH_BASE + 0x00006000)
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#define LPC43_USB1_BASE (LPC43_AHBPERIPH_BASE + 0x00007000)
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#define LPC43_LCD_BASE (LPC43_AHBPERIPH_BASE + 0x00008000)
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#define LPC43_ETHERNET_BASE (LPC43_AHBPERIPH_BASE + 0x00010000)
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/* RTC Domain Peripherals */
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#define LPC43_ALARM_BASE (LPC43_RTCPERIPH_BASE + 0x00000000)
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#define LPC43_BACKUP_BASE (LPC43_RTCPERIPH_BASE + 0x00001000)
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#define LPC43_PWRMODE_BASE (LPC43_RTCPERIPH_BASE + 0x00002000)
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#define LPC43_CREG_BASE (LPC43_RTCPERIPH_BASE + 0x00003000)
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#define LPC43_EVROUTER_BASE (LPC43_RTCPERIPH_BASE + 0x00004000)
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#define LPC43_OTPC_BASE (LPC43_RTCPERIPH_BASE + 0x00005000)
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#define LPC43_RTC_BASE (LPC43_RTCPERIPH_BASE + 0x00006000)
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/* Clocking and Reset Peripherals */
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#define LPC43_CGU_BASE (LPC43_CLKPERIPH_BASE + 0x00000000)
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#define LPC43_CCU1_BASE (LPC43_CLKPERIPH_BASE + 0x00001000)
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#define LPC43_CCU2_BASE (LPC43_CLKPERIPH_BASE + 0x00002000)
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#define LPC43_RGU_BASE (LPC43_CLKPERIPH_BASE + 0x00003000)
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/* APB0 Peripherals */
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#define LPC43_WWDT_BASE (LPC43_APB0PERIPH_BASE + 0x00000000)
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#define LPC43_USART0_BASE (LPC43_APB0PERIPH_BASE + 0x00001000)
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#define LPC43_UART1_BASE (LPC43_APB0PERIPH_BASE + 0x00002000)
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#define LPC43_SSP0_BASE (LPC43_APB0PERIPH_BASE + 0x00003000)
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#define LPC43_TIMER0_BASE (LPC43_APB0PERIPH_BASE + 0x00004000)
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#define LPC43_TIMER1_BASE (LPC43_APB0PERIPH_BASE + 0x00005000)
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#define LPC43_SCU_BASE (LPC43_APB0PERIPH_BASE + 0x00006000)
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#define LPC43_GPIOINT_BASE (LPC43_APB0PERIPH_BASE + 0x00007000)
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#define LPC43_GRP0INT_BASE (LPC43_APB0PERIPH_BASE + 0x00008000)
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#define LPC43_GRP1INT_BASE (LPC43_APB0PERIPH_BASE + 0x00009000)
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/* APB1 Peripherals */
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#define LPC43_MCPWM_BASE (LPC43_APB1PERIPH_BASE + 0x00000000)
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#define LPC43_I2C0_BASE (LPC43_APB1PERIPH_BASE + 0x00001000)
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#define LPC43_I2S0_BASE (LPC43_APB1PERIPH_BASE + 0x00002000)
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#define LPC43_I2S1_BASE (LPC43_APB1PERIPH_BASE + 0x00003000)
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#define LPC43_CAN1_BASE (LPC43_APB1PERIPH_BASE + 0x00004000)
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/* APB2 Peripherals */
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#define LPC43_RITIMER_BASE (LPC43_APB2PERIPH_BASE + 0x00000000)
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#define LPC43_USART2_BASE (LPC43_APB2PERIPH_BASE + 0x00001000)
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#define LPC43_USART3_BASE (LPC43_APB2PERIPH_BASE + 0x00002000)
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#define LPC43_TIMER2_BASE (LPC43_APB2PERIPH_BASE + 0x00003000)
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#define LPC43_TIMER3_BASE (LPC43_APB2PERIPH_BASE + 0x00004000)
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#define LPC43_SSP1_BASE (LPC43_APB2PERIPH_BASE + 0x00005000)
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#define LPC43_QEI_BASE (LPC43_APB2PERIPH_BASE + 0x00006000)
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#define LPC43_GIMA_BASE (LPC43_APB2PERIPH_BASE + 0x00007000)
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/* APB3 Peripherals */
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#define LPC43_I2C1_BASE (LPC43_APB3PERIPH_BASE + 0x00000000)
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#define LPC43_DAC_BASE (LPC43_APB3PERIPH_BASE + 0x00001000)
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#define LPC43_CAN0_BASE (LPC43_APB3PERIPH_BASE + 0x00002000)
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#define LPC43_ADC0_BASE (LPC43_APB3PERIPH_BASE + 0x00003000)
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#define LPC43_ADC1_BASE (LPC43_APB3PERIPH_BASE + 0x00004000)
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/* ARM Private */
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#define LPC43_SCS_BASE (LPC43_ARM_BASE + 0x0000e000)
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#define LPC43_DEBUGMCU_BASE (LPC43_ARM_BASE + 0x00042000)
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_MEMORYMAP_H */
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