Some ENC28J60-related fixes

git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@5154 7fd9a85b-ad96-42d3-883c-3090e2eb8679

apps/examples/xmlrpc/Kconfig

@@ -16,6 +16,7 @@ config EXAMPLES_XMLRPC
 config EXAMPLES_XMLRPC_BUFFERSIZE
 	int "HTTP buffer size"
 	default 1024
+	depends on EXAMPLES_XMLRPC
 
 config EXAMPLES_XMLRPC_DHCPC
 	bool "DHCP Client"

apps/nshlib/nsh_netinit.c

@@ -164,6 +164,7 @@ int nsh_netinit(void)
         dhcpc_close(handle);
     }
 #endif
+
   return OK;
 }
 

nuttx/configs/fire-stm32v2/nsh/defconfig

@@ -260,7 +260,7 @@ CONFIG_SDCLONE_DISABLE=y
 CONFIG_SCHED_WORKQUEUE=y
 CONFIG_SCHED_WORKPRIORITY=192
 CONFIG_SCHED_WORKPERIOD=50000
-CONFIG_SCHED_WORKSTACKSIZE=1024
+CONFIG_SCHED_WORKSTACKSIZE=2048
 CONFIG_SIG_SIGWORK=4
 # CONFIG_SCHED_LPWORK is not set
 CONFIG_SCHED_WAITPID=y

nuttx/configs/fire-stm32v2/src/up_autoleds.c

@@ -115,23 +115,23 @@
 
 #define LED_STARTED_ON_SETBITS       (0)
 #define LED_STARTED_ON_CLRBITS       ((FIRE_LED1|FIRE_LED2|FIRE_LED3) << ON_CLRBITS_SHIFT)
-#define LED_STARTED_OFF_SETBITS      LED_STARTED_ON_SETBITS
+#define LED_STARTED_OFF_SETBITS      (0)
-#define LED_STARTED_OFF_CLRBITS      LED_STARTED_ON_CLRBITS
+#define LED_STARTED_OFF_CLRBITS      ((FIRE_LED1|FIRE_LED2|FIRE_LED3) << OFF_CLRBITS_SHIFT)
 
 #define LED_HEAPALLOCATE_ON_SETBITS  ((FIRE_LED1) << ON_SETBITS_SHIFT)
 #define LED_HEAPALLOCATE_ON_CLRBITS  ((FIRE_LED2|FIRE_LED3) << ON_CLRBITS_SHIFT)
-#define LED_HEAPALLOCATE_OFF_SETBITS LED_STARTED_ON_SETBITS
+#define LED_HEAPALLOCATE_OFF_SETBITS (0)
-#define LED_HEAPALLOCATE_OFF_CLRBITS LED_STARTED_ON_CLRBITS
+#define LED_HEAPALLOCATE_OFF_CLRBITS ((FIRE_LED1|FIRE_LED2|FIRE_LED3) << OFF_CLRBITS_SHIFT)
 
 #define LED_IRQSENABLED_ON_SETBITS   ((FIRE_LED2) << ON_SETBITS_SHIFT)
 #define LED_IRQSENABLED_ON_CLRBITS   ((FIRE_LED1|FIRE_LED3) << ON_CLRBITS_SHIFT)
-#define LED_IRQSENABLED_OFF_SETBITS  LED_HEAPALLOCATE_ON_SETBITS
+#define LED_IRQSENABLED_OFF_SETBITS  ((FIRE_LED1) << OFF_SETBITS_SHIFT)
-#define LED_IRQSENABLED_OFF_CLRBITS  LED_HEAPALLOCATE_ON_CLRBITS
+#define LED_IRQSENABLED_OFF_CLRBITS  ((FIRE_LED1|FIRE_LED2|FIRE_LED3) << OFF_CLRBITS_SHIFT)
 
 #define LED_STACKCREATED_ON_SETBITS  (0)
 #define LED_STACKCREATED_ON_CLRBITS  ((FIRE_LED1|FIRE_LED2|FIRE_LED3) << ON_CLRBITS_SHIFT)
-#define LED_STACKCREATED_OFF_SETBITS LED_IRQSENABLED_ON_SETBITS
+#define LED_STACKCREATED_OFF_SETBITS ((FIRE_LED2) << OFF_SETBITS_SHIFT)
-#define LED_STACKCREATED_OFF_CLRBITS LED_IRQSENABLED_ON_CLRBITS
+#define LED_STACKCREATED_OFF_CLRBITS ((FIRE_LED1|FIRE_LED3) << OFF_CLRBITS_SHIFT)
 
 #define LED_FLASH_ON_SETBITS         ((FIRE_LED3) << ON_SETBITS_SHIFT)
 #define LED_FLASH_ON_CLRBITS         ((0) << ON_CLRBITS_SHIFT)

nuttx/configs/fire-stm32v2/src/up_enc28j60.c

@@ -157,12 +157,12 @@ static void up_enable(FAR const struct enc_lower_s *lower)
   FAR struct stm32_lower_s *priv = (FAR struct stm32_lower_s *)lower;
 
   DEBUGASSERT(priv->handler);
-  (void)stm32_gpiosetevent(GPIO_ENC28J60_INTR, true, true, true, priv->handler);
+  (void)stm32_gpiosetevent(GPIO_ENC28J60_INTR, false, true, true, priv->handler);
 }
 
 static void up_disable(FAR const struct enc_lower_s *lower)
 {
-  (void)stm32_gpiosetevent(GPIO_ENC28J60_INTR, true, true, true, NULL);
+  (void)stm32_gpiosetevent(GPIO_ENC28J60_INTR, false, true, true, NULL);
 }
 
 /****************************************************************************

nuttx/drivers/net/enc28j60.c

@@ -1383,7 +1383,14 @@ static void enc_worker(FAR void *arg)
 
   DEBUGASSERT(priv);
 
-  /* Disable further interrupts by clearing the global interrup enable bit */
+  /* Disable further interrupts by clearing the global interrupt enable bit.
+   * "After an interrupt occurs, the host controller should clear the global
+   * enable bit for the interrupt pin before servicing the interrupt. Clearing
+   * the enable bit will cause the interrupt pin to return to the non-asserted
+   * state (high). Doing so will prevent the host controller from missing a
+   * falling edge should another interrupt occur while the immediate interrupt
+   * is being serviced."
+   */
 
   enc_bfcgreg(priv, ENC_EIE, EIE_INTIE);
 
@@ -1551,12 +1558,17 @@ static void enc_worker(FAR void *arg)
           enc_rxerif(priv);                       /* Handle the RX error */
           enc_bfcgreg(priv, ENC_EIR, EIR_RXERIF); /* Clear the RXERIF interrupt */
         }
-
     }
 
   /* Enable Ethernet interrupts */
 
   enc_bfsgreg(priv, ENC_EIE, EIE_INTIE);
+
+  /* Enable GPIO interrupts if they were disbled in enc_interrupt */
+
+#ifndef CONFIG_SPI_OWNBUS
+  priv->lower->enable(priv->lower);
+#endif
 }
 
 /****************************************************************************
@@ -1596,6 +1608,14 @@ static int enc_interrupt(int irq, FAR void *context)
    * a good thing to do in any event.
    */
 
+  DEBUGASSERT(work_available(&priv->work));
+
+  /* Notice that further GPIO interrupts are disabled until the work is
+   * actually performed.  This is to prevent overrun of the worker thread.
+   * Interrupts are re-enabled in enc_worker() when the work is completed.
+   */
+
+  priv->lower->disable(priv->lower);
   return work_queue(HPWORK, &priv->work, enc_worker, (FAR void *)priv, 0);
 #endif
 }

nuttx/include/nuttx/net/enc28j60.h

@@ -85,6 +85,22 @@ struct enc_stats_s
 /* The ENC28J60 normal provides interrupts to the MCU via a GPIO pin.  The
  * following structure provides an MCU-independent mechanixm for controlling
  * the ENC28J60 GPIO interrupt.
+ *
+ * The ENC32J60 interrupt is an active low, *level* interrupt. "When an
+ * interrupt occurs, the interrupt flag is set. If the interrupt is enabled
+ * in the EIE register and the INTIE global interrupt enable bit is set, the
+ * INT pin will be driven low"
+ *
+ * "When an enabled interrupt occurs, the interrupt pin will remain low until
+ * all flags which are causing the interrupt are cleared or masked off
+ * (enable bit is cleared) by the host controller."  However, the interrupt
+ * will behave like a falling edge interrupt because "After an interrupt
+ * occurs, the host controller [clears] the global enable bit for the
+ * interrupt pin before servicing the interrupt. Clearing the enable bit
+ * will cause the interrupt pin to return to the non-asserted state (high).
+ * Doing so will prevent the host controller from missing a falling edge
+ * should another interrupt occur while the immediate interrupt is being
+ * serviced."
  */
 
 struct enc_lower_s