mirror of
https://gitee.com/mirrors_PX4/PX4-Autopilot.git
synced 2026-04-14 10:07:39 +08:00
Merge pull request #125 from UAVCAN/stm32-test-removal
Remove STM32 test application
This commit is contained in:
Pavel Kirienko
GitHub
commit
cf4c7355c8
@ -31,4 +31,4 @@ before_script: "mkdir build && cd build && cmake .. -DCMAKE_BUILD_TYPE=Debug -DC
|
||||
script:
|
||||
- if [ "${COVERITY_SCAN_BRANCH}" != 1 ] && [ "${TARGET}" == "native" ]; then make ; fi
|
||||
- if [ "${COVERITY_SCAN_BRANCH}" != 1 ] && [ "${TARGET}" == "lpc11c24" ]; then cd "$TRAVIS_BUILD_DIR/libuavcan_drivers/lpc11c24/test_olimex_lpc_p11c24" && make all ; fi
|
||||
- if [ "${COVERITY_SCAN_BRANCH}" != 1 ] && [ "${TARGET}" == "stm32" ]; then cd "$TRAVIS_BUILD_DIR/libuavcan_drivers/stm32/test_stm32f107" && git clone "https://github.com/Zubax/zubax_chibios" && cd zubax_chibios && git checkout stable_v1 && git submodule update --init --recursive && cd .. && make ; fi
|
||||
- if [ "${COVERITY_SCAN_BRANCH}" != 1 ] && [ "${TARGET}" == "stm32" ]; then echo "TODO STM32 test environment is not configured"; fi
|
||||
|
||||
11
libuavcan_drivers/stm32/README.md
Normal file
11
libuavcan_drivers/stm32/README.md
Normal file
@ -0,0 +1,11 @@
|
||||
STM32 platform driver
|
||||
=====================
|
||||
|
||||
The directory `driver` contains the STM32 platform driver for Libuavcan.
|
||||
|
||||
A dedicated example application may be added later here.
|
||||
For now, please consider the following open source projects as a reference:
|
||||
|
||||
- https://github.com/PX4/sapog
|
||||
- https://github.com/Zubax/zubax_gnss
|
||||
- https://github.com/PX4/Firmware
|
||||
@ -1,2 +0,0 @@
|
||||
# Nested repository, we don't need to submodule it
|
||||
zubax_chibios
|
||||
@ -1,61 +0,0 @@
|
||||
#
|
||||
# Copyright (C) 2014 Pavel Kirienko <pavel.kirienko@gmail.com>
|
||||
#
|
||||
|
||||
PROJECT = uavcan_test_stm32f107
|
||||
|
||||
#
|
||||
# Test application
|
||||
#
|
||||
|
||||
MAIN ?= main.cpp
|
||||
|
||||
CPPSRC = src/$(MAIN) \
|
||||
src/dummy.cpp \
|
||||
src/board/board.cpp
|
||||
|
||||
#
|
||||
# UAVCAN library
|
||||
#
|
||||
|
||||
export LIBUAVCAN_REPO_ROOT := $(abspath ../../..)
|
||||
|
||||
UDEFS = -DUAVCAN_STM32_CHIBIOS=1 \
|
||||
-DUAVCAN_STM32_TIMER_NUMBER=6 \
|
||||
-DUAVCAN_TINY=1 \
|
||||
-DUAVCAN_STM32_NUM_IFACES=2 \
|
||||
-DUAVCAN_MEM_POOL_BLOCK_SIZE=48
|
||||
|
||||
include $(LIBUAVCAN_REPO_ROOT)/libuavcan/include.mk
|
||||
CPPSRC += $(LIBUAVCAN_SRC)
|
||||
UINCDIR += $(LIBUAVCAN_INC)
|
||||
|
||||
include $(LIBUAVCAN_REPO_ROOT)/libuavcan_drivers/stm32/driver/include.mk
|
||||
CPPSRC += $(LIBUAVCAN_STM32_SRC)
|
||||
UINCDIR += $(LIBUAVCAN_STM32_INC)
|
||||
|
||||
$(info $(shell $(LIBUAVCAN_DSDLC) $(UAVCAN_DSDL_DIR)))
|
||||
UINCDIR += dsdlc_generated
|
||||
|
||||
#
|
||||
# Git commit hash
|
||||
#
|
||||
|
||||
GIT_HASH := $(shell git rev-parse --short HEAD)
|
||||
UDEFS += -DGIT_HASH=0x$(GIT_HASH)
|
||||
|
||||
#
|
||||
# Platform
|
||||
#
|
||||
|
||||
UINCDIR += src/sys
|
||||
|
||||
SERIAL_CLI_PORT_NUMBER = 2
|
||||
|
||||
CPPWARN := -Wundef -Wno-error=undef
|
||||
|
||||
RELEASE_OPT = -Os -fomit-frame-pointer
|
||||
DEBUG_OPT = -Os -g3
|
||||
#USE_OPT = -flto
|
||||
|
||||
include zubax_chibios/rules_stm32f105_107.mk
|
||||
@ -1,4 +0,0 @@
|
||||
UAVCAN test project for STM32
|
||||
-----------------------------
|
||||
|
||||
Please checkout/symlink https://github.com/Zubax/zubax_chibios, branch `stable_v1`, into subdirectory `zubax_chibios`; then follow instructions in `zubax_chibios/README.md`.
|
||||
@ -1,99 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Pavel Kirienko <pavel.kirienko@gmail.com>
|
||||
*/
|
||||
|
||||
#include "board.hpp"
|
||||
#include <cstring>
|
||||
#include <unistd.h>
|
||||
#include <ch.h>
|
||||
#include <ch.hpp>
|
||||
#include <hal.h>
|
||||
#include <zubax_chibios/sys/sys.h>
|
||||
|
||||
/**
|
||||
* GPIO config for ChibiOS PAL driver
|
||||
*/
|
||||
const PALConfig pal_default_config =
|
||||
{
|
||||
{ VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH },
|
||||
{ VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH },
|
||||
{ VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH },
|
||||
{ VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH },
|
||||
{ VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH }
|
||||
};
|
||||
|
||||
namespace board
|
||||
{
|
||||
|
||||
void init()
|
||||
{
|
||||
halInit();
|
||||
|
||||
chibios_rt::System::init();
|
||||
|
||||
sdStart(&STDOUT_SD, nullptr);
|
||||
}
|
||||
|
||||
__attribute__((noreturn))
|
||||
void die(int error)
|
||||
{
|
||||
lowsyslog("Fatal error %i\n", error);
|
||||
while (1)
|
||||
{
|
||||
setLed(false);
|
||||
::sleep(1);
|
||||
setLed(true);
|
||||
::sleep(1);
|
||||
}
|
||||
}
|
||||
|
||||
void setLed(bool state)
|
||||
{
|
||||
palWritePad(GPIO_PORT_LED, GPIO_PIN_LED, state);
|
||||
}
|
||||
|
||||
void restart()
|
||||
{
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
|
||||
void readUniqueID(std::uint8_t bytes[UniqueIDSize])
|
||||
{
|
||||
std::memcpy(bytes, reinterpret_cast<const void*>(0x1FFFF7E8), UniqueIDSize);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
* Early init from ChibiOS
|
||||
*/
|
||||
extern "C"
|
||||
{
|
||||
|
||||
void __early_init(void)
|
||||
{
|
||||
stm32_clock_init();
|
||||
}
|
||||
|
||||
void boardInit(void)
|
||||
{
|
||||
AFIO->MAPR |=
|
||||
AFIO_MAPR_CAN_REMAP_REMAP3 |
|
||||
AFIO_MAPR_CAN2_REMAP |
|
||||
AFIO_MAPR_USART2_REMAP;
|
||||
|
||||
/*
|
||||
* Enabling the CAN controllers, then configuring GPIO functions for CAN_TX.
|
||||
* Order matters, otherwise the CAN_TX pins will twitch, disturbing the CAN bus.
|
||||
* This is why we can't perform this initialization using ChibiOS GPIO configuration.
|
||||
*/
|
||||
RCC->APB1ENR |= RCC_APB1ENR_CAN1EN;
|
||||
palSetPadMode(GPIOD, 1, PAL_MODE_STM32_ALTERNATE_PUSHPULL);
|
||||
|
||||
#if UAVCAN_STM32_NUM_IFACES > 1
|
||||
RCC->APB1ENR |= RCC_APB1ENR_CAN2EN;
|
||||
palSetPadMode(GPIOB, 6, PAL_MODE_STM32_ALTERNATE_PUSHPULL);
|
||||
#endif
|
||||
}
|
||||
|
||||
}
|
||||
@ -1,25 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Pavel Kirienko <pavel.kirienko@gmail.com>
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <cstdint>
|
||||
|
||||
namespace board
|
||||
{
|
||||
|
||||
void init();
|
||||
|
||||
__attribute__((noreturn))
|
||||
void die(int error);
|
||||
|
||||
void setLed(bool state);
|
||||
|
||||
void restart();
|
||||
|
||||
constexpr unsigned UniqueIDSize = 12;
|
||||
|
||||
void readUniqueID(std::uint8_t bytes[UniqueIDSize]);
|
||||
|
||||
}
|
||||
@ -1,215 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Pavel Kirienko <pavel.kirienko@gmail.com>
|
||||
*/
|
||||
|
||||
#include <unistd.h>
|
||||
#include <zubax_chibios/sys/sys.h>
|
||||
#include <uavcan_stm32/uavcan_stm32.hpp>
|
||||
#include <uavcan/protocol/global_time_sync_slave.hpp>
|
||||
#include <uavcan/protocol/dynamic_node_id_client.hpp>
|
||||
#include "board/board.hpp"
|
||||
|
||||
namespace app
|
||||
{
|
||||
namespace
|
||||
{
|
||||
|
||||
uavcan_stm32::CanInitHelper<128> can;
|
||||
|
||||
constexpr unsigned NodePoolSize = 16384;
|
||||
|
||||
uavcan::Node<NodePoolSize>& getNode()
|
||||
{
|
||||
static uavcan::Node<NodePoolSize> node(can.driver, uavcan_stm32::SystemClock::instance());
|
||||
return node;
|
||||
}
|
||||
|
||||
void init()
|
||||
{
|
||||
board::init();
|
||||
|
||||
/*
|
||||
* CAN auto bit rate detection.
|
||||
* Automatic bit rate detection requires that the bus has at least one other CAN node publishing some
|
||||
* frames periodically.
|
||||
* Auto bit rate detection can be bypassed byif the desired bit rate is passed directly to can.init(), e.g.:
|
||||
* can.init(1000000);
|
||||
*/
|
||||
int res = 0;
|
||||
do
|
||||
{
|
||||
::sleep(1);
|
||||
::lowsyslog("CAN auto bit rate detection...\n");
|
||||
|
||||
std::uint32_t bitrate = 0;
|
||||
res = can.init([]() { ::usleep(can.getRecommendedListeningDelay().toUSec()); }, bitrate);
|
||||
if (res >= 0)
|
||||
{
|
||||
::lowsyslog("CAN inited at %u bps\n", unsigned(bitrate));
|
||||
}
|
||||
}
|
||||
while (res < 0);
|
||||
}
|
||||
|
||||
class : public chibios_rt::BaseStaticThread<8192>
|
||||
{
|
||||
void configureNodeInfo()
|
||||
{
|
||||
getNode().setName("org.uavcan.stm32_test_stm32f107");
|
||||
|
||||
/*
|
||||
* Software version
|
||||
* TODO: Fill other fields too
|
||||
*/
|
||||
uavcan::protocol::SoftwareVersion swver;
|
||||
|
||||
swver.vcs_commit = GIT_HASH;
|
||||
swver.optional_field_flags = swver.OPTIONAL_FIELD_FLAG_VCS_COMMIT;
|
||||
|
||||
getNode().setSoftwareVersion(swver);
|
||||
|
||||
lowsyslog("Git commit hash: 0x%08x\n", GIT_HASH);
|
||||
|
||||
/*
|
||||
* Hardware version
|
||||
* TODO: Fill other fields too
|
||||
*/
|
||||
uavcan::protocol::HardwareVersion hwver;
|
||||
|
||||
std::uint8_t uid[board::UniqueIDSize] = {};
|
||||
board::readUniqueID(uid);
|
||||
std::copy(std::begin(uid), std::end(uid), std::begin(hwver.unique_id));
|
||||
|
||||
getNode().setHardwareVersion(hwver);
|
||||
|
||||
lowsyslog("UDID:");
|
||||
for (auto b : hwver.unique_id)
|
||||
{
|
||||
lowsyslog(" %02x", unsigned(b));
|
||||
}
|
||||
lowsyslog("\n");
|
||||
}
|
||||
|
||||
void performDynamicNodeIDAllocation()
|
||||
{
|
||||
uavcan::DynamicNodeIDClient client(getNode());
|
||||
|
||||
const int client_start_res = client.start(getNode().getHardwareVersion().unique_id);
|
||||
if (client_start_res < 0)
|
||||
{
|
||||
board::die(client_start_res);
|
||||
}
|
||||
|
||||
lowsyslog("Waiting for dynamic node ID allocation...\n");
|
||||
while (!client.isAllocationComplete())
|
||||
{
|
||||
const int spin_res = getNode().spin(uavcan::MonotonicDuration::fromMSec(100));
|
||||
if (spin_res < 0)
|
||||
{
|
||||
lowsyslog("Spin failure: %i\n", spin_res);
|
||||
}
|
||||
}
|
||||
|
||||
lowsyslog("Dynamic node ID %d allocated by %d\n",
|
||||
int(client.getAllocatedNodeID().get()),
|
||||
int(client.getAllocatorNodeID().get()));
|
||||
|
||||
getNode().setNodeID(client.getAllocatedNodeID());
|
||||
}
|
||||
|
||||
public:
|
||||
msg_t main()
|
||||
{
|
||||
/*
|
||||
* Setting up the node parameters
|
||||
*/
|
||||
configureNodeInfo();
|
||||
|
||||
/*
|
||||
* Initializing the UAVCAN node
|
||||
*/
|
||||
const int node_init_res = getNode().start();
|
||||
if (node_init_res < 0)
|
||||
{
|
||||
board::die(node_init_res);
|
||||
}
|
||||
|
||||
/*
|
||||
* Waiting for a dynamic node ID allocation
|
||||
*/
|
||||
performDynamicNodeIDAllocation();
|
||||
|
||||
/*
|
||||
* Time synchronizer
|
||||
*/
|
||||
static uavcan::GlobalTimeSyncSlave time_sync_slave(getNode());
|
||||
{
|
||||
const int res = time_sync_slave.start();
|
||||
if (res < 0)
|
||||
{
|
||||
board::die(res);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Main loop
|
||||
*/
|
||||
lowsyslog("UAVCAN node started\n");
|
||||
getNode().setModeOperational();
|
||||
while (true)
|
||||
{
|
||||
const int spin_res = getNode().spin(uavcan::MonotonicDuration::fromMSec(5000));
|
||||
if (spin_res < 0)
|
||||
{
|
||||
lowsyslog("Spin failure: %i\n", spin_res);
|
||||
}
|
||||
|
||||
lowsyslog("Time sync master: %u\n", unsigned(time_sync_slave.getMasterNodeID().get()));
|
||||
|
||||
lowsyslog("Memory usage: free=%u used=%u worst=%u\n",
|
||||
getNode().getAllocator().getNumFreeBlocks(),
|
||||
getNode().getAllocator().getNumUsedBlocks(),
|
||||
getNode().getAllocator().getPeakNumUsedBlocks());
|
||||
|
||||
lowsyslog("CAN errors: %lu %lu\n",
|
||||
static_cast<unsigned long>(can.driver.getIface(0)->getErrorCount()),
|
||||
static_cast<unsigned long>(can.driver.getIface(1)->getErrorCount()));
|
||||
|
||||
#if !UAVCAN_TINY
|
||||
node.getLogger().setLevel(uavcan::protocol::debug::LogLevel::INFO);
|
||||
node.logInfo("app", "UTC %* sec, %* corr, %* jumps",
|
||||
uavcan_stm32::clock::getUtc().toMSec() / 1000,
|
||||
uavcan_stm32::clock::getUtcSpeedCorrectionPPM(),
|
||||
uavcan_stm32::clock::getUtcAjdustmentJumpCount());
|
||||
#endif
|
||||
}
|
||||
return msg_t();
|
||||
}
|
||||
} uavcan_node_thread;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
int main()
|
||||
{
|
||||
app::init();
|
||||
|
||||
lowsyslog("Starting the UAVCAN thread\n");
|
||||
app::uavcan_node_thread.start(LOWPRIO);
|
||||
|
||||
while (true)
|
||||
{
|
||||
for (int i = 0; i < 200; i++)
|
||||
{
|
||||
board::setLed(app::can.driver.hadActivity());
|
||||
::usleep(25000);
|
||||
}
|
||||
|
||||
const uavcan::UtcTime utc = uavcan_stm32::clock::getUtc();
|
||||
lowsyslog("UTC %lu sec Rate corr: %fPPM Jumps: %lu Locked: %i\n",
|
||||
static_cast<unsigned long>(utc.toMSec() / 1000),
|
||||
uavcan_stm32::clock::getUtcRateCorrectionPPM(),
|
||||
uavcan_stm32::clock::getUtcJumpCount(),
|
||||
int(uavcan_stm32::clock::isUtcLocked()));
|
||||
}
|
||||
}
|
||||
@ -1,77 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Pavel Kirienko <pavel.kirienko@gmail.com>
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/// Assert is needed for STM32 SPL (if it is being used, that is)
|
||||
#include <assert.h>
|
||||
#define assert_param(x) assert(x)
|
||||
|
||||
#define STM32_LSECLK 32768
|
||||
#define STM32_HSECLK 25000000
|
||||
|
||||
#define STM32F10X_CL
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
// LED
|
||||
#define GPIO_PORT_LED GPIOB
|
||||
#define GPIO_PIN_LED 9
|
||||
|
||||
// GPIOD 10 is configured as OUTPUT, it is used as board reboot monitor.
|
||||
|
||||
/*
|
||||
* I/O ports initial setup, this configuration is established soon after reset
|
||||
* in the initialization code.
|
||||
*
|
||||
* The digits have the following meaning:
|
||||
* 0 - Analog input.
|
||||
* 1 - Push Pull output 10MHz.
|
||||
* 2 - Push Pull output 2MHz.
|
||||
* 3 - Push Pull output 50MHz.
|
||||
* 4 - Digital input.
|
||||
* 5 - Open Drain output 10MHz.
|
||||
* 6 - Open Drain output 2MHz.
|
||||
* 7 - Open Drain output 50MHz.
|
||||
* 8 - Digital input with PullUp or PullDown resistor depending on ODR.
|
||||
* 9 - Alternate Push Pull output 10MHz.
|
||||
* A - Alternate Push Pull output 2MHz.
|
||||
* B - Alternate Push Pull output 50MHz.
|
||||
* C - Reserved.
|
||||
* D - Alternate Open Drain output 10MHz.
|
||||
* E - Alternate Open Drain output 2MHz.
|
||||
* F - Alternate Open Drain output 50MHz.
|
||||
* Please refer to the STM32 Reference Manual for details.
|
||||
*/
|
||||
|
||||
#define VAL_GPIOACRL 0x88888888 // 7..0
|
||||
#define VAL_GPIOACRH 0x88888888 // 15..8
|
||||
#define VAL_GPIOAODR 0x00000000
|
||||
|
||||
#define VAL_GPIOBCRL 0x84488888 // CAN2 TX initialized as INPUT, it must be configured later!
|
||||
#define VAL_GPIOBCRH 0x88888828
|
||||
#define VAL_GPIOBODR 0x00000000
|
||||
|
||||
#define VAL_GPIOCCRL 0x88888888
|
||||
#define VAL_GPIOCCRH 0x88888888
|
||||
#define VAL_GPIOCODR 0x00000000
|
||||
|
||||
#define VAL_GPIODCRL 0x88b88844 // CAN1 TX initialized as INPUT, it must be configured later!
|
||||
#define VAL_GPIODCRH 0x88888288
|
||||
#define VAL_GPIODODR ((1 << 10))
|
||||
|
||||
#define VAL_GPIOECRL 0x88888888
|
||||
#define VAL_GPIOECRH 0x88888888
|
||||
#define VAL_GPIOEODR 0x00000000
|
||||
|
||||
#if !defined(_FROM_ASM_)
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void boardInit(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _FROM_ASM_ */
|
||||
@ -1,29 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Pavel Kirienko <pavel.kirienko@gmail.com>
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#define CH_FREQUENCY 1000
|
||||
|
||||
#define CH_USE_HEAP TRUE
|
||||
#define CH_USE_DYNAMIC FALSE
|
||||
|
||||
#if defined(DEBUG_BUILD) && DEBUG_BUILD
|
||||
# define CH_OPTIMIZE_SPEED FALSE
|
||||
# define CH_DBG_SYSTEM_STATE_CHECK TRUE
|
||||
# define CH_DBG_ENABLE_CHECKS TRUE
|
||||
# define CH_DBG_ENABLE_ASSERTS TRUE
|
||||
# define CH_DBG_ENABLE_STACK_CHECK TRUE
|
||||
# define CH_DBG_FILL_THREADS TRUE
|
||||
# define CH_DBG_THREADS_PROFILING TRUE
|
||||
#elif defined(RELEASE_BUILD) && RELEASE_BUILD
|
||||
# define CH_DBG_THREADS_PROFILING FALSE
|
||||
#else
|
||||
# error "Invalid configuration: Either DEBUG_BUILD or RELEASE_BUILD must be true"
|
||||
#endif
|
||||
|
||||
#define PORT_IDLE_THREAD_STACK_SIZE 64
|
||||
#define PORT_INT_REQUIRED_STACK 256
|
||||
|
||||
#include <zubax_chibios/sys/chconf_tail.h>
|
||||
@ -1,32 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Pavel Kirienko <pavel.kirienko@gmail.com>
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "mcuconf.h"
|
||||
|
||||
#define HAL_USE_TM TRUE
|
||||
#define HAL_USE_PAL TRUE
|
||||
#define HAL_USE_ADC FALSE
|
||||
#define HAL_USE_CAN FALSE
|
||||
#define HAL_USE_DAC FALSE
|
||||
#define HAL_USE_EXT FALSE
|
||||
#define HAL_USE_GPT FALSE
|
||||
#define HAL_USE_I2C FALSE
|
||||
#define HAL_USE_ICU FALSE
|
||||
#define HAL_USE_MAC FALSE
|
||||
#define HAL_USE_MMC_SPI FALSE
|
||||
#define HAL_USE_PWM FALSE
|
||||
#define HAL_USE_RTC FALSE
|
||||
#define HAL_USE_SDC FALSE
|
||||
#define HAL_USE_SERIAL TRUE
|
||||
#define HAL_USE_SERIAL_USB FALSE
|
||||
#define HAL_USE_SPI FALSE
|
||||
#define HAL_USE_UART FALSE
|
||||
#define HAL_USE_USB FALSE
|
||||
|
||||
#define SERIAL_DEFAULT_BITRATE 115200
|
||||
#define SERIAL_BUFFERS_SIZE 128
|
||||
|
||||
#include <zubax_chibios/sys/halconf_tail.h>
|
||||
@ -1,191 +0,0 @@
|
||||
/*
|
||||
* STM32F107 drivers configuration.
|
||||
* The following settings override the default settings present in
|
||||
* the various device driver implementation headers.
|
||||
* Note that the settings for each driver only have effect if the whole
|
||||
* driver is enabled in halconf.h.
|
||||
*
|
||||
* IRQ priorities:
|
||||
* 15...0 Lowest...Highest.
|
||||
*
|
||||
* DMA priorities:
|
||||
* 0...3 Lowest...Highest.
|
||||
*/
|
||||
|
||||
#define STM32F107_MCUCONF
|
||||
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define STM32_NO_INIT FALSE
|
||||
#define STM32_HSI_ENABLED TRUE
|
||||
#define STM32_LSI_ENABLED TRUE
|
||||
#define STM32_HSE_ENABLED TRUE
|
||||
#define STM32_LSE_ENABLED FALSE
|
||||
#define STM32_SW STM32_SW_PLL
|
||||
#define STM32_PLLSRC STM32_PLLSRC_PREDIV1
|
||||
#define STM32_PREDIV1SRC STM32_PREDIV1SRC_PLL2
|
||||
#define STM32_PREDIV1_VALUE 5
|
||||
#define STM32_PLLMUL_VALUE 9
|
||||
#define STM32_PREDIV2_VALUE 5
|
||||
#define STM32_PLL2MUL_VALUE 8
|
||||
#define STM32_PLL3MUL_VALUE 10
|
||||
#define STM32_HPRE STM32_HPRE_DIV1
|
||||
#define STM32_PPRE1 STM32_PPRE1_DIV2
|
||||
#define STM32_PPRE2 STM32_PPRE2_DIV2
|
||||
#define STM32_ADCPRE STM32_ADCPRE_DIV4
|
||||
#define STM32_OTG_CLOCK_REQUIRED FALSE
|
||||
#define STM32_OTGFSPRE STM32_OTGFSPRE_DIV3
|
||||
#define STM32_I2S_CLOCK_REQUIRED FALSE
|
||||
#define STM32_MCOSEL STM32_MCOSEL_PLL3
|
||||
#define STM32_RTCSEL STM32_RTCSEL_HSEDIV
|
||||
#define STM32_PVD_ENABLE FALSE
|
||||
#define STM32_PLS STM32_PLS_LEV0
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_USE_ADC1 FALSE
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY 2
|
||||
#define STM32_ADC_ADC1_IRQ_PRIORITY 6
|
||||
|
||||
/*
|
||||
* CAN driver system settings.
|
||||
*/
|
||||
#define STM32_CAN_USE_CAN1 FALSE
|
||||
#define STM32_CAN_USE_CAN2 FALSE
|
||||
#define STM32_CAN_CAN1_IRQ_PRIORITY 4
|
||||
#define STM32_CAN_CAN2_IRQ_PRIORITY 4
|
||||
|
||||
/*
|
||||
* EXT driver system settings.
|
||||
*/
|
||||
#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI17_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
|
||||
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM1 FALSE
|
||||
#define STM32_GPT_USE_TIM2 FALSE
|
||||
#define STM32_GPT_USE_TIM3 FALSE
|
||||
#define STM32_GPT_USE_TIM4 FALSE
|
||||
#define STM32_GPT_USE_TIM5 FALSE
|
||||
#define STM32_GPT_USE_TIM8 FALSE
|
||||
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM5_IRQ_PRIORITY 7
|
||||
#define STM32_GPT_TIM8_IRQ_PRIORITY 7
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 FALSE
|
||||
#define STM32_I2C_USE_I2C2 FALSE
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY 3
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY 3
|
||||
#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt()
|
||||
#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt()
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM1 FALSE
|
||||
#define STM32_ICU_USE_TIM2 FALSE
|
||||
#define STM32_ICU_USE_TIM3 FALSE
|
||||
#define STM32_ICU_USE_TIM4 FALSE
|
||||
#define STM32_ICU_USE_TIM5 FALSE
|
||||
#define STM32_ICU_USE_TIM8 FALSE
|
||||
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
|
||||
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
|
||||
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
|
||||
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
|
||||
#define STM32_ICU_TIM5_IRQ_PRIORITY 7
|
||||
#define STM32_ICU_TIM8_IRQ_PRIORITY 7
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_ADVANCED FALSE
|
||||
#define STM32_PWM_USE_TIM1 TRUE
|
||||
#define STM32_PWM_USE_TIM2 FALSE
|
||||
#define STM32_PWM_USE_TIM3 FALSE
|
||||
#define STM32_PWM_USE_TIM4 FALSE
|
||||
#define STM32_PWM_USE_TIM5 FALSE
|
||||
#define STM32_PWM_USE_TIM8 FALSE
|
||||
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM5_IRQ_PRIORITY 7
|
||||
#define STM32_PWM_TIM8_IRQ_PRIORITY 7
|
||||
|
||||
/*
|
||||
* RTC driver system settings.
|
||||
*/
|
||||
#define STM32_RTC_IRQ_PRIORITY 15
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 FALSE
|
||||
#define STM32_SERIAL_USE_USART2 TRUE
|
||||
#define STM32_SERIAL_USE_USART3 FALSE
|
||||
#define STM32_SERIAL_USE_UART4 FALSE
|
||||
#define STM32_SERIAL_USE_UART5 FALSE
|
||||
#define STM32_SERIAL_USART1_PRIORITY 12
|
||||
#define STM32_SERIAL_USART2_PRIORITY 12
|
||||
#define STM32_SERIAL_USART3_PRIORITY 12
|
||||
#define STM32_SERIAL_UART4_PRIORITY 12
|
||||
#define STM32_SERIAL_UART5_PRIORITY 12
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 FALSE
|
||||
#define STM32_SPI_USE_SPI2 FALSE
|
||||
#define STM32_SPI_USE_SPI3 FALSE
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY 1
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 FALSE
|
||||
#define STM32_UART_USE_USART2 FALSE
|
||||
#define STM32_UART_USE_USART3 FALSE
|
||||
#define STM32_UART_USART1_IRQ_PRIORITY 12
|
||||
#define STM32_UART_USART2_IRQ_PRIORITY 12
|
||||
#define STM32_UART_USART3_IRQ_PRIORITY 12
|
||||
#define STM32_UART_USART1_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART2_DMA_PRIORITY 0
|
||||
#define STM32_UART_USART3_DMA_PRIORITY 0
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_OTG1 FALSE
|
||||
#define STM32_USB_OTG1_IRQ_PRIORITY 14
|
||||
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
|
||||
#define STM32_USB_OTG_THREAD_PRIO LOWPRIO
|
||||
#define STM32_USB_OTG_THREAD_STACK_SIZE 128
|
||||
#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
|
||||
Loading…
x
Reference in New Issue
Block a user