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Costmet clean, whitespace, carriage-return removal

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git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4274 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
2012-01-06 23:41:20 +00:00
parent 9fad100973
commit cdc1e0760e
14 changed files with 459 additions and 461 deletions
Download Patch File Download Diff File Expand all files Collapse all files
nuttx/arch/mips/src/pic32mx/excptmacros.h
+1 -1
View File
@@ -356,7 +356,7 @@
mtc0 k0, MIPS32_CP0_STATUS mtc0 k0, MIPS32_CP0_STATUS
ehb ehb
mtc0 k1, MIPS32_CP0_EPC mtc0 k1, MIPS32_CP0_EPC
eret eret
nop nop
.endm .endm
nuttx/arch/mips/src/pic32mx/pic32mx-decodeirq.c
+2 -2
View File
@@ -132,7 +132,7 @@ uint32_t *pic32mx_decodeirq(uint32_t *regs)
*/ */
irq = ((regval) & INT_INTSTAT_VEC_MASK) >> INT_INTSTAT_VEC_SHIFT; irq = ((regval) & INT_INTSTAT_VEC_MASK) >> INT_INTSTAT_VEC_SHIFT;
/* Deliver the IRQ */ /* Deliver the IRQ */
irq_dispatch(irq, regs); irq_dispatch(irq, regs);
@@ -153,7 +153,7 @@ uint32_t *pic32mx_decodeirq(uint32_t *regs)
#ifdef CONFIG_PIC32MX_NESTED_INTERRUPTS #ifdef CONFIG_PIC32MX_NESTED_INTERRUPTS
/* I think there are some task switching issues here. You should not /* I think there are some task switching issues here. You should not
* enable nested interrupts unless you are ready to deal with the * enable nested interrupts unless you are ready to deal with the
* complexities of nested context switching. The logic here is probably * complexities of nested context switching. The logic here is probably
* insufficient. * insufficient.
*/ */
nuttx/arch/mips/src/pic32mx/pic32mx-gpio.c
+2 -2
View File
@@ -120,10 +120,10 @@ static inline unsigned int pic32mx_pinno(uint16_t pinset)
* Description: * Description:
* Configure a GPIO pin based on bit-encoded description of the pin (the * Configure a GPIO pin based on bit-encoded description of the pin (the
* interrupt will be configured when pic32mx_attach() is called. * interrupt will be configured when pic32mx_attach() is called.
* *
* Returned Value: * Returned Value:
* OK on success; negated errno on failure. * OK on success; negated errno on failure.
* *
****************************************************************************/ ****************************************************************************/
int pic32mx_configgpio(uint16_t cfgset) int pic32mx_configgpio(uint16_t cfgset)
nuttx/arch/mips/src/pic32mx/pic32mx-gpioirq.c
+4 -4
View File
@@ -188,13 +188,13 @@ void pic32mx_gpioirqinitialize(void)
* When an interrupt occurs, it is due to a change on the GPIO input pin. * When an interrupt occurs, it is due to a change on the GPIO input pin.
* In that case, all attached handlers will be called. Each handler must * In that case, all attached handlers will be called. Each handler must
* maintain state and determine if the unlying GPIO input value changed. * maintain state and determine if the unlying GPIO input value changed.
* *
* Parameters: * Parameters:
* - pinset: GPIO pin configuration * - pinset: GPIO pin configuration
* - cn: The change notification number associated with the pin. * - cn: The change notification number associated with the pin.
* - handler: Interrupt handler (may be NULL to detach) * - handler: Interrupt handler (may be NULL to detach)
* *
* Returns: * Returns:
* The previous value of the interrupt handler function pointer. This * The previous value of the interrupt handler function pointer. This
* value may, for example, be used to restore the previous handler when * value may, for example, be used to restore the previous handler when
* multiple handlers are used. * multiple handlers are used.
@@ -228,7 +228,7 @@ xcpt_t pic32mx_gpioattach(uint32_t pinset, unsigned int cn, xcpt_t handler)
pic32mx_configgpio(pinset); pic32mx_configgpio(pinset);
/* Pull-up requested? */ /* Pull-up requested? */
if (pic32mx_pullup(pinset)) if (pic32mx_pullup(pinset))
{ {
putreg32(1 << cn, PIC32MX_IOPORT_CNPUESET); putreg32(1 << cn, PIC32MX_IOPORT_CNPUESET);
nuttx/arch/mips/src/pic32mx/pic32mx-head.S
+4 -5
View File
@@ -158,7 +158,6 @@ __reset:
nop nop
.end __reset .end __reset
/**************************************************************************** /****************************************************************************
* Name: _gen_exception * Name: _gen_exception
* *
@@ -218,7 +217,7 @@ _ebase_exception:
* *
* Description: * Description:
* Boot Exception Vector Handler. Jumps to _exception_handler. This * Boot Exception Vector Handler. Jumps to _exception_handler. This
* vector will be positioned at 0xbfc00380 by the linker script. * vector will be positioned at 0xbfc00380 by the linker script.
* *
* Input Parameters: * Input Parameters:
* None * None
@@ -242,7 +241,7 @@ _bev_exception:
* *
* Description: * Description:
* Interrupt Exception Vector Handler. Jumps to _int_handler. This * Interrupt Exception Vector Handler. Jumps to _int_handler. This
* vector will be positioned at 0xbfc00400 by the linker script. * vector will be positioned at 0xbfc00400 by the linker script.
* *
* Input Parameters: * Input Parameters:
* None * None
@@ -379,7 +378,7 @@ __start:
la t1, _sramfunc la t1, _sramfunc
la t2, _eramfunc la t2, _eramfunc
.Lramfuncloop: .Lramfuncloop:
lw t3,(t0) lw t3,(t0)
sw t3,(t1) sw t3,(t1)
addu t0,4 addu t0,4
@@ -635,7 +634,7 @@ devconfig0:
/* g_instackbase is a pointer to the final, aligned word of the interrupt /* g_instackbase is a pointer to the final, aligned word of the interrupt
* stack. * stack.
*/ */
.sdata .sdata
.type g_intstackbase, object .type g_intstackbase, object
g_intstackbase: g_intstackbase:
nuttx/arch/mips/src/pic32mx/pic32mx-internal.h
+7 -7
View File
@@ -247,10 +247,10 @@ EXTERN uint32_t *pic32mx_exception(uint32_t *regs);
* Description: * Description:
* Configure a GPIO pin based on bit-encoded description of the pin (the interrupt * Configure a GPIO pin based on bit-encoded description of the pin (the interrupt
* will be configured when pic32mx_attach() is called). * will be configured when pic32mx_attach() is called).
* *
* Returned Value: * Returned Value:
* OK on success; negated errno on failure. * OK on success; negated errno on failure.
* *
************************************************************************************/ ************************************************************************************/
EXTERN int pic32mx_configgpio(uint16_t cfgset); EXTERN int pic32mx_configgpio(uint16_t cfgset);
@@ -303,13 +303,13 @@ EXTERN void pic32mx_gpioirqinitialize(void);
* When an interrupt occurs, it is due to a change on the GPIO input pin. In that * When an interrupt occurs, it is due to a change on the GPIO input pin. In that
* case, all attached handlers will be called. Each handler must maintain state * case, all attached handlers will be called. Each handler must maintain state
* and determine if the unlying GPIO input value changed. * and determine if the unlying GPIO input value changed.
* *
* Parameters: * Parameters:
* - pinset: GPIO pin configuration * - pinset: GPIO pin configuration
* - cn: The change notification number associated with the pin * - cn: The change notification number associated with the pin
* - handler: Interrupt handler (may be NULL to detach) * - handler: Interrupt handler (may be NULL to detach)
* *
* Returns: * Returns:
* The previous value of the interrupt handler function pointer. This value may, * The previous value of the interrupt handler function pointer. This value may,
* for example, be used to restore the previous handler when multiple handlers are * for example, be used to restore the previous handler when multiple handlers are
* used. * used.
@@ -370,7 +370,7 @@ EXTERN void pic32mx_dumpgpio(uint32_t pinset, const char *msg);
* Description: * Description:
* These external functions must be provided by board-specific logic. They are * These external functions must be provided by board-specific logic. They are
* implementations of the select, status, and cmddata methods of the SPI interface * implementations of the select, status, and cmddata methods of the SPI interface
* defined by struct spi_ops_s (see include/nuttx/spi.h). All other methods * defined by struct spi_ops_s (see include/nuttx/spi.h). All other methods
* including up_spiinitialize()) are provided by common PIC32MX logic. To use * including up_spiinitialize()) are provided by common PIC32MX logic. To use
* this common SPI logic on your board: * this common SPI logic on your board:
* *
@@ -386,7 +386,7 @@ EXTERN void pic32mx_dumpgpio(uint32_t pinset, const char *msg);
* 3. Add a call to up_spiinitialize() in your low level application * 3. Add a call to up_spiinitialize() in your low level application
* initialization logic * initialization logic
* 4. The handle returned by up_spiinitialize() may then be used to bind the * 4. The handle returned by up_spiinitialize() may then be used to bind the
* SPI driver to higher level logic (e.g., calling * SPI driver to higher level logic (e.g., calling
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to * mmcsd_spislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver). * the SPI MMC/SD driver).
* *
nuttx/arch/mips/src/pic32mx/pic32mx-irq.c
+2 -2
View File
@@ -127,7 +127,7 @@ void up_irqinitialize(void)
/* Set the IV bit in the CAUSE register */ /* Set the IV bit in the CAUSE register */
regval = cp0_getcause(); regval = cp0_getcause();
regval |= CP0_CAUSE_IV; regval |= CP0_CAUSE_IV;
cp0_putcause(regval); cp0_putcause(regval);
/* Clear the EXL and BEV bits in the STATUS register */ /* Clear the EXL and BEV bits in the STATUS register */
@@ -145,7 +145,7 @@ void up_irqinitialize(void)
#endif #endif
/* Initialize GPIO change notification handling */ /* Initialize GPIO change notification handling */
#ifdef CONFIG_GPIO_IRQ #ifdef CONFIG_GPIO_IRQ
pic32mx_gpioirqinitialize(); pic32mx_gpioirqinitialize();
#endif #endif
nuttx/arch/mips/src/pic32mx/pic32mx-lowconsole.c
+1 -1
View File
@@ -175,7 +175,7 @@ static void pic32mx_uartsetbaud(uintptr_t uart_base, uint32_t baudrate)
/* We want the largest value of BRG divisor possible (for the best accuracy). /* We want the largest value of BRG divisor possible (for the best accuracy).
* Subject to BRG <= 65536. * Subject to BRG <= 65536.
*/ */
tmp = BOARD_PBCLOCK / baudrate; tmp = BOARD_PBCLOCK / baudrate;
/* Try BRGH=1 first. This will select the 4x divisor and will produce the /* Try BRGH=1 first. This will select the 4x divisor and will produce the
nuttx/arch/mips/src/pic32mx/pic32mx-lowinit.c
+3 -3
View File
@@ -115,9 +115,9 @@ static inline void pic32mx_waitstates(void)
/* Disable DRM wait states */ /* Disable DRM wait states */
putreg32(BMX_CON_BMXWSDRM, PIC32MX_BMX_CONCLR); putreg32(BMX_CON_BMXWSDRM, PIC32MX_BMX_CONCLR);
/* Configure pre-fetch cache FLASH wait states */ /* Configure pre-fetch cache FLASH wait states */
residual = BOARD_CPU_CLOCK; residual = BOARD_CPU_CLOCK;
nwaits = 0; nwaits = 0;
@@ -153,7 +153,7 @@ static inline void pic32mx_cache(void)
regval = getreg32(PIC32MX_CHE_CON); regval = getreg32(PIC32MX_CHE_CON);
regval |= CHE_CON_PREFEN_ALL; regval |= CHE_CON_PREFEN_ALL;
putreg32(regval, PIC32MX_CHE_CON); putreg32(regval, PIC32MX_CHE_CON);
/* Enable cache on KSEG 0 in the CP0 CONFIG register*/ /* Enable cache on KSEG 0 in the CP0 CONFIG register*/
asm("\tmfc0 %0,$16,0\n" : "=r"(regval)); asm("\tmfc0 %0,$16,0\n" : "=r"(regval));
nuttx/arch/mips/src/pic32mx/pic32mx-pmp.h
+241 -241
View File
@@ -1,241 +1,241 @@
/************************************************************************************ /************************************************************************************
* arch/mips/src/pic32mx/pic32mx-pmp.h * arch/mips/src/pic32mx/pic32mx-pmp.h
* *
* Copyright (C) 2011 Gregory Nutt. All rights reserved. * Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr> * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
* are met: * are met:
* *
* 1. Redistributions of source code must retain the above copyright * 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer. * notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright * 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in * notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the * the documentation and/or other materials provided with the
* distribution. * distribution.
* 3. Neither the name NuttX nor the names of its contributors may be * 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software * used to endorse or promote products derived from this software
* without specific prior written permission. * without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
* *
************************************************************************************/ ************************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_PMP_H #ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_PMP_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_PMP_H #define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_PMP_H
/************************************************************************************ /************************************************************************************
* Included Files * Included Files
************************************************************************************/ ************************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include "pic32mx-memorymap.h" #include "pic32mx-memorymap.h"
/************************************************************************************ /************************************************************************************
* Pre-Processor Definitions * Pre-Processor Definitions
************************************************************************************/ ************************************************************************************/
/* Register Offsets *****************************************************************/ /* Register Offsets *****************************************************************/
#define PIC32MX_PMP_CON_OFFSET 0x0000 /* Parallel Port Control Register */ #define PIC32MX_PMP_CON_OFFSET 0x0000 /* Parallel Port Control Register */
#define PIC32MX_PMP_CONCLR_OFFSET 0x0000 /* Parallel Port Control Clear Register */ #define PIC32MX_PMP_CONCLR_OFFSET 0x0000 /* Parallel Port Control Clear Register */
#define PIC32MX_PMP_CONSET_OFFSET 0x0000 /* Parallel Port Control Set Register */ #define PIC32MX_PMP_CONSET_OFFSET 0x0000 /* Parallel Port Control Set Register */
#define PIC32MX_PMP_CONINV_OFFSET 0x0000 /* Parallel Port Control Invert Register */ #define PIC32MX_PMP_CONINV_OFFSET 0x0000 /* Parallel Port Control Invert Register */
#define PIC32MX_PMP_MODE_OFFSET 0x0000 /* Parallel Port Mode Register */ #define PIC32MX_PMP_MODE_OFFSET 0x0000 /* Parallel Port Mode Register */
#define PIC32MX_PMP_MODECLR_OFFSET 0x0000 /* Parallel Port Mode Clear Register */ #define PIC32MX_PMP_MODECLR_OFFSET 0x0000 /* Parallel Port Mode Clear Register */
#define PIC32MX_PMP_MODESET_OFFSET 0x0000 /* Parallel Port Mode Set Register */ #define PIC32MX_PMP_MODESET_OFFSET 0x0000 /* Parallel Port Mode Set Register */
#define PIC32MX_PMP_MODEINV_OFFSET 0x0000 /* Parallel Port Mode Invert Register */ #define PIC32MX_PMP_MODEINV_OFFSET 0x0000 /* Parallel Port Mode Invert Register */
#define PIC32MX_PMP_ADDR_OFFSET 0x0000 /* Parallel Port Address Register */ #define PIC32MX_PMP_ADDR_OFFSET 0x0000 /* Parallel Port Address Register */
#define PIC32MX_PMP_ADDRCLR_OFFSET 0x0000 /* Parallel Port Address Clear Register */ #define PIC32MX_PMP_ADDRCLR_OFFSET 0x0000 /* Parallel Port Address Clear Register */
#define PIC32MX_PMP_ADDRSET_OFFSET 0x0000 /* Parallel Port Address Set Register */ #define PIC32MX_PMP_ADDRSET_OFFSET 0x0000 /* Parallel Port Address Set Register */
#define PIC32MX_PMP_ADDRINV_OFFSET 0x0000 /* Parallel Port Address Invert Register */ #define PIC32MX_PMP_ADDRINV_OFFSET 0x0000 /* Parallel Port Address Invert Register */
#define PIC32MX_PMP_DOUT_OFFSET 0x0000 /* Parallel Port Data Output Register */ #define PIC32MX_PMP_DOUT_OFFSET 0x0000 /* Parallel Port Data Output Register */
#define PIC32MX_PMP_DOUTCLR_OFFSET 0x0000 /* Parallel Port Data Output Clear Register */ #define PIC32MX_PMP_DOUTCLR_OFFSET 0x0000 /* Parallel Port Data Output Clear Register */
#define PIC32MX_PMP_DOUTSET_OFFSET 0x0000 /* Parallel Port Data Output Set Register */ #define PIC32MX_PMP_DOUTSET_OFFSET 0x0000 /* Parallel Port Data Output Set Register */
#define PIC32MX_PMP_DOUTINV_OFFSET 0x0000 /* Parallel Port Data Output Invert Register */ #define PIC32MX_PMP_DOUTINV_OFFSET 0x0000 /* Parallel Port Data Output Invert Register */
#define PIC32MX_PMP_DIN_OFFSET 0x0000 /* Parallel Port Data Input Register */ #define PIC32MX_PMP_DIN_OFFSET 0x0000 /* Parallel Port Data Input Register */
#define PIC32MX_PMP_DINCLR_OFFSET 0x0000 /* Parallel Port Data Input Clear Register */ #define PIC32MX_PMP_DINCLR_OFFSET 0x0000 /* Parallel Port Data Input Clear Register */
#define PIC32MX_PMP_DINSET_OFFSET 0x0000 /* Parallel Port Data Input Set Register */ #define PIC32MX_PMP_DINSET_OFFSET 0x0000 /* Parallel Port Data Input Set Register */
#define PIC32MX_PMP_DININV_OFFSET 0x0000 /* Parallel Port Data Input Invert Register */ #define PIC32MX_PMP_DININV_OFFSET 0x0000 /* Parallel Port Data Input Invert Register */
#define PIC32MX_PMP_AEN_OFFSET 0x0000 /* Parallel Port Pin Enable Register */ #define PIC32MX_PMP_AEN_OFFSET 0x0000 /* Parallel Port Pin Enable Register */
#define PIC32MX_PMP_AENCLR_OFFSET 0x0000 /* Parallel Port Pin Enable Clear Register */ #define PIC32MX_PMP_AENCLR_OFFSET 0x0000 /* Parallel Port Pin Enable Clear Register */
#define PIC32MX_PMP_AENSET_OFFSET 0x0000 /* Parallel Port Pin Enable Set Register */ #define PIC32MX_PMP_AENSET_OFFSET 0x0000 /* Parallel Port Pin Enable Set Register */
#define PIC32MX_PMP_AENINV_OFFSET 0x0000 /* Parallel Port Pin Enable Invert Register */ #define PIC32MX_PMP_AENINV_OFFSET 0x0000 /* Parallel Port Pin Enable Invert Register */
#define PIC32MX_PMP_STAT_OFFSET 0x0000 /* Parallel Port Status Register */ #define PIC32MX_PMP_STAT_OFFSET 0x0000 /* Parallel Port Status Register */
#define PIC32MX_PMP_STATCLR_OFFSET 0x0000 /* Parallel Port Status Clear Register */ #define PIC32MX_PMP_STATCLR_OFFSET 0x0000 /* Parallel Port Status Clear Register */
#define PIC32MX_PMP_STATSET_OFFSET 0x0000 /* Parallel Port Status Set Register */ #define PIC32MX_PMP_STATSET_OFFSET 0x0000 /* Parallel Port Status Set Register */
#define PIC32MX_PMP_STATINV_OFFSET 0x0000 /* Parallel Port Status Invert Register */ #define PIC32MX_PMP_STATINV_OFFSET 0x0000 /* Parallel Port Status Invert Register */
/* Register Addresses ***************************************************************/ /* Register Addresses ***************************************************************/
#define PIC32MX_PMP_CON (PIC32MX_PMP_K1BASE+PIC32MX_PMP_CON_OFFSET) #define PIC32MX_PMP_CON (PIC32MX_PMP_K1BASE+PIC32MX_PMP_CON_OFFSET)
#define PIC32MX_PMP_CONCLR (PIC32MX_PMP_K1BASE+PIC32MX_PMP_CONCLR_OFFSET) #define PIC32MX_PMP_CONCLR (PIC32MX_PMP_K1BASE+PIC32MX_PMP_CONCLR_OFFSET)
#define PIC32MX_PMP_CONSET (PIC32MX_PMP_K1BASE+PIC32MX_PMP_CONSET_OFFSET) #define PIC32MX_PMP_CONSET (PIC32MX_PMP_K1BASE+PIC32MX_PMP_CONSET_OFFSET)
#define PIC32MX_PMP_CONINV (PIC32MX_PMP_K1BASE+PIC32MX_PMP_CONINV_OFFSET) #define PIC32MX_PMP_CONINV (PIC32MX_PMP_K1BASE+PIC32MX_PMP_CONINV_OFFSET)
#define PIC32MX_PMP_MODE (PIC32MX_PMP_K1BASE+PIC32MX_PMP_MODE_OFFSET) #define PIC32MX_PMP_MODE (PIC32MX_PMP_K1BASE+PIC32MX_PMP_MODE_OFFSET)
#define PIC32MX_PMP_MODECLR (PIC32MX_PMP_K1BASE+PIC32MX_PMP_MODECLR_OFFSET) #define PIC32MX_PMP_MODECLR (PIC32MX_PMP_K1BASE+PIC32MX_PMP_MODECLR_OFFSET)
#define PIC32MX_PMP_MODESET (PIC32MX_PMP_K1BASE+PIC32MX_PMP_MODESET_OFFSET) #define PIC32MX_PMP_MODESET (PIC32MX_PMP_K1BASE+PIC32MX_PMP_MODESET_OFFSET)
#define PIC32MX_PMP_MODEINV (PIC32MX_PMP_K1BASE+PIC32MX_PMP_MODEINV_OFFSET) #define PIC32MX_PMP_MODEINV (PIC32MX_PMP_K1BASE+PIC32MX_PMP_MODEINV_OFFSET)
#define PIC32MX_PMP_ADDR (PIC32MX_PMP_K1BASE+PIC32MX_PMP_ADDR_OFFSET) #define PIC32MX_PMP_ADDR (PIC32MX_PMP_K1BASE+PIC32MX_PMP_ADDR_OFFSET)
#define PIC32MX_PMP_ADDRCLR (PIC32MX_PMP_K1BASE+PIC32MX_PMP_ADDRCLR_OFFSET) #define PIC32MX_PMP_ADDRCLR (PIC32MX_PMP_K1BASE+PIC32MX_PMP_ADDRCLR_OFFSET)
#define PIC32MX_PMP_ADDRSET (PIC32MX_PMP_K1BASE+PIC32MX_PMP_ADDRSET_OFFSET) #define PIC32MX_PMP_ADDRSET (PIC32MX_PMP_K1BASE+PIC32MX_PMP_ADDRSET_OFFSET)
#define PIC32MX_PMP_ADDRINV (PIC32MX_PMP_K1BASE+PIC32MX_PMP_ADDRINV_OFFSET) #define PIC32MX_PMP_ADDRINV (PIC32MX_PMP_K1BASE+PIC32MX_PMP_ADDRINV_OFFSET)
#define PIC32MX_PMP_DOUT (PIC32MX_PMP_K1BASE+PIC32MX_PMP_DOUT_OFFSET) #define PIC32MX_PMP_DOUT (PIC32MX_PMP_K1BASE+PIC32MX_PMP_DOUT_OFFSET)
#define PIC32MX_PMP_DOUTCLR (PIC32MX_PMP_K1BASE+PIC32MX_PMP_DOUTCLR_OFFSET) #define PIC32MX_PMP_DOUTCLR (PIC32MX_PMP_K1BASE+PIC32MX_PMP_DOUTCLR_OFFSET)
#define PIC32MX_PMP_DOUTSET (PIC32MX_PMP_K1BASE+PIC32MX_PMP_DOUTSET_OFFSET) #define PIC32MX_PMP_DOUTSET (PIC32MX_PMP_K1BASE+PIC32MX_PMP_DOUTSET_OFFSET)
#define PIC32MX_PMP_DOUTINV (PIC32MX_PMP_K1BASE+PIC32MX_PMP_DOUTINV_OFFSET) #define PIC32MX_PMP_DOUTINV (PIC32MX_PMP_K1BASE+PIC32MX_PMP_DOUTINV_OFFSET)
#define PIC32MX_PMP_DIN (PIC32MX_PMP_K1BASE+PIC32MX_PMP_DIN_OFFSET) #define PIC32MX_PMP_DIN (PIC32MX_PMP_K1BASE+PIC32MX_PMP_DIN_OFFSET)
#define PIC32MX_PMP_DINCLR (PIC32MX_PMP_K1BASE+PIC32MX_PMP_DINCLR_OFFSET) #define PIC32MX_PMP_DINCLR (PIC32MX_PMP_K1BASE+PIC32MX_PMP_DINCLR_OFFSET)
#define PIC32MX_PMP_DINSET (PIC32MX_PMP_K1BASE+PIC32MX_PMP_DINSET_OFFSET) #define PIC32MX_PMP_DINSET (PIC32MX_PMP_K1BASE+PIC32MX_PMP_DINSET_OFFSET)
#define PIC32MX_PMP_DININV (PIC32MX_PMP_K1BASE+PIC32MX_PMP_DININV_OFFSET) #define PIC32MX_PMP_DININV (PIC32MX_PMP_K1BASE+PIC32MX_PMP_DININV_OFFSET)
#define PIC32MX_PMP_AEN (PIC32MX_PMP_K1BASE+PIC32MX_PMP_AEN_OFFSET) #define PIC32MX_PMP_AEN (PIC32MX_PMP_K1BASE+PIC32MX_PMP_AEN_OFFSET)
#define PIC32MX_PMP_AENCLR (PIC32MX_PMP_K1BASE+PIC32MX_PMP_AENCLR_OFFSET) #define PIC32MX_PMP_AENCLR (PIC32MX_PMP_K1BASE+PIC32MX_PMP_AENCLR_OFFSET)
#define PIC32MX_PMP_AENSET (PIC32MX_PMP_K1BASE+PIC32MX_PMP_AENSET_OFFSET) #define PIC32MX_PMP_AENSET (PIC32MX_PMP_K1BASE+PIC32MX_PMP_AENSET_OFFSET)
#define PIC32MX_PMP_AENINV (PIC32MX_PMP_K1BASE+PIC32MX_PMP_AENINV_OFFSET) #define PIC32MX_PMP_AENINV (PIC32MX_PMP_K1BASE+PIC32MX_PMP_AENINV_OFFSET)
#define PIC32MX_PMP_STAT (PIC32MX_PMP_K1BASE+PIC32MX_PMP_STAT_OFFSET) #define PIC32MX_PMP_STAT (PIC32MX_PMP_K1BASE+PIC32MX_PMP_STAT_OFFSET)
#define PIC32MX_PMP_STATCLR (PIC32MX_PMP_K1BASE+PIC32MX_PMP_STATCLR_OFFSET) #define PIC32MX_PMP_STATCLR (PIC32MX_PMP_K1BASE+PIC32MX_PMP_STATCLR_OFFSET)
#define PIC32MX_PMP_STATSET (PIC32MX_PMP_K1BASE+PIC32MX_PMP_STATSET_OFFSET) #define PIC32MX_PMP_STATSET (PIC32MX_PMP_K1BASE+PIC32MX_PMP_STATSET_OFFSET)
#define PIC32MX_PMP_STATINV (PIC32MX_PMP_K1BASE+PIC32MX_PMP_STATINV_OFFSET) #define PIC32MX_PMP_STATINV (PIC32MX_PMP_K1BASE+PIC32MX_PMP_STATINV_OFFSET)
/* Register Bit-Field Definitions ***************************************************/ /* Register Bit-Field Definitions ***************************************************/
/* Parallel Port Control Register */ /* Parallel Port Control Register */
#define PMP_CON_RDSP (1 << 0) /* Bit 0: Read strobe polarity */ #define PMP_CON_RDSP (1 << 0) /* Bit 0: Read strobe polarity */
#define PMP_CON_WRSP (1 << 1) /* Bit 1: Write strobe polarity */ #define PMP_CON_WRSP (1 << 1) /* Bit 1: Write strobe polarity */
#define PMP_CON_CS1P (1 << 3) /* Bit 3: Chip select 0 polarity */ #define PMP_CON_CS1P (1 << 3) /* Bit 3: Chip select 0 polarity */
#define PMP_CON_CS2P (1 << 4) /* Bit 4: Chip select 1 polarity */ #define PMP_CON_CS2P (1 << 4) /* Bit 4: Chip select 1 polarity */
#define PMP_CON_ALP (1 << 5) /* Bit 5: Address latch polarity */ #define PMP_CON_ALP (1 << 5) /* Bit 5: Address latch polarity */
#define PMP_CON_CSF_SHIFT (6) /* Bits 6-7: Chip select function */ #define PMP_CON_CSF_SHIFT (6) /* Bits 6-7: Chip select function */
#define PMP_CON_CSF_MASK (3 << PMP_CON_CSF_SHIFT) #define PMP_CON_CSF_MASK (3 << PMP_CON_CSF_SHIFT)
#define PMP_CON_CSF_ADDR1415 (0 << PMP_CON_CSF_SHIFT) /* PMCS2/PMCS1 = address bits 15 and 14 */ #define PMP_CON_CSF_ADDR1415 (0 << PMP_CON_CSF_SHIFT) /* PMCS2/PMCS1 = address bits 15 and 14 */
#define PMP_CON_CSF_CS2ADDR14 (1 << PMP_CON_CSF_SHIFT) /* PMCS2 = Chip Select, PMCS1 = address bit 14 */ #define PMP_CON_CSF_CS2ADDR14 (1 << PMP_CON_CSF_SHIFT) /* PMCS2 = Chip Select, PMCS1 = address bit 14 */
#define PMP_CON_CSF_CS12 (2 << PMP_CON_CSF_SHIFT) /* PMCS2/PMCS1 = Chip Select */ #define PMP_CON_CSF_CS12 (2 << PMP_CON_CSF_SHIFT) /* PMCS2/PMCS1 = Chip Select */
#define PMP_CON_PTRDEN (1 << 8) /* Bit 8: Read/write strobe port enable */ #define PMP_CON_PTRDEN (1 << 8) /* Bit 8: Read/write strobe port enable */
#define PMP_CON_PTWREN (1 << 9) /* Bit 9: Write enable strobe port enable */ #define PMP_CON_PTWREN (1 << 9) /* Bit 9: Write enable strobe port enable */
#define PMP_CON_PMPTTL (1 << 10) /* Bit 10: PMP module TTL input buffer select */ #define PMP_CON_PMPTTL (1 << 10) /* Bit 10: PMP module TTL input buffer select */
#define PMP_CON_ADRMUX_SHIFT (11) /* Bits 11-12: Address/data multiplexing selection */ #define PMP_CON_ADRMUX_SHIFT (11) /* Bits 11-12: Address/data multiplexing selection */
#define PMP_CON_ADRMUX_MASK (3 << PMP_CON_ADRMUX_SHIFT) #define PMP_CON_ADRMUX_MASK (3 << PMP_CON_ADRMUX_SHIFT)
# define PMP_CON_ADRMUX_NONE (0 << PMP_CON_ADRMUX_SHIFT) /* Address and data appear separate */ # define PMP_CON_ADRMUX_NONE (0 << PMP_CON_ADRMUX_SHIFT) /* Address and data appear separate */
# define PMP_CON_ADRMUX_BYTE (1 << PMP_CON_ADRMUX_SHIFT) /* LS address are mux'ed on PMD 7:0 MS on PMA 15:8 */ # define PMP_CON_ADRMUX_BYTE (1 << PMP_CON_ADRMUX_SHIFT) /* LS address are mux'ed on PMD 7:0 MS on PMA 15:8 */
# define PMP_CON_ADRMUX_MUX8 (2 << PMP_CON_ADRMUX_SHIFT) /* Address mux'ed on PMD 7:0 */ # define PMP_CON_ADRMUX_MUX8 (2 << PMP_CON_ADRMUX_SHIFT) /* Address mux'ed on PMD 7:0 */
# define PMP_CON_ADRMUX_MUX16 (3 << PMP_CON_ADRMUX_SHIFT) /* Address mux'ed on PMD 15:0 */ # define PMP_CON_ADRMUX_MUX16 (3 << PMP_CON_ADRMUX_SHIFT) /* Address mux'ed on PMD 15:0 */
#define PMP_CON_SIDL (1 << 13) /* Bit 13: Stop in idle mode */ #define PMP_CON_SIDL (1 << 13) /* Bit 13: Stop in idle mode */
#define PMP_CON_FRZ (1 << 14) /* Bit 14: Freeze in debug exception mode */ #define PMP_CON_FRZ (1 << 14) /* Bit 14: Freeze in debug exception mode */
#define PMP_CON_ON (1 << 15) /* Bit 15: Parallel master port enable */ #define PMP_CON_ON (1 << 15) /* Bit 15: Parallel master port enable */
/* Parallel Port Mode Register */ /* Parallel Port Mode Register */
#define PMP_MODE_WAITE_SHIFT (0) /* Bits 0-1: Data hold after R/W strobe wait states */ #define PMP_MODE_WAITE_SHIFT (0) /* Bits 0-1: Data hold after R/W strobe wait states */
#define PMP_MODE_WAITE_MASK (3 << PMP_MODE_WAITE_SHIFT) #define PMP_MODE_WAITE_MASK (3 << PMP_MODE_WAITE_SHIFT)
# define PMP_MODE_WAITE_WR(n) ((n-1) << PMP_MODE_WAITE_SHIFT) /* Wait of n TPB n=1..4 */ # define PMP_MODE_WAITE_WR(n) ((n-1) << PMP_MODE_WAITE_SHIFT) /* Wait of n TPB n=1..4 */
# define PMP_MODE_WAITE_RD(n) ((n) << PMP_MODE_WAITE_SHIFT) /* Wait of n TPB n=0..3 */ # define PMP_MODE_WAITE_RD(n) ((n) << PMP_MODE_WAITE_SHIFT) /* Wait of n TPB n=0..3 */
#define PMP_MODE_WAITM_SHIFT (2) /* Bits 2-5: Data R/W strobe wait states */ #define PMP_MODE_WAITM_SHIFT (2) /* Bits 2-5: Data R/W strobe wait states */
#define PMP_MODE_WAITM_MASK (15 << PMP_MODE_WAITM_SHIFT) #define PMP_MODE_WAITM_MASK (15 << PMP_MODE_WAITM_SHIFT)
# define PMP_MODE_WAITM(n) ((n-1) << PMP_MODE_WAITM_SHIFT) /* Wait of n TPB n=1..16 */ # define PMP_MODE_WAITM(n) ((n-1) << PMP_MODE_WAITM_SHIFT) /* Wait of n TPB n=1..16 */
#define PMP_MODE_WAITB_SHIFT (6) /* Bits 6-7: Data setup to R/W strobe wait states */ #define PMP_MODE_WAITB_SHIFT (6) /* Bits 6-7: Data setup to R/W strobe wait states */
#define PMP_MODE_WAITB_MASK (3 << PMP_MODE_WAITB_SHIFT) #define PMP_MODE_WAITB_MASK (3 << PMP_MODE_WAITB_SHIFT)
# define PMP_MODE_WAITB_1TPB (0 << PMP_MODE_WAITB_SHIFT) /* Data wait of 1 TPB */ # define PMP_MODE_WAITB_1TPB (0 << PMP_MODE_WAITB_SHIFT) /* Data wait of 1 TPB */
# define PMP_MODE_WAITB_2TPB (1 << PMP_MODE_WAITB_SHIFT) /* Data wait of 2 TPB */ # define PMP_MODE_WAITB_2TPB (1 << PMP_MODE_WAITB_SHIFT) /* Data wait of 2 TPB */
# define PMP_MODE_WAITB_3TPB (2 << PMP_MODE_WAITB_SHIFT) /* Data wait of 3 TPB */ # define PMP_MODE_WAITB_3TPB (2 << PMP_MODE_WAITB_SHIFT) /* Data wait of 3 TPB */
# define PMP_MODE_WAITB_4TPB (3 << PMP_MODE_WAITB_SHIFT) /* Data wait of 4 TPB */ # define PMP_MODE_WAITB_4TPB (3 << PMP_MODE_WAITB_SHIFT) /* Data wait of 4 TPB */
#define PMP_MODE_MODE_SHIFT (8) /* Bits 8-9: Parallel port mode select */ #define PMP_MODE_MODE_SHIFT (8) /* Bits 8-9: Parallel port mode select */
#define PMP_MODE_MODE_MASK (3 << PMP_MODE_MODE_SHIFT) #define PMP_MODE_MODE_MASK (3 << PMP_MODE_MODE_SHIFT)
# define PMP_MODE_MODE_LEGACY (0 << PMP_MODE_MODE_SHIFT) /* Legacy parallel slave port */ # define PMP_MODE_MODE_LEGACY (0 << PMP_MODE_MODE_SHIFT) /* Legacy parallel slave port */
# define PMP_MODE_MODE_SLAVE (1 << PMP_MODE_MODE_SHIFT) /* Enhanced slave mode */ # define PMP_MODE_MODE_SLAVE (1 << PMP_MODE_MODE_SHIFT) /* Enhanced slave mode */
# define PMP_MODE_MODE_MODE2 (2 << PMP_MODE_MODE_SHIFT) /* Master mode 2 */ # define PMP_MODE_MODE_MODE2 (2 << PMP_MODE_MODE_SHIFT) /* Master mode 2 */
# define PMP_MODE_MODE_MODE1 (3 << PMP_MODE_MODE_SHIFT) /* Master mode 1 */ # define PMP_MODE_MODE_MODE1 (3 << PMP_MODE_MODE_SHIFT) /* Master mode 1 */
#define PMP_MODE_MODE16 (1 << 10) /* Bit 10: 8/16-bit mode */ #define PMP_MODE_MODE16 (1 << 10) /* Bit 10: 8/16-bit mode */
#define PMP_MODE_INCM_SHIFT (11) /* Bits 11-12: Increment Mode */ #define PMP_MODE_INCM_SHIFT (11) /* Bits 11-12: Increment Mode */
#define PMP_MODE_INCM_MASK (3 << PMP_MODE_INCM_MASK) #define PMP_MODE_INCM_MASK (3 << PMP_MODE_INCM_MASK)
# define PMP_MODE_INCM_NONE (0 << PMP_MODE_INCM_MASK) /* No incr or decr of addr */ # define PMP_MODE_INCM_NONE (0 << PMP_MODE_INCM_MASK) /* No incr or decr of addr */
# define PMP_MODE_INCM_INCR (1 << PMP_MODE_INCM_MASK) /* Incr addr on R/W cycle */ # define PMP_MODE_INCM_INCR (1 << PMP_MODE_INCM_MASK) /* Incr addr on R/W cycle */
# define PMP_MODE_INCM_DECR (2 << PMP_MODE_INCM_MASK) /* Decr addr on R/Wcycle */ # define PMP_MODE_INCM_DECR (2 << PMP_MODE_INCM_MASK) /* Decr addr on R/Wcycle */
# define PMP_MODE_INCM_SLAVE (3 << PMP_MODE_INCM_MASK) /* Slave mode auto-increment */ # define PMP_MODE_INCM_SLAVE (3 << PMP_MODE_INCM_MASK) /* Slave mode auto-increment */
#define PMP_MODE_IRQM_SHIFT (13) /* Bits 13-14: Interrupt request mode */ #define PMP_MODE_IRQM_SHIFT (13) /* Bits 13-14: Interrupt request mode */
#define PMP_MODE_IRQM_MASK (3 << PMP_MODE_IRQM_SHIFT) #define PMP_MODE_IRQM_MASK (3 << PMP_MODE_IRQM_SHIFT)
# define PMP_MODE_IRQM_NONE (0 << PMP_MODE_IRQM_SHIFT) /* No Interrupt generated */ # define PMP_MODE_IRQM_NONE (0 << PMP_MODE_IRQM_SHIFT) /* No Interrupt generated */
# define PMP_MODE_IRQM_RW (1 << PMP_MODE_IRQM_SHIFT) /* Interrupt at end of R/W cycle */ # define PMP_MODE_IRQM_RW (1 << PMP_MODE_IRQM_SHIFT) /* Interrupt at end of R/W cycle */
# define PMP_MODE_IRQM_BUFFER (2 << PMP_MODE_IRQM_SHIFT) /* R/W buffer 3 or write PMA=11 */ # define PMP_MODE_IRQM_BUFFER (2 << PMP_MODE_IRQM_SHIFT) /* R/W buffer 3 or write PMA=11 */
#define PMP_MODE_BUSY (1 << 15) /* Bit 15: Busy (master mode only) */ #define PMP_MODE_BUSY (1 << 15) /* Bit 15: Busy (master mode only) */
/* Parallel Port Address Register */ /* Parallel Port Address Register */
#define PMP_ADDR_ADDR_SHIFT (0) /* Bits 0-13: Destination address */ #define PMP_ADDR_ADDR_SHIFT (0) /* Bits 0-13: Destination address */
#define PMP_ADDR_ADDR_MASK (0x3fff << PMP_ADDR_ADDR_SHIFT) #define PMP_ADDR_ADDR_MASK (0x3fff << PMP_ADDR_ADDR_SHIFT)
#define PMP_ADDR_CS1EN (1 << 14) /* Bit 14: Chip select 1 */ #define PMP_ADDR_CS1EN (1 << 14) /* Bit 14: Chip select 1 */
#define PMP_ADDR_CS2EN (1 << 15) /* Bit 15: Chip select 2 */ #define PMP_ADDR_CS2EN (1 << 15) /* Bit 15: Chip select 2 */
/* Parallel Port Data Output Register -- 32-bit data register */ /* Parallel Port Data Output Register -- 32-bit data register */
/* Parallel Port Data Input Register -- 32-bit data register */ /* Parallel Port Data Input Register -- 32-bit data register */
/* Parallel Port Pin Enable Register */ /* Parallel Port Pin Enable Register */
#define PMP_AEN_PTEN_SHIFT (0) /* Bits 0-15: xx */ #define PMP_AEN_PTEN_SHIFT (0) /* Bits 0-15: xx */
#define PMP_AEN_PTEN_MASK (0xffff << PMP_AEN_PTEN_SHIFT) #define PMP_AEN_PTEN_MASK (0xffff << PMP_AEN_PTEN_SHIFT)
#define PMP_AEN_PMCSEN_SHIFT (14) /* PTEN 14-15: PMCSx Strobe enable */ #define PMP_AEN_PMCSEN_SHIFT (14) /* PTEN 14-15: PMCSx Strobe enable */
#define PMP_AEN_PMCSEN_MASK (3 << PMP_AEN_STROBEN_SHIFT) #define PMP_AEN_PMCSEN_MASK (3 << PMP_AEN_STROBEN_SHIFT)
#define PMP_AEN_ADDR_SHIFT (2) /* PTEN 2-13: PMP address port enable */ #define PMP_AEN_ADDR_SHIFT (2) /* PTEN 2-13: PMP address port enable */
#define PMP_AEN_ADDR_MASK (0xfff << PMP_AEN_STROBEN_SHIFT) #define PMP_AEN_ADDR_MASK (0xfff << PMP_AEN_STROBEN_SHIFT)
#define PMP_AEN_PMALEN_SHIFT (0) /* PTEN 0-1: PMALH/PMALL strobe enable */ #define PMP_AEN_PMALEN_SHIFT (0) /* PTEN 0-1: PMALH/PMALL strobe enable */
#define PMP_AEN_PMALEN_MASK (3 << PMP_AEN_STROBEN_SHIFT) #define PMP_AEN_PMALEN_MASK (3 << PMP_AEN_STROBEN_SHIFT)
/* Parallel Port Status Register */ /* Parallel Port Status Register */
#define PMP_STAT_OBE(n) (1 << (n)) #define PMP_STAT_OBE(n) (1 << (n))
#define PMP_STAT_OB0E (1 << 0) /* Bit 0: Output buffer 0 status empty bits */ #define PMP_STAT_OB0E (1 << 0) /* Bit 0: Output buffer 0 status empty bits */
#define PMP_STAT_OB1E (1 << 1) /* Bit 1: Output buffer 1 status empty bits */ #define PMP_STAT_OB1E (1 << 1) /* Bit 1: Output buffer 1 status empty bits */
#define PMP_STAT_OB2E (1 << 2) /* Bit 2: Output buffer 2 status empty bits */ #define PMP_STAT_OB2E (1 << 2) /* Bit 2: Output buffer 2 status empty bits */
#define PMP_STAT_OB3E (1 << 3) /* Bit 3: Output buffer 3 status empty bits */ #define PMP_STAT_OB3E (1 << 3) /* Bit 3: Output buffer 3 status empty bits */
#define PMP_STAT_OBUF (1 << 6) /* Bit 6: Output buffer underflow status */ #define PMP_STAT_OBUF (1 << 6) /* Bit 6: Output buffer underflow status */
#define PMP_STAT_OBE (1 << 7) /* Bit 7: Output buffer empty status */ #define PMP_STAT_OBE (1 << 7) /* Bit 7: Output buffer empty status */
#define PMP_STAT_IBF(n) (1 << (n+8)) #define PMP_STAT_IBF(n) (1 << (n+8))
#define PMP_STAT_IB0F (1 << 8) /* Bit 8: Input buffer 0 status full */ #define PMP_STAT_IB0F (1 << 8) /* Bit 8: Input buffer 0 status full */
#define PMP_STAT_IB1F (1 << 9) /* Bit 9: Input buffer 1 status full */ #define PMP_STAT_IB1F (1 << 9) /* Bit 9: Input buffer 1 status full */
#define PMP_STAT_IB2F (1 << 10) /* Bit 10: Input buffer 2 status full */ #define PMP_STAT_IB2F (1 << 10) /* Bit 10: Input buffer 2 status full */
#define PMP_STAT_IB3F (1 << 11) /* Bit 11: Input buffer 3 status full */ #define PMP_STAT_IB3F (1 << 11) /* Bit 11: Input buffer 3 status full */
#define PMP_STAT_IBOV (1 << 14) /* Bit 14: Input buffer overflow status */ #define PMP_STAT_IBOV (1 << 14) /* Bit 14: Input buffer overflow status */
#define PMP_STAT_IBF (1 << 15) /* Bit 15: Input buffer full status */ #define PMP_STAT_IBF (1 << 15) /* Bit 15: Input buffer full status */
/************************************************************************************ /************************************************************************************
* Public Types * Public Types
************************************************************************************/ ************************************************************************************/
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
/************************************************************************************ /************************************************************************************
* Inline Functions * Inline Functions
************************************************************************************/ ************************************************************************************/
/************************************************************************************ /************************************************************************************
* Public Function Prototypes * Public Function Prototypes
************************************************************************************/ ************************************************************************************/
#ifdef __cplusplus #ifdef __cplusplus
#define EXTERN extern "C" #define EXTERN extern "C"
extern "C" { extern "C" {
#else #else
#define EXTERN extern #define EXTERN extern
#endif #endif
#undef EXTERN #undef EXTERN
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* __ASSEMBLY__ */ #endif /* __ASSEMBLY__ */
#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_PMP_H */ #endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_PMP_H */
nuttx/arch/mips/src/pic32mx/pic32mx-serial.c
+4 -4
View File
@@ -419,7 +419,7 @@ static int up_attach(struct uart_dev_s *dev)
static void up_detach(struct uart_dev_s *dev) static void up_detach(struct uart_dev_s *dev)
{ {
struct up_dev_s *priv = (struct up_dev_s*)dev->priv; struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
/* Disable interrupts */ /* Disable interrupts */
up_disableuartint(dev, NULL); up_disableuartint(dev, NULL);
@@ -478,8 +478,8 @@ static int up_interrupt(int irq, void *context)
handled = false; handled = false;
/* Handle error interrupts. This interrupt occurs when any of the /* Handle error interrupts. This interrupt occurs when any of the
* following error conditions take place: * following error conditions take place:
* - Parity error PERR (UxSTA bit 3) is detected * - Parity error PERR (UxSTA bit 3) is detected
* - Framing Error FERR (UxSTA bit 2) is detected * - Framing Error FERR (UxSTA bit 2) is detected
* - Overflow condition for the receive buffer OERR (UxSTA bit 1) occurs * - Overflow condition for the receive buffer OERR (UxSTA bit 1) occurs
*/ */
@@ -544,7 +544,7 @@ static int up_interrupt(int irq, void *context)
uart_xmitchars(dev); uart_xmitchars(dev);
handled = true; handled = true;
/* Clear the pending TX interrupt if the TX FIFO is empty. /* Clear the pending TX interrupt if the TX FIFO is empty.
* Note that interrupts can be lost if the interrupt condition is * Note that interrupts can be lost if the interrupt condition is
* still true when the interrupt is cleared. Keeping the TX * still true when the interrupt is cleared. Keeping the TX
* interrupt pending too long is not a problem: Upper level logic * interrupt pending too long is not a problem: Upper level logic
nuttx/arch/mips/src/pic32mx/pic32mx-timerisr.c
+2 -2
View File
@@ -104,7 +104,7 @@
* TIMER1_PRESCALE = 64 * TIMER1_PRESCALE = 64
* TIMER1_MATCH = 9375 -> 100.0 ticks/sec * TIMER1_MATCH = 9375 -> 100.0 ticks/sec
*/ */
#define OPTIMAL_PRESCALE (TIMER1_SRC_FREQ / CLOCKS_PER_SEC / 65535) #define OPTIMAL_PRESCALE (TIMER1_SRC_FREQ / CLOCKS_PER_SEC / 65535)
#if OPTIMAL_PRESCALE <= 1 #if OPTIMAL_PRESCALE <= 1
# define TIMER1_CON_TCKPS TIMER1_CON_TCKPS_1 # define TIMER1_CON_TCKPS TIMER1_CON_TCKPS_1
@@ -148,7 +148,7 @@
int up_timerisr(int irq, uint32_t *regs) int up_timerisr(int irq, uint32_t *regs)
{ {
/* Clear the pending timer interrupt */ /* Clear the pending timer interrupt */
putreg32(INT_T1, PIC32MX_INT_IFS0CLR); putreg32(INT_T1, PIC32MX_INT_IFS0CLR);
/* Process timer interrupt */ /* Process timer interrupt */
nuttx/arch/mips/src/pic32mx/pic32mx-usbdev.c
+69 -70
View File
@@ -116,7 +116,7 @@
#define PIC32MX_ENDP_ALLSET 0xffff #define PIC32MX_ENDP_ALLSET 0xffff
/* Endpoint Definitions */ /* Endpoint Definitions */
#ifndef CONFIG_USB_PINGPONG #ifndef CONFIG_USB_PINGPONG
# define USB_NEXT_PINGPONG (0) # define USB_NEXT_PINGPONG (0)
# define EP0_OUT_EVEN (0) # define EP0_OUT_EVEN (0)
@@ -146,7 +146,7 @@
#define PIC32MX_MAXPACKET_SHIFT (6) #define PIC32MX_MAXPACKET_SHIFT (6)
#define PIC32MX_MAXPACKET_SIZE (1 << (PIC32MX_MAXPACKET_SHIFT)) #define PIC32MX_MAXPACKET_SIZE (1 << (PIC32MX_MAXPACKET_SHIFT))
#define PIC32MX_EP0MAXPACKET PIC32MX_MAXPACKET_SIZE #define PIC32MX_EP0MAXPACKET PIC32MX_MAXPACKET_SIZE
/* Endpoint register initialization parameters */ /* Endpoint register initialization parameters */
@@ -280,7 +280,7 @@
/* Overvall device state */ /* Overvall device state */
enum pic32mx_devstate_e enum pic32mx_devstate_e
{ {
DEVSTATE_DETACHED = 0, /* Not connected to a host */ DEVSTATE_DETACHED = 0, /* Not connected to a host */
DEVSTATE_ATTACHED, /* Connected to a host */ DEVSTATE_ATTACHED, /* Connected to a host */
@@ -293,7 +293,7 @@ enum pic32mx_devstate_e
/* The various states of the control pipe */ /* The various states of the control pipe */
enum pic32mx_ctrlstate_e enum pic32mx_ctrlstate_e
{ {
CTRLSTATE_WAITSETUP = 0, /* No request in progress, waiting for setup */ CTRLSTATE_WAITSETUP = 0, /* No request in progress, waiting for setup */
CTRLSTATE_RDREQUEST, /* Read request (OUT) in progress */ CTRLSTATE_RDREQUEST, /* Read request (OUT) in progress */
@@ -519,7 +519,7 @@ volatile struct usbotg_bdtentry_s
/**************************************************************************** /****************************************************************************
* Private Private Functions * Private Private Functions
****************************************************************************/ ****************************************************************************/
/**************************************************************************** /****************************************************************************
* Register Operations * Register Operations
****************************************************************************/ ****************************************************************************/
@@ -721,7 +721,7 @@ static void pic32mx_epwrite(struct pic32mx_ep_s *privep,
status ^= USB_BDT_DATA01; status ^= USB_BDT_DATA01;
#endif #endif
bdt->status = status; bdt->status = status;
/* Set the data pointer, data length, and enable the endpoint */ /* Set the data pointer, data length, and enable the endpoint */
bdt->addr = (uint8_t *)PHYS_ADDR(src); bdt->addr = (uint8_t *)PHYS_ADDR(src);
@@ -731,7 +731,7 @@ static void pic32mx_epwrite(struct pic32mx_ep_s *privep,
*/ */
status |= (nbytes << USB_BDT_BYTECOUNT_SHIFT) | USB_BDT_DTS; status |= (nbytes << USB_BDT_BYTECOUNT_SHIFT) | USB_BDT_DTS;
/* Point to the next ping pong buffer. */ /* Point to the next ping pong buffer. */
#ifdef CONFIG_USB_PINGPONG #ifdef CONFIG_USB_PINGPONG
@@ -769,7 +769,7 @@ static int pic32mx_wrrequest(struct pic32mx_usbdev_s *priv, struct pic32mx_ep_s
/* We get here when an IN endpoint interrupt occurs. So now we know that /* We get here when an IN endpoint interrupt occurs. So now we know that
* there is no TX transfer in progress. * there is no TX transfer in progress.
*/ */
privep->txbusy = false; privep->txbusy = false;
/* Get the endpoint number that we are servicing */ /* Get the endpoint number that we are servicing */
@@ -1000,7 +1000,7 @@ static int pic32mx_rdsetup(struct pic32mx_usbdev_s *priv,
/* Set the data length (preserving the data toggle). */ /* Set the data length (preserving the data toggle). */
status |= (readlen << USB_BDT_BYTECOUNT_SHIFT) | USB_BDT_DTS; status |= (readlen << USB_BDT_BYTECOUNT_SHIFT) | USB_BDT_DTS;
/* Point to the next ping pong buffer. */ /* Point to the next ping pong buffer. */
#ifdef CONFIG_USB_PINGPONG #ifdef CONFIG_USB_PINGPONG
@@ -1119,7 +1119,7 @@ static void pic32mx_dispatchrequest(struct pic32mx_usbdev_s *priv)
* Name: pic32mx_ep0stall * Name: pic32mx_ep0stall
****************************************************************************/ ****************************************************************************/
static void pic32mx_ep0stall(struct pic32mx_usbdev_s *priv) static void pic32mx_ep0stall(struct pic32mx_usbdev_s *priv)
{ {
uint16_t regval; uint16_t regval;
@@ -1157,12 +1157,12 @@ static void pic32mx_ep0stall(struct pic32mx_usbdev_s *priv)
* Name: pic32mx_eptransfer * Name: pic32mx_eptransfer
****************************************************************************/ ****************************************************************************/
static void pic32mx_eptransfer(struct pic32mx_usbdev_s *priv, uint8_t epno, static void pic32mx_eptransfer(struct pic32mx_usbdev_s *priv, uint8_t epno,
uint16_t status) uint16_t status)
{ {
struct pic32mx_ep_s *privep; struct pic32mx_ep_s *privep;
/* Decode and service non control endpoints interrupt */ /* Decode and service non control endpoints interrupt */
privep = &priv->eplist[epno]; privep = &priv->eplist[epno];
@@ -1198,11 +1198,11 @@ static void pic32mx_eptransfer(struct pic32mx_usbdev_s *priv, uint8_t epno,
/* IN: device-to-host */ /* IN: device-to-host */
usbtrace(TRACE_INTDECODE(PIC32MX_TRACEINTID_EPINDONE), status); usbtrace(TRACE_INTDECODE(PIC32MX_TRACEINTID_EPINDONE), status);
/* Handle write requests */ /* Handle write requests */
pic32mx_wrrequest(priv, privep); pic32mx_wrrequest(priv, privep);
} }
} }
/**************************************************************************** /****************************************************************************
@@ -1214,7 +1214,7 @@ static void pic32mx_ep0nextsetup(struct pic32mx_usbdev_s *priv)
struct pic32mx_ep_s *ep0 = &priv->eplist[EP0]; struct pic32mx_ep_s *ep0 = &priv->eplist[EP0];
volatile struct usbotg_bdtentry_s *bdt = ep0->bdtin; volatile struct usbotg_bdtentry_s *bdt = ep0->bdtin;
uint16_t status; uint16_t status;
priv->ctrlstate = CTRLSTATE_WAITSETUP; priv->ctrlstate = CTRLSTATE_WAITSETUP;
/* Don't need to do anything to EP0 OUT buffer descriptor table (BDT) here, /* Don't need to do anything to EP0 OUT buffer descriptor table (BDT) here,
@@ -1283,7 +1283,7 @@ static void pic32mx_ep0done(struct pic32mx_usbdev_s *priv,
status = bdtout->status & ~(USB_BDT_BYTECOUNT_MASK | USB_BDT_DTS); status = bdtout->status & ~(USB_BDT_BYTECOUNT_MASK | USB_BDT_DTS);
status |= (USB_SIZEOF_CTRLREQ << USB_BDT_BYTECOUNT_SHIFT); status |= (USB_SIZEOF_CTRLREQ << USB_BDT_BYTECOUNT_SHIFT);
status |= USB_BDT_UOWN; /* Note: DTSEN is 0 */ status |= USB_BDT_UOWN; /* Note: DTSEN is 0 */
bdtout->addr = (uint8_t *)PHYS_ADDR(&priv->ctrl); bdtout->addr = (uint8_t *)PHYS_ADDR(&priv->ctrl);
regdbg("EP0 BDT OUT (Next) {%08x, %08x}\n", status, bdtout->addr); regdbg("EP0 BDT OUT (Next) {%08x, %08x}\n", status, bdtout->addr);
@@ -1437,13 +1437,13 @@ static void pic32mx_ep0setup(struct pic32mx_usbdev_s *priv)
if (USB_ISEPIN(index.b[LSB])) if (USB_ISEPIN(index.b[LSB]))
{ {
/* IN endpoint */ /* IN endpoint */
bdt = privep->bdtin; bdt = privep->bdtin;
} }
else else
{ {
/* OUT endpoint */ /* OUT endpoint */
bdt = privep->bdtout; bdt = privep->bdtout;
} }
@@ -1519,7 +1519,7 @@ static void pic32mx_ep0setup(struct pic32mx_usbdev_s *priv)
} }
/* Disable A device HNP support */ /* Disable A device HNP support */
else if (value.w == USBOTG_FEATURE_A_HNP_SUPPORT) else if (value.w == USBOTG_FEATURE_A_HNP_SUPPORT)
{ {
/* Disable HNP support*/ /* Disable HNP support*/
@@ -1614,8 +1614,8 @@ static void pic32mx_ep0setup(struct pic32mx_usbdev_s *priv)
#warning "Missing logic" #warning "Missing logic"
} }
else else
#endif #endif
if (value.w == USB_FEATURE_REMOTEWAKEUP) if (value.w == USB_FEATURE_REMOTEWAKEUP)
{ {
priv->rwakeup = 0; priv->rwakeup = 0;
@@ -1924,8 +1924,8 @@ static void pic32mx_ep0in(struct pic32mx_usbdev_s *priv)
/* This should be the equivalent state */ /* This should be the equivalent state */
DEBUGASSERT(priv->ctrl.req == USB_REQ_SETADDRESS && DEBUGASSERT(priv->ctrl.req == USB_REQ_SETADDRESS &&
(priv->ctrl.type & REQRECIPIENT_MASK) == (priv->ctrl.type & REQRECIPIENT_MASK) ==
(USB_REQ_TYPE_STANDARD | USB_REQ_RECIPIENT_DEVICE)); (USB_REQ_TYPE_STANDARD | USB_REQ_RECIPIENT_DEVICE));
pic32mx_putreg(addr, PIC32MX_USB_ADDR); pic32mx_putreg(addr, PIC32MX_USB_ADDR);
@@ -2103,7 +2103,7 @@ static void pic32mx_ep0transfer(struct pic32mx_usbdev_s *priv, uint16_t status)
memcpy(dest, src, USB_SIZEOF_CTRLREQ); memcpy(dest, src, USB_SIZEOF_CTRLREQ);
bdt->addr = (uint8_t *)PHYS_ADDR(&priv->ctrl); bdt->addr = (uint8_t *)PHYS_ADDR(&priv->ctrl);
} }
/* Handle the control OUT transfer */ /* Handle the control OUT transfer */
usbtrace(TRACE_INTDECODE(PIC32MX_TRACEINTID_EP0SETUPDONE), bdt->status); usbtrace(TRACE_INTDECODE(PIC32MX_TRACEINTID_EP0SETUPDONE), bdt->status);
@@ -2155,7 +2155,7 @@ static int pic32mx_interrupt(int irq, void *context)
uint16_t pending; uint16_t pending;
uint16_t regval; uint16_t regval;
int i; int i;
/* Get the set of pending USB interrupts */ /* Get the set of pending USB interrupts */
pending = pic32mx_getreg(PIC32MX_USB_IR) & pic32mx_getreg(PIC32MX_USB_IE); pending = pic32mx_getreg(PIC32MX_USB_IR) & pic32mx_getreg(PIC32MX_USB_IE);
@@ -2163,12 +2163,12 @@ static int pic32mx_interrupt(int irq, void *context)
#ifdef CONFIG_USBOTG #ifdef CONFIG_USBOTG
/* Session Request Protocol (SRP) Time Out Check */ /* Session Request Protocol (SRP) Time Out Check */
/* if USB OTG SRP is ready */ /* if USB OTG SRP is ready */
# warning "Missing logic" # warning "Missing logic"
{ {
/* Check if the 1 millisecond timer has expired */ /* Check if the 1 millisecond timer has expired */
if ((pic32mx_getreg(PIC32MX_USBOTG_IR) & pic32mx_getreg(PIC32MX_USBOTG_IE) & USB OTG_INT_T1MSEC) != 0) if ((pic32mx_getreg(PIC32MX_USBOTG_IR) & pic32mx_getreg(PIC32MX_USBOTG_IE) & USB OTG_INT_T1MSEC) != 0)
{ {
usbtrace(TRACE_INTDECODE(PIC32MX_TRACEINTID_T1MSEC), pending); usbtrace(TRACE_INTDECODE(PIC32MX_TRACEINTID_T1MSEC), pending);
@@ -2179,7 +2179,7 @@ static int pic32mx_interrupt(int irq, void *context)
/* Handle OTG events of the SRP timeout has expired */ /* Handle OTG events of the SRP timeout has expired */
# warning "Missing logic" # warning "Missing logic"
} }
/* Clear Interrupt 1 msec timer Flag */ /* Clear Interrupt 1 msec timer Flag */
pic32mx_putreg(USBOTG_INT_T1MSEC, PIC32MX_USBOTG_IR); pic32mx_putreg(USBOTG_INT_T1MSEC, PIC32MX_USBOTG_IR);
@@ -2205,7 +2205,7 @@ static int pic32mx_interrupt(int irq, void *context)
priv->devstate = DEVSTATE_POWERED; priv->devstate = DEVSTATE_POWERED;
} }
#ifdef CONFIG_USBOTG #ifdef CONFIG_USBOTG
/* Check if the ID Pin Changed State */ /* Check if the ID Pin Changed State */
@@ -2219,7 +2219,7 @@ static int pic32mx_interrupt(int irq, void *context)
pic32mx_putreg(USBOTG_INT_ID, PIC32MX_USBOTG_IR); pic32mx_putreg(USBOTG_INT_ID, PIC32MX_USBOTG_IR);
} }
#endif #endif
/* Service the USB Activity Interrupt */ /* Service the USB Activity Interrupt */
if ((pending & USBOTG_INT_ACTV) != 0) if ((pending & USBOTG_INT_ACTV) != 0)
@@ -2243,7 +2243,7 @@ static int pic32mx_interrupt(int irq, void *context)
up_clrpend_irq(PIC32MX_IRQSRC_USB); up_clrpend_irq(PIC32MX_IRQSRC_USB);
return OK; return OK;
} }
/* Service USB Bus Reset Interrupt. When bus reset is received during /* Service USB Bus Reset Interrupt. When bus reset is received during
* suspend, ACTVIF will be set first, once the UCONbits.SUSPND is clear, * suspend, ACTVIF will be set first, once the UCONbits.SUSPND is clear,
* then the URSTIF bit will be asserted. This is why URSTIF is checked * then the URSTIF bit will be asserted. This is why URSTIF is checked
@@ -2269,7 +2269,7 @@ static int pic32mx_interrupt(int irq, void *context)
g_bdt[EP0_OUT_EVEN].status |= (USB_SIZEOF_CTRLREQ << USB_BDT_BYTECOUNT_SHIFT); g_bdt[EP0_OUT_EVEN].status |= (USB_SIZEOF_CTRLREQ << USB_BDT_BYTECOUNT_SHIFT);
g_bdt[EP0_OUT_EVEN].status &= ~USB_BDT_STATUS_MASK; g_bdt[EP0_OUT_EVEN].status &= ~USB_BDT_STATUS_MASK;
g_bdt[EP0_OUT_EVEN].status |= USB_BDT_UOWN | USB_BDT_DATA0 | USB_BDT_DTS | USB_BDT_BSTALL; g_bdt[EP0_OUT_EVEN].status |= USB_BDT_UOWN | USB_BDT_DATA0 | USB_BDT_DTS | USB_BDT_BSTALL;
#ifdef CONFIG_USBOTG #ifdef CONFIG_USBOTG
/* Disable and deactivate HNP */ /* Disable and deactivate HNP */
#warning Missing Logic #warning Missing Logic
@@ -2277,19 +2277,19 @@ static int pic32mx_interrupt(int irq, void *context)
pic32mx_putreg(USB_INT_URST, PIC32MX_USB_IR); pic32mx_putreg(USB_INT_URST, PIC32MX_USB_IR);
return OK; return OK;
} }
/* Service IDLE interrupts */ /* Service IDLE interrupts */
if ((pending & USB_INT_IDLE) != 0) if ((pending & USB_INT_IDLE) != 0)
{ {
usbtrace(TRACE_INTDECODE(PIC32MX_TRACEINTID_IDLE), pending); usbtrace(TRACE_INTDECODE(PIC32MX_TRACEINTID_IDLE), pending);
#ifdef CONFIG_USBOTG #ifdef CONFIG_USBOTG
/* If Suspended, Try to switch to Host */ /* If Suspended, Try to switch to Host */
#warning "Missing logic" #warning "Missing logic"
#else #else
pic32mx_suspend(priv); pic32mx_suspend(priv);
#endif #endif
pic32mx_putreg(USB_INT_IDLE, PIC32MX_USB_IR); pic32mx_putreg(USB_INT_IDLE, PIC32MX_USB_IR);
} }
@@ -2308,7 +2308,7 @@ static int pic32mx_interrupt(int irq, void *context)
#endif #endif
/* Service stall interrupts */ /* Service stall interrupts */
if ((pending & USB_INT_STALL) != 0) if ((pending & USB_INT_STALL) != 0)
{ {
usbtrace(TRACE_INTDECODE(PIC32MX_TRACEINTID_STALL), pending); usbtrace(TRACE_INTDECODE(PIC32MX_TRACEINTID_STALL), pending);
@@ -2331,7 +2331,7 @@ static int pic32mx_interrupt(int irq, void *context)
pic32mx_putreg(USB_EINT_ALL, PIC32MX_USB_EIR); pic32mx_putreg(USB_EINT_ALL, PIC32MX_USB_EIR);
} }
/* There is no point in continuing if the host has not sent a bus reset. /* There is no point in continuing if the host has not sent a bus reset.
* Once bus reset is received, the device transitions into the DEFAULT * Once bus reset is received, the device transitions into the DEFAULT
* state and is ready for communication. * state and is ready for communication.
@@ -2342,7 +2342,7 @@ static int pic32mx_interrupt(int irq, void *context)
up_clrpend_irq(PIC32MX_IRQSRC_USB); up_clrpend_irq(PIC32MX_IRQSRC_USB);
return OK; return OK;
} }
/* Service USB Transaction Complete Interrupt */ /* Service USB Transaction Complete Interrupt */
if ((pending & USB_INT_TRN) != 0) if ((pending & USB_INT_TRN) != 0)
@@ -2361,11 +2361,10 @@ static int pic32mx_interrupt(int irq, void *context)
/* Is token processing complete */ /* Is token processing complete */
if ((pic32mx_getreg(PIC32MX_USB_IR) & USB_INT_TRN) != 0) if ((pic32mx_getreg(PIC32MX_USB_IR) & USB_INT_TRN) != 0)
{ {
regval = pic32mx_getreg(PIC32MX_USB_STAT); regval = pic32mx_getreg(PIC32MX_USB_STAT);
pic32mx_putreg(USB_INT_TRN, PIC32MX_USB_IR); pic32mx_putreg(USB_INT_TRN, PIC32MX_USB_IR);
/* Handle the endpoint tranfer complete event. */ /* Handle the endpoint tranfer complete event. */
epno = (regval & USB_STAT_ENDPT_MASK) >> USB_STAT_ENDPT_SHIFT; epno = (regval & USB_STAT_ENDPT_MASK) >> USB_STAT_ENDPT_SHIFT;
@@ -2377,7 +2376,7 @@ static int pic32mx_interrupt(int irq, void *context)
{ {
pic32mx_eptransfer(priv, epno, regval); pic32mx_eptransfer(priv, epno, regval);
} }
} }
else else
{ {
/* USTAT FIFO must be empty. */ /* USTAT FIFO must be empty. */
@@ -2401,14 +2400,14 @@ static int pic32mx_interrupt(int irq, void *context)
* Name: pic32mx_suspend * Name: pic32mx_suspend
****************************************************************************/ ****************************************************************************/
static void pic32mx_suspend(struct pic32mx_usbdev_s *priv) static void pic32mx_suspend(struct pic32mx_usbdev_s *priv)
{ {
uint16_t regval; uint16_t regval;
/* NOTE: Do not clear UIRbits.ACTVIF here! Reason: ACTVIF is only /* NOTE: Do not clear UIRbits.ACTVIF here! Reason: ACTVIF is only
* generated once an IDLEIF has been generated. This is a 1:1 ratio * generated once an IDLEIF has been generated. This is a 1:1 ratio
* interrupt generation. For every IDLEIF, there will be only one ACTVIF * interrupt generation. For every IDLEIF, there will be only one ACTVIF
* regardless of the number of subsequent bus transitions. If the ACTIF * regardless of the number of subsequent bus transitions. If the ACTIF
* is cleared here, a problem could occur. The driver services IDLEIF * is cleared here, a problem could occur. The driver services IDLEIF
* first because ACTIVIE=0. If this routine clears the only ACTIVIF, * first because ACTIVIE=0. If this routine clears the only ACTIVIF,
* then it can never get out of the suspend mode. * then it can never get out of the suspend mode.
@@ -2423,13 +2422,13 @@ static void pic32mx_suspend(struct pic32mx_usbdev_s *priv)
*/ */
pic32mx_usbsuspend((struct usbdev_s *)priv, false); pic32mx_usbsuspend((struct usbdev_s *)priv, false);
} }
/**************************************************************************** /****************************************************************************
* Name: pic32mx_resume * Name: pic32mx_resume
****************************************************************************/ ****************************************************************************/
static void pic32mx_resume(struct pic32mx_usbdev_s *priv) static void pic32mx_resume(struct pic32mx_usbdev_s *priv)
{ {
irqstate_t flags; irqstate_t flags;
uint16_t regval; uint16_t regval;
@@ -2475,7 +2474,7 @@ static void pic32mx_resume(struct pic32mx_usbdev_s *priv)
pic32mx_putreg(USB_INT_IDLE, PIC32MX_USBOTG_IR); pic32mx_putreg(USB_INT_IDLE, PIC32MX_USBOTG_IR);
irqrestore(flags); irqrestore(flags);
} }
/**************************************************************************** /****************************************************************************
* Endpoint Helpers * Endpoint Helpers
@@ -2648,7 +2647,7 @@ static int pic32mx_epconfigure(struct usbdev_ep_s *ep,
regdbg("EP%d BDT IN {%08x, %08x}\n", epno, status, bdt->addr); regdbg("EP%d BDT IN {%08x, %08x}\n", epno, status, bdt->addr);
#endif #endif
} }
if (!epin || bidi) if (!epin || bidi)
{ {
index = EP(epno, 0, 0); index = EP(epno, 0, 0);
@@ -2738,7 +2737,7 @@ static int pic32mx_epdisable(struct usbdev_ep_s *ep)
/* Disable the endpoint */ /* Disable the endpoint */
pic32mx_putreg(0, PIC32MX_USB_EP(epno)); pic32mx_putreg(0, PIC32MX_USB_EP(epno));
/* Reset the BDTs */ /* Reset the BDTs */
ptr = (uint32_t*)&g_bdt[EP(epno, 0, 0)]; ptr = (uint32_t*)&g_bdt[EP(epno, 0, 0)];
@@ -3290,7 +3289,7 @@ static void pic32mx_reset(struct pic32mx_usbdev_s *priv)
{ {
CLASS_DISCONNECT(priv->driver, &priv->usbdev); CLASS_DISCONNECT(priv->driver, &priv->usbdev);
} }
/* Reset the device state structure */ /* Reset the device state structure */
priv->ctrlstate = CTRLSTATE_WAITSETUP; priv->ctrlstate = CTRLSTATE_WAITSETUP;
@@ -3322,7 +3321,7 @@ static void pic32mx_reset(struct pic32mx_usbdev_s *priv)
/* Re-configure the USB controller in its initial, unconnected state */ /* Re-configure the USB controller in its initial, unconnected state */
pic32mx_hwreset(priv); pic32mx_hwreset(priv);
} }
/**************************************************************************** /****************************************************************************
* Name: pic32mx_attach * Name: pic32mx_attach
@@ -3339,12 +3338,12 @@ static void pic32mx_attach(struct pic32mx_usbdev_s *priv)
/* Initialize registers to known states. */ /* Initialize registers to known states. */
pic32mx_putreg(0, PIC32MX_USB_CON); pic32mx_putreg(0, PIC32MX_USB_CON);
/* Mask all USB interrupts */ /* Mask all USB interrupts */
pic32mx_putreg(0, PIC32MX_USB_IE); pic32mx_putreg(0, PIC32MX_USB_IE);
/* Configure things like: pull ups, full/low-speed mode, /* Configure things like: pull ups, full/low-speed mode,
* set the ping pong mode, and set internal transceiver * set the ping pong mode, and set internal transceiver
*/ */
@@ -3402,7 +3401,7 @@ static void pic32mx_detach(struct pic32mx_usbdev_s *priv)
/* Disable the USB controller and detach from the bus. */ /* Disable the USB controller and detach from the bus. */
pic32mx_putreg(0, PIC32MX_USB_CON); pic32mx_putreg(0, PIC32MX_USB_CON);
/* Mask all USB interrupts */ /* Mask all USB interrupts */
pic32mx_putreg(0, PIC32MX_USB_IE); pic32mx_putreg(0, PIC32MX_USB_IE);
@@ -3410,12 +3409,12 @@ static void pic32mx_detach(struct pic32mx_usbdev_s *priv)
/* We are now in the detached state */ /* We are now in the detached state */
priv->devstate = DEVSTATE_DETACHED; priv->devstate = DEVSTATE_DETACHED;
#ifdef CONFIG_USBOTG #ifdef CONFIG_USBOTG
/* Disable the D+ Pullup */ /* Disable the D+ Pullup */
U1OTGCONbits.DPPULUP = 0; U1OTGCONbits.DPPULUP = 0;
/* Disable and deactivate HNP */ /* Disable and deactivate HNP */
#warning Missing Logic #warning Missing Logic
@@ -3425,7 +3424,7 @@ static void pic32mx_detach(struct pic32mx_usbdev_s *priv)
{ {
/* Re-detect & Initialize */ /* Re-detect & Initialize */
#warning "Missing logic" #warning "Missing logic"
/* Clear ID Interrupt Flag */ /* Clear ID Interrupt Flag */
pic32mx_putreg(USBOTG_INT_ID, PIC32MX_USBOTG_IR); pic32mx_putreg(USBOTG_INT_ID, PIC32MX_USBOTG_IR);
@@ -3489,7 +3488,7 @@ static void pic32mx_hwreset(struct pic32mx_usbdev_s *priv)
/* Clear all of the buffer descriptor table (BDT) entries */ /* Clear all of the buffer descriptor table (BDT) entries */
memset((void*)g_bdt, 0, sizeof(g_bdt)); memset((void*)g_bdt, 0, sizeof(g_bdt));
/* Initialize EP0 as a Ctrl EP */ /* Initialize EP0 as a Ctrl EP */
pic32mx_putreg(PIC32MX_EP_CONTROL, PIC32MX_USB_EP0); pic32mx_putreg(PIC32MX_EP_CONTROL, PIC32MX_USB_EP0);
@@ -3501,7 +3500,7 @@ static void pic32mx_hwreset(struct pic32mx_usbdev_s *priv)
{ {
pic32mx_putreg(USB_INT_TRN, PIC32MX_USB_IR); pic32mx_putreg(USB_INT_TRN, PIC32MX_USB_IR);
} }
/* Make sure packet processing is enabled */ /* Make sure packet processing is enabled */
regval = pic32mx_getreg(PIC32MX_USB_CON); regval = pic32mx_getreg(PIC32MX_USB_CON);
@@ -3527,10 +3526,10 @@ static void pic32mx_hwsetup(struct pic32mx_usbdev_s *priv)
/* Disconnect the device / disable the pull-up. We don't want the /* Disconnect the device / disable the pull-up. We don't want the
* host to enumerate us until the class driver is registered. * host to enumerate us until the class driver is registered.
*/ */
pic32mx_usbpullup(&priv->usbdev, false); pic32mx_usbpullup(&priv->usbdev, false);
/* Initialize the device state structure. NOTE: many fields /* Initialize the device state structure. NOTE: many fields
* have the initial value of zero and, hence, are not explicitly * have the initial value of zero and, hence, are not explicitly
* initialized here. * initialized here.
@@ -3586,20 +3585,20 @@ static void pic32mx_hwshutdown(struct pic32mx_usbdev_s *priv)
pic32mx_reset(priv); pic32mx_reset(priv);
priv->usbdev.speed = USB_SPEED_UNKNOWN; priv->usbdev.speed = USB_SPEED_UNKNOWN;
/* Disable all interrupts and force the USB controller into reset */ /* Disable all interrupts and force the USB controller into reset */
pic32mx_putreg(0, PIC32MX_USB_EIE); pic32mx_putreg(0, PIC32MX_USB_EIE);
pic32mx_putreg(0, PIC32MX_USB_EIE); pic32mx_putreg(0, PIC32MX_USB_EIE);
/* Clear any pending interrupts */ /* Clear any pending interrupts */
pic32mx_putreg(USB_EINT_ALL, PIC32MX_USB_EIR); pic32mx_putreg(USB_EINT_ALL, PIC32MX_USB_EIR);
pic32mx_putreg(USB_INT_ALL, PIC32MX_USB_IR); pic32mx_putreg(USB_INT_ALL, PIC32MX_USB_IR);
/* Disconnect the device / disable the pull-up */ /* Disconnect the device / disable the pull-up */
pic32mx_usbpullup(&priv->usbdev, false); pic32mx_usbpullup(&priv->usbdev, false);
/* Power down the USB controller */ /* Power down the USB controller */
regval = pic32mx_getreg(PIC32MX_USB_PWRC); regval = pic32mx_getreg(PIC32MX_USB_PWRC);
@@ -3624,7 +3623,7 @@ static void pic32mx_hwshutdown(struct pic32mx_usbdev_s *priv)
* *
****************************************************************************/ ****************************************************************************/
void up_usbinitialize(void) void up_usbinitialize(void)
{ {
/* For now there is only one USB controller, but we will always refer to /* For now there is only one USB controller, but we will always refer to
* it using a pointer to make any future ports to multiple USB controllers * it using a pointer to make any future ports to multiple USB controllers
@@ -3651,7 +3650,7 @@ void up_usbinitialize(void)
(uint16_t)PIC32MX_IRQ_USB); (uint16_t)PIC32MX_IRQ_USB);
up_usbuninitialize(); up_usbuninitialize();
} }
} }
/**************************************************************************** /****************************************************************************
* Name: up_usbuninitialize * Name: up_usbuninitialize
@@ -3665,7 +3664,7 @@ void up_usbinitialize(void)
* *
****************************************************************************/ ****************************************************************************/
void up_usbuninitialize(void) void up_usbuninitialize(void)
{ {
/* For now there is only one USB controller, but we will always refer to /* For now there is only one USB controller, but we will always refer to
* it using a pointer to make any future ports to multiple USB controllers * it using a pointer to make any future ports to multiple USB controllers
nuttx/arch/mips/src/pic32mx/pic32mx-wdt.h
+117 -117
View File
@@ -1,117 +1,117 @@
/**************************************************************************** /****************************************************************************
* arch/mips/src/pic32mx/pic32mx-wdt.h * arch/mips/src/pic32mx/pic32mx-wdt.h
* *
* Copyright (C) 2011 Gregory Nutt. All rights reserved. * Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr> * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
* are met: * are met:
* *
* 1. Redistributions of source code must retain the above copyright * 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer. * notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright * 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in * notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the * the documentation and/or other materials provided with the
* distribution. * distribution.
* 3. Neither the name NuttX nor the names of its contributors may be * 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software * used to endorse or promote products derived from this software
* without specific prior written permission. * without specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************/ ****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_WDT_H #ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_WDT_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_WDT_H #define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_WDT_H
/**************************************************************************** /****************************************************************************
* Included Files * Included Files
****************************************************************************/ ****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include "pic32mx-memorymap.h" #include "pic32mx-memorymap.h"
/**************************************************************************** /****************************************************************************
* Pre-Processor Definitions * Pre-Processor Definitions
****************************************************************************/ ****************************************************************************/
/* Register Offsets *********************************************************/ /* Register Offsets *********************************************************/
#define PIC32MX_WDT_CON_OFFSET 0x0000 /* Watchdog timer control register */ #define PIC32MX_WDT_CON_OFFSET 0x0000 /* Watchdog timer control register */
/* See also the WDTO, SLEEP, and IDLE bits in the resets RCON register */ /* See also the WDTO, SLEEP, and IDLE bits in the resets RCON register */
/* Register Addresses *******************************************************/ /* Register Addresses *******************************************************/
#define PIC32MX_WDT_CON (PIC32MX_WDT_K1BASE+PIC32MX_WDT_CON_OFFSET) #define PIC32MX_WDT_CON (PIC32MX_WDT_K1BASE+PIC32MX_WDT_CON_OFFSET)
/* Register Bit-Field Definitions *******************************************/ /* Register Bit-Field Definitions *******************************************/
/* Watchdog timer control register */ /* Watchdog timer control register */
#define WDT_CON_WDTCLR (1 << 0) /* Bit 0: Watchdog timer reset */ #define WDT_CON_WDTCLR (1 << 0) /* Bit 0: Watchdog timer reset */
#define WDT_CON_SWDTPS_SHIFT (2) /* Bits 2-6: WDT postscaler value from DEVCFG1 */ #define WDT_CON_SWDTPS_SHIFT (2) /* Bits 2-6: WDT postscaler value from DEVCFG1 */
#define WDT_CON_SWDTPS_MASK (31 << WDT_CON_SWDTPS_SHIFT) #define WDT_CON_SWDTPS_MASK (31 << WDT_CON_SWDTPS_SHIFT)
# define WDT_CON_SWDTPS_1 (0 << WDT_CON_SWDTPS_SHIFT) /* 1:1 */ # define WDT_CON_SWDTPS_1 (0 << WDT_CON_SWDTPS_SHIFT) /* 1:1 */
# define WDT_CON_SWDTPS_2 (1 << WDT_CON_SWDTPS_SHIFT) /* 1:2 */ # define WDT_CON_SWDTPS_2 (1 << WDT_CON_SWDTPS_SHIFT) /* 1:2 */
# define WDT_CON_SWDTPS_4 (2 << WDT_CON_SWDTPS_SHIFT) /* 1:4 */ # define WDT_CON_SWDTPS_4 (2 << WDT_CON_SWDTPS_SHIFT) /* 1:4 */
# define WDT_CON_SWDTPS_8 (3 << WDT_CON_SWDTPS_SHIFT) /* 1:8 */ # define WDT_CON_SWDTPS_8 (3 << WDT_CON_SWDTPS_SHIFT) /* 1:8 */
# define WDT_CON_SWDTPS_16 (4 << WDT_CON_SWDTPS_SHIFT) /* 1:16 */ # define WDT_CON_SWDTPS_16 (4 << WDT_CON_SWDTPS_SHIFT) /* 1:16 */
# define WDT_CON_SWDTPS_32 (5 << WDT_CON_SWDTPS_SHIFT) /* 1:32 */ # define WDT_CON_SWDTPS_32 (5 << WDT_CON_SWDTPS_SHIFT) /* 1:32 */
# define WDT_CON_SWDTPS_64 (6 << WDT_CON_SWDTPS_SHIFT) /* 1:64 */ # define WDT_CON_SWDTPS_64 (6 << WDT_CON_SWDTPS_SHIFT) /* 1:64 */
# define WDT_CON_SWDTPS_128 (7 << WDT_CON_SWDTPS_SHIFT) /* 1:128 */ # define WDT_CON_SWDTPS_128 (7 << WDT_CON_SWDTPS_SHIFT) /* 1:128 */
# define WDT_CON_SWDTPS_256 (8 << WDT_CON_SWDTPS_SHIFT) /* 1:256 */ # define WDT_CON_SWDTPS_256 (8 << WDT_CON_SWDTPS_SHIFT) /* 1:256 */
# define WDT_CON_SWDTPS_512 (9 << WDT_CON_SWDTPS_SHIFT) /* 1:512 */ # define WDT_CON_SWDTPS_512 (9 << WDT_CON_SWDTPS_SHIFT) /* 1:512 */
# define WDT_CON_SWDTPS_1024 (10 << WDT_CON_SWDTPS_SHIFT) /* 1:1024 */ # define WDT_CON_SWDTPS_1024 (10 << WDT_CON_SWDTPS_SHIFT) /* 1:1024 */
# define WDT_CON_SWDTPS_2048 (11 << WDT_CON_SWDTPS_SHIFT) /* 1:2048 */ # define WDT_CON_SWDTPS_2048 (11 << WDT_CON_SWDTPS_SHIFT) /* 1:2048 */
# define WDT_CON_SWDTPS_4096 (12 << WDT_CON_SWDTPS_SHIFT) /* 1:4096 */ # define WDT_CON_SWDTPS_4096 (12 << WDT_CON_SWDTPS_SHIFT) /* 1:4096 */
# define WDT_CON_SWDTPS_8192 (13 << WDT_CON_SWDTPS_SHIFT) /* 1:8192 */ # define WDT_CON_SWDTPS_8192 (13 << WDT_CON_SWDTPS_SHIFT) /* 1:8192 */
# define WDT_CON_SWDTPS_16384 (14 << WDT_CON_SWDTPS_SHIFT) /* 1:16384 */ # define WDT_CON_SWDTPS_16384 (14 << WDT_CON_SWDTPS_SHIFT) /* 1:16384 */
# define WDT_CON_SWDTPS_32768 (15 << WDT_CON_SWDTPS_SHIFT) /* 1:32768 */ # define WDT_CON_SWDTPS_32768 (15 << WDT_CON_SWDTPS_SHIFT) /* 1:32768 */
# define WDT_CON_SWDTPS_65536 (16 << WDT_CON_SWDTPS_SHIFT) /* 1:65536 */ # define WDT_CON_SWDTPS_65536 (16 << WDT_CON_SWDTPS_SHIFT) /* 1:65536 */
# define WDT_CON_SWDTPS_131072 (17 << WDT_CON_SWDTPS_SHIFT) /* 1:131072 */ # define WDT_CON_SWDTPS_131072 (17 << WDT_CON_SWDTPS_SHIFT) /* 1:131072 */
# define WDT_CON_SWDTPS_262144 (18 << WDT_CON_SWDTPS_SHIFT) /* 1:262144 */ # define WDT_CON_SWDTPS_262144 (18 << WDT_CON_SWDTPS_SHIFT) /* 1:262144 */
# define WDT_CON_SWDTPS_524288 (19 << WDT_CON_SWDTPS_SHIFT) /* 1:524288 */ # define WDT_CON_SWDTPS_524288 (19 << WDT_CON_SWDTPS_SHIFT) /* 1:524288 */
# define WDT_CON_SWDTPS_1048576 (20 << WDT_CON_SWDTPS_SHIFT) /* 1:1048576 */ # define WDT_CON_SWDTPS_1048576 (20 << WDT_CON_SWDTPS_SHIFT) /* 1:1048576 */
#define WDT_CON_ON (1 << 15 /* Bit 15: Watchdog timer enable */ #define WDT_CON_ON (1 << 15 /* Bit 15: Watchdog timer enable */
/**************************************************************************** /****************************************************************************
* Public Types * Public Types
****************************************************************************/ ****************************************************************************/
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
/**************************************************************************** /****************************************************************************
* Inline Functions * Inline Functions
****************************************************************************/ ****************************************************************************/
/**************************************************************************** /****************************************************************************
* Public Function Prototypes * Public Function Prototypes
****************************************************************************/ ****************************************************************************/
#ifdef __cplusplus #ifdef __cplusplus
#define EXTERN extern "C" #define EXTERN extern "C"
extern "C" { extern "C" {
#else #else
#define EXTERN extern #define EXTERN extern
#endif #endif
#undef EXTERN #undef EXTERN
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* __ASSEMBLY__ */ #endif /* __ASSEMBLY__ */
#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_WDT_H */ #endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_WDT_H */