mirror of
https://gitee.com/mirrors_PX4/PX4-Autopilot.git
synced 2026-10-18 16:03:34 +08:00
Merge branch 'master' into nuttx-merge-5447
This commit is contained in:
px4dev
@@ -9,6 +9,7 @@ choice
|
||||
|
||||
config ARCH_8051
|
||||
bool "8051"
|
||||
select CUSTOM_STACK
|
||||
---help---
|
||||
Intel 8051 architectures and derivaties
|
||||
|
||||
@@ -111,12 +112,30 @@ config ARCH_DMA
|
||||
bool
|
||||
default n
|
||||
|
||||
config ARCH_IRQPRIO
|
||||
bool
|
||||
default n
|
||||
|
||||
config CUSTOM_STACK
|
||||
bool
|
||||
default n
|
||||
|
||||
config ADDRENV
|
||||
bool
|
||||
default n
|
||||
|
||||
config ARCH_STACKDUMP
|
||||
bool "Dump stack on assertions"
|
||||
default n
|
||||
---help---
|
||||
Enable to do stack dumps after assertions
|
||||
|
||||
config ENDIAN_BIG
|
||||
bool "Big Endian Architecture"
|
||||
default n
|
||||
---help---
|
||||
Select if architecture operates using big-endian byte ordering.
|
||||
|
||||
comment "Board Settings"
|
||||
|
||||
config BOARD_LOOPSPERMSEC
|
||||
|
||||
+26
-6
@@ -4,6 +4,8 @@
|
||||
#
|
||||
|
||||
if ARCH_ARM
|
||||
comment "ARM Options"
|
||||
|
||||
choice
|
||||
prompt "ARM chip selection"
|
||||
default ARCH_CHIP_STM32
|
||||
@@ -44,6 +46,7 @@ config ARCH_CHIP_KINETIS
|
||||
bool "Freescale Kinetis"
|
||||
select ARCH_CORTEXM4
|
||||
select ARCH_HAVE_MPU
|
||||
select ARCH_IRQPRIO
|
||||
---help---
|
||||
Freescale Kinetis Architectures (ARM Cortex-M4)
|
||||
|
||||
@@ -51,6 +54,7 @@ config ARCH_CHIP_LM3S
|
||||
bool "TI Stellaris"
|
||||
select ARCH_CORTEXM3
|
||||
select ARCH_HAVE_MPU
|
||||
select ARCH_IRQPRIO
|
||||
---help---
|
||||
TI Stellaris LMS3 architecutres (ARM Cortex-M3)
|
||||
|
||||
@@ -58,6 +62,7 @@ config ARCH_CHIP_LPC17XX
|
||||
bool "NXP LPC17xx"
|
||||
select ARCH_CORTEXM3
|
||||
select ARCH_HAVE_MPU
|
||||
select ARCH_IRQPRIO
|
||||
---help---
|
||||
NXP LPC17xx architectures (ARM Cortex-M3)
|
||||
|
||||
@@ -89,6 +94,7 @@ config ARCH_CHIP_LPC43XX
|
||||
select ARCH_HAVE_CMNVECTOR
|
||||
select ARMV7M_CMNVECTOR
|
||||
select ARCH_HAVE_MPU
|
||||
select ARCH_IRQPRIO
|
||||
---help---
|
||||
NPX LPC43XX architectures (ARM Cortex-M4).
|
||||
|
||||
@@ -96,6 +102,7 @@ config ARCH_CHIP_SAM3U
|
||||
bool "Atmel AT91SAM3U"
|
||||
select ARCH_CORTEXM3
|
||||
select ARCH_HAVE_MPU
|
||||
select ARCH_IRQPRIO
|
||||
---help---
|
||||
Atmel AT91SAM3U architectures (ARM Cortex-M3)
|
||||
|
||||
@@ -104,6 +111,7 @@ config ARCH_CHIP_STM32
|
||||
select ARCH_HAVE_CMNVECTOR
|
||||
select ARCH_HAVE_MPU
|
||||
select ARCH_HAVE_I2CRESET
|
||||
select ARCH_IRQPRIO
|
||||
---help---
|
||||
STMicro STM32 architectures (ARM Cortex-M3/4).
|
||||
|
||||
@@ -153,6 +161,9 @@ config ARCH_CHIP
|
||||
default "stm32" if ARCH_CHIP_STM32
|
||||
default "str71x" if ARCH_CHIP_STR71X
|
||||
|
||||
config ARCH_HAVE_CMNVECTOR
|
||||
bool
|
||||
|
||||
config ARMV7M_CMNVECTOR
|
||||
bool "Use common ARMv7-M vectors"
|
||||
default n
|
||||
@@ -217,12 +228,6 @@ config PAGING
|
||||
If set =y in your configation file, this setting will enable the on-demand
|
||||
paging feature as described in http://www.nuttx.org/NuttXDemandPaging.html.
|
||||
|
||||
config ARCH_IRQPRIO
|
||||
bool "Interrupt priority"
|
||||
default y if ARCH_CORTEXM3 || ARCH_CORTEXM4
|
||||
---help---
|
||||
Select if your board supports interrupt prioritization.
|
||||
|
||||
config BOARD_LOOPSPERMSEC
|
||||
int "Delay loops per millisecond"
|
||||
default 5000
|
||||
@@ -239,6 +244,21 @@ config ARCH_CALIBRATION
|
||||
watch to measure the 100 second delay then adjust BOARD_LOOPSPERMSEC until
|
||||
the delay actually is 100 seconds.
|
||||
|
||||
config DEBUG_HARDFAULT
|
||||
bool "Verbose Hard-Fault Debug"
|
||||
default n
|
||||
depends on DEBUG && (ARCH_CORTEXM3 || ARCH_CORTEXM4)
|
||||
---help---
|
||||
Enables verbose debug output when a hard fault is occurs. This verbose
|
||||
output is sometimes helpful when debugging difficult hard fault problems,
|
||||
but may be more than you typcially want to see.
|
||||
|
||||
if ARCH_CORTEXM3 || ARCH_CORTEXM4
|
||||
source arch/arm/src/armv7-m/Kconfig
|
||||
endif
|
||||
if ARCH_ARM7TDMI || ARCH_ARM926EJS
|
||||
source arch/arm/src/arm/Kconfig
|
||||
endif
|
||||
if ARCH_CHIP_C5471
|
||||
source arch/arm/src/c5471/Kconfig
|
||||
endif
|
||||
|
||||
@@ -0,0 +1,266 @@
|
||||
############################################################################
|
||||
# arch/arm/src/armv7-m/Toolchain.defs
|
||||
#
|
||||
# Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
# Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in
|
||||
# the documentation and/or other materials provided with the
|
||||
# distribution.
|
||||
# 3. Neither the name NuttX nor the names of its contributors may be
|
||||
# used to endorse or promote products derived from this software
|
||||
# without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
############################################################################
|
||||
|
||||
# Setup for the selected toolchain
|
||||
|
||||
#
|
||||
# Handle old-style chip-specific toolchain names in the absence of
|
||||
# a new-style toolchain specification, force the selection of a single
|
||||
# toolchain and allow the selected toolchain to be overridden by a
|
||||
# command-line selection.
|
||||
#
|
||||
|
||||
ifeq ($(filter y, \
|
||||
$(CONFIG_LPC43_ATOLLIC_LITE) \
|
||||
$(CONFIG_STM32_ATOLLIC_LITE) \
|
||||
$(CONFIG_LPC43_ATOLLIC_PRO) \
|
||||
$(CONFIG_STM32_ATOLLIC_PRO) \
|
||||
$(CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC) \
|
||||
),y)
|
||||
CONFIG_ARMV7M_TOOLCHAIN ?= ATOLLIC
|
||||
endif
|
||||
ifeq ($(filter y, \
|
||||
$(CONFIG_KINETIS_BUILDROOT) \
|
||||
$(CONFIG_LM3S_BUILDROOT) \
|
||||
$(CONFIG_LPC17_BUILDROOT) \
|
||||
$(CONFIG_LPC43_BUILDROOT) \
|
||||
$(CONFIG_SAM3U_BUILDROOT) \
|
||||
$(CONFIG_STM32_BUILDROOT) \
|
||||
$(CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT) \
|
||||
),y)
|
||||
CONFIG_ARMV7M_TOOLCHAIN ?= BUILDROOT
|
||||
endif
|
||||
ifeq ($(filter y, \
|
||||
$(CONFIG_LPC17_CODEREDL) \
|
||||
$(CONFIG_ARMV7M_TOOLCHAIN_CODEREDL) \
|
||||
),y)
|
||||
CONFIG_ARMV7M_TOOLCHAIN ?= CODEREDL
|
||||
endif
|
||||
ifeq ($(filter y, \
|
||||
$(CONFIG_LPC17_CODEREDW) \
|
||||
$(CONFIG_LPC43_CODEREDW) \
|
||||
$(CONFIG_ARMV7M_TOOLCHAIN_CODEREDW) \
|
||||
),y)
|
||||
CONFIG_ARMV7M_TOOLCHAIN ?= CODEREDW
|
||||
endif
|
||||
ifeq ($(filter y, \
|
||||
$(CONFIG_KINETIS_CODESOURCERYL) \
|
||||
$(CONFIG_LM3S_CODESOURCERYL) \
|
||||
$(CONFIG_LPC17_CODESOURCERYL) \
|
||||
$(CONFIG_LPC43_CODESOURCERYL) \
|
||||
$(CONFIG_SAM3U_CODESOURCERYL) \
|
||||
$(CONFIG_STM32_CODESOURCERYL) \
|
||||
$(CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL) \
|
||||
),y)
|
||||
CONFIG_ARMV7M_TOOLCHAIN ?= CODESOURCERYL
|
||||
endif
|
||||
ifeq ($(filter y, \
|
||||
$(CONFIG_KINETIS_CODESOURCERYW) \
|
||||
$(CONFIG_LM3S_CODESOURCERYW) \
|
||||
$(CONFIG_LPC17_CODESOURCERYW) \
|
||||
$(CONFIG_LPC43_CODESOURCERYW) \
|
||||
$(CONFIG_SAM3U_CODESOURCERYW) \
|
||||
$(CONFIG_STM32_CODESOURCERYW) \
|
||||
$(CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW) \
|
||||
),y)
|
||||
CONFIG_ARMV7M_TOOLCHAIN ?= CODESOURCERYW
|
||||
endif
|
||||
ifeq ($(filter y, \
|
||||
$(CONFIG_KINETIS_DEVKITARM) \
|
||||
$(CONFIG_LM3S_DEVKITARM) \
|
||||
$(CONFIG_LPC17_DEVKITARM) \
|
||||
$(CONFIG_LPC43_DEVKITARM) \
|
||||
$(CONFIG_SAM3U_DEVKITARM) \
|
||||
$(CONFIG_STM32_DEVKITARM) \
|
||||
$(CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM) \
|
||||
),y)
|
||||
CONFIG_ARMV7M_TOOLCHAIN ?= DEVKITARM
|
||||
endif
|
||||
ifeq ($(filter y, \
|
||||
$(CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI) \
|
||||
),y)
|
||||
CONFIG_ARMV7M_TOOLCHAIN ?= GNU_EABI
|
||||
endif
|
||||
ifeq ($(filter y, \
|
||||
$(CONFIG_STM32_RAISONANCE) \
|
||||
$(CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE) \
|
||||
),y)
|
||||
CONFIG_ARMV7M_TOOLCHAIN ?= RAISONANCE
|
||||
endif
|
||||
|
||||
#
|
||||
# Supported toolchains
|
||||
#
|
||||
# TODO - It's likely that all of these toolchains now support the
|
||||
# CortexM4. Since they are all GCC-based, we could almost
|
||||
# certainly simplify this further.
|
||||
#
|
||||
# Each toolchain definition should set:
|
||||
#
|
||||
# CROSSDEV The GNU toolchain triple (command prefix)
|
||||
# ARCROSSDEV If required, an alternative prefix used when
|
||||
# invoking ar and nm.
|
||||
# ARCHCPUFLAGS CPU-specific flags selecting the instruction set
|
||||
# FPU options, etc.
|
||||
# MAXOPTIMIZATION The maximum optimization level that results in
|
||||
# reliable code generation.
|
||||
#
|
||||
|
||||
# Atollic toolchain under Windows
|
||||
|
||||
ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),ATOLLIC)
|
||||
CROSSDEV = arm-atollic-eabi-
|
||||
ARCROSSDEV = arm-atollic-eabi-
|
||||
ifneq ($(CONFIG_WINDOWS_NATIVE),y)
|
||||
WINTOOL = y
|
||||
endif
|
||||
ifeq ($(CONFIG_ARCH_CORTEXM4),y)
|
||||
ifeq ($(CONFIG_ARCH_FPU),y)
|
||||
ARCHCPUFLAGS = -mcpu=cortex-m4 -mthumb -march=armv7e-m -mfpu=fpv4-sp-d16 -mfloat-abi=hard
|
||||
else
|
||||
ARCHCPUFLAGS = -mcpu=cortex-m4 -mthumb -march=armv7e-m -mfloat-abi=soft
|
||||
endif
|
||||
else ifeq ($(CONFIG_ARCH_CORTEXM3),y)
|
||||
ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
|
||||
endif
|
||||
endif
|
||||
|
||||
# NuttX buildroot under Linux or Cygwin
|
||||
|
||||
ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),BUILDROOT)
|
||||
# OABI
|
||||
# CROSSDEV = arm-nuttx-elf-
|
||||
# ARCROSSDEV = arm-nuttx-elf-
|
||||
# ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft
|
||||
# EABI
|
||||
CROSSDEV = arm-nuttx-eabi-
|
||||
ARCROSSDEV = arm-nuttx-eabi-
|
||||
ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
|
||||
MAXOPTIMIZATION = -Os
|
||||
endif
|
||||
|
||||
# Code Red RedSuite under Linux
|
||||
|
||||
ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),CODEREDL)
|
||||
CROSSDEV = arm-none-eabi-
|
||||
ARCROSSDEV = arm-none-eabi-
|
||||
ifeq ($(CONFIG_ARCH_CORTEXM4),y)
|
||||
ifeq ($(CONFIG_ARCH_FPU),y)
|
||||
ARCHCPUFLAGS = -mcpu=cortex-m4 -mthumb -march=armv7e-m -mfpu=fpv4-sp-d16 -mfloat-abi=hard
|
||||
else
|
||||
ARCHCPUFLAGS = -mcpu=cortex-m4 -mthumb -march=armv7e-m -mfloat-abi=soft
|
||||
endif
|
||||
else ifeq ($(CONFIG_ARCH_CORTEXM3),y)
|
||||
ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
|
||||
endif
|
||||
endif
|
||||
|
||||
# Code Red RedSuite under Windows
|
||||
|
||||
ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),CODEREDW)
|
||||
CROSSDEV = arm-none-eabi-
|
||||
ARCROSSDEV = arm-none-eabi-
|
||||
ifneq ($(CONFIG_WINDOWS_NATIVE),y)
|
||||
WINTOOL = y
|
||||
endif
|
||||
ifeq ($(CONFIG_ARCH_CORTEXM4),y)
|
||||
ifeq ($(CONFIG_ARCH_FPU),y)
|
||||
ARCHCPUFLAGS = -mcpu=cortex-m4 -mthumb -march=armv7e-m -mfpu=fpv4-sp-d16 -mfloat-abi=hard
|
||||
else
|
||||
ARCHCPUFLAGS = -mcpu=cortex-m4 -mthumb -march=armv7e-m -mfloat-abi=soft
|
||||
endif
|
||||
else ifeq ($(CONFIG_ARCH_CORTEXM3),y)
|
||||
ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
|
||||
endif
|
||||
endif
|
||||
|
||||
# CodeSourcery under Linux
|
||||
|
||||
ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),CODESOURCERYL)
|
||||
CROSSDEV = arm-none-eabi-
|
||||
ARCROSSDEV = arm-none-eabi-
|
||||
ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
|
||||
MAXOPTIMIZATION = -O2
|
||||
endif
|
||||
|
||||
# CodeSourcery under Windows
|
||||
|
||||
ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),CODESOURCERYW)
|
||||
CROSSDEV = arm-none-eabi-
|
||||
ARCROSSDEV = arm-none-eabi-
|
||||
ifneq ($(CONFIG_WINDOWS_NATIVE),y)
|
||||
WINTOOL = y
|
||||
endif
|
||||
ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
|
||||
endif
|
||||
|
||||
# devkitARM under Windows
|
||||
|
||||
ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),DEVKITARM)
|
||||
CROSSDEV = arm-eabi-
|
||||
ARCROSSDEV = arm-eabi-
|
||||
ifneq ($(CONFIG_WINDOWS_NATIVE),y)
|
||||
WINTOOL = y
|
||||
endif
|
||||
ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
|
||||
endif
|
||||
|
||||
# Generic GNU EABI toolchain on OS X, Linux or any typical Posix system
|
||||
|
||||
ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),GNU_EABI)
|
||||
CROSSDEV = arm-none-eabi-
|
||||
ARCROSSDEV = arm-none-eabi-
|
||||
MAXOPTIMIZATION = -O3
|
||||
ifeq ($(CONFIG_ARCH_CORTEXM4),y)
|
||||
ifeq ($(CONFIG_ARCH_FPU),y)
|
||||
ARCHCPUFLAGS = -mcpu=cortex-m4 -mthumb -march=armv7e-m -mfpu=fpv4-sp-d16 -mfloat-abi=hard
|
||||
else
|
||||
ARCHCPUFLAGS = -mcpu=cortex-m4 -mthumb -march=armv7e-m -mfloat-abi=soft
|
||||
endif
|
||||
else ifeq ($(CONFIG_ARCH_CORTEXM3),y)
|
||||
ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
|
||||
endif
|
||||
endif
|
||||
|
||||
# Raisonance RIDE7 under Windows
|
||||
|
||||
ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),RAISONANCE)
|
||||
CROSSDEV = arm-none-eabi-
|
||||
ARCROSSDEV = arm-none-eabi-
|
||||
ifneq ($(CONFIG_WINDOWS_NATIVE),y)
|
||||
WINTOOL = y
|
||||
endif
|
||||
ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
|
||||
endif
|
||||
@@ -134,9 +134,9 @@ exception_common:
|
||||
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 3
|
||||
ldr sp, =g_intstackbase
|
||||
push r1 /* Save the MSP on the interrupt stack */
|
||||
push {r1} /* Save the MSP on the interrupt stack */
|
||||
bl up_doirq /* R0=IRQ, R1=register save area on stack */
|
||||
pop r1 /* Recover R1=main stack pointer */
|
||||
pop {r1} /* Recover R1=main stack pointer */
|
||||
#else
|
||||
msr msp, r1 /* We are using the main stack pointer */
|
||||
bl up_doirq /* R0=IRQ, R1=register save area on stack */
|
||||
|
||||
@@ -599,6 +599,15 @@ config STM32_ETH_REMAP
|
||||
|
||||
endmenu
|
||||
|
||||
config STM32_FLASH_PREFETCH
|
||||
bool "Enable FLASH Pre-fetch"
|
||||
depends on STM32_STM32F20XX || STM32_STM32F40XX
|
||||
default n
|
||||
---help---
|
||||
Enable FLASH prefetch and F2 and F4 parts (FLASH pre-fetch is always enabled
|
||||
on F1 parts). Some early revisions of F4 parts do not support FLASH pre-fetch
|
||||
properly and enabling this option may interfere with ADC accuracy.
|
||||
|
||||
choice
|
||||
prompt "JTAG Configuration"
|
||||
default STM32_JTAG_DISABLE
|
||||
|
||||
@@ -110,6 +110,7 @@
|
||||
# define FLASH_ACR_HLFCYA (1 << 3) /* FLASH half cycle access */
|
||||
# define FLASH_ACR_PRTFBE (1 << 4) /* FLASH prefetch enable */
|
||||
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
|
||||
# define FLASH_ACR_PRFTEN (1 << 8) /* FLASH prefetch enable */
|
||||
# define FLASH_ACR_ICEN (1 << 9) /* Bit 9: Instruction cache enable */
|
||||
# define FLASH_ACR_DCEN (1 << 10) /* Bit 10: Data cache enable */
|
||||
# define FLASH_ACR_ICRST (1 << 11) /* Bit 11: Instruction cache reset */
|
||||
|
||||
@@ -51,6 +51,7 @@
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/kmalloc.h>
|
||||
#include <nuttx/clock.h>
|
||||
#include <nuttx/usb/usb.h>
|
||||
#include <nuttx/usb/usbhost.h>
|
||||
|
||||
@@ -149,8 +150,8 @@
|
||||
|
||||
#define STM32_READY_DELAY 200000 /* In loop counts */
|
||||
#define STM32_FLUSH_DELAY 200000 /* In loop counts */
|
||||
#define STM32_SETUP_DELAY 5000 /* In frames */
|
||||
#define STM32_DATANAK_DELAY 5000 /* In frames */
|
||||
#define STM32_SETUP_DELAY (5000 / MSEC_PER_TICK) /* 5 seconds in system ticks */
|
||||
#define STM32_DATANAK_DELAY (5000 / MSEC_PER_TICK) /* 5 seconds in system ticks */
|
||||
|
||||
/* Ever-present MIN/MAX macros */
|
||||
|
||||
@@ -305,7 +306,9 @@ static void stm32_chan_wakeup(FAR struct stm32_usbhost_s *priv,
|
||||
/* Control/data transfer logic *************************************************/
|
||||
|
||||
static void stm32_transfer_start(FAR struct stm32_usbhost_s *priv, int chidx);
|
||||
#if 0 /* Not used */
|
||||
static inline uint16_t stm32_getframe(void);
|
||||
#endif
|
||||
static int stm32_ctrl_sendsetup(FAR struct stm32_usbhost_s *priv,
|
||||
FAR const struct usb_ctrlreq_s *req);
|
||||
static int stm32_ctrl_senddata(FAR struct stm32_usbhost_s *priv,
|
||||
@@ -1182,14 +1185,18 @@ static void stm32_transfer_start(FAR struct stm32_usbhost_s *priv, int chidx)
|
||||
* Name: stm32_getframe
|
||||
*
|
||||
* Description:
|
||||
* Get the current frame number.
|
||||
* Get the current frame number. The frame number (FRNUM) field increments
|
||||
* when a new SOF is transmitted on the USB, and is cleared to 0 when it
|
||||
* reaches 0x3fff.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#if 0 /* Not used */
|
||||
static inline uint16_t stm32_getframe(void)
|
||||
{
|
||||
return (uint16_t)(stm32_getreg(STM32_OTGFS_HFNUM) & OTGFS_HFNUM_FRNUM_MASK);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Name: stm32_ctrl_sendsetup
|
||||
@@ -1203,14 +1210,14 @@ static int stm32_ctrl_sendsetup(FAR struct stm32_usbhost_s *priv,
|
||||
FAR const struct usb_ctrlreq_s *req)
|
||||
{
|
||||
FAR struct stm32_chan_s *chan;
|
||||
uint16_t start;
|
||||
uint16_t elapsed;
|
||||
uint32_t start;
|
||||
uint32_t elapsed;
|
||||
int ret;
|
||||
|
||||
/* Loop while the device reports NAK (and a timeout is not exceeded */
|
||||
|
||||
chan = &priv->chan[priv->ep0out];
|
||||
start = stm32_getframe();
|
||||
start = clock_systimer();
|
||||
|
||||
do
|
||||
{
|
||||
@@ -1258,7 +1265,7 @@ static int stm32_ctrl_sendsetup(FAR struct stm32_usbhost_s *priv,
|
||||
|
||||
/* Get the elapsed time (in frames) */
|
||||
|
||||
elapsed = stm32_getframe() - start;
|
||||
elapsed = clock_systimer() - start;
|
||||
}
|
||||
while (elapsed < STM32_SETUP_DELAY);
|
||||
|
||||
@@ -1367,8 +1374,8 @@ static int stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
|
||||
FAR uint8_t *buffer, size_t buflen)
|
||||
{
|
||||
FAR struct stm32_chan_s *chan;
|
||||
uint16_t start;
|
||||
uint16_t elapsed;
|
||||
uint32_t start;
|
||||
uint32_t elapsed;
|
||||
int ret = OK;
|
||||
|
||||
/* Loop until the transfer completes (i.e., buflen is decremented to zero)
|
||||
@@ -1379,7 +1386,7 @@ static int stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
|
||||
chan->buffer = buffer;
|
||||
chan->buflen = buflen;
|
||||
|
||||
start = stm32_getframe();
|
||||
start = clock_systimer();
|
||||
while (chan->buflen > 0)
|
||||
{
|
||||
/* Set up for the wait BEFORE starting the transfer */
|
||||
@@ -1447,7 +1454,7 @@ static int stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
|
||||
* buffer pointer and buffer size will be unaltered.
|
||||
*/
|
||||
|
||||
elapsed = stm32_getframe() - start;
|
||||
elapsed = clock_systimer() - start;
|
||||
if (ret != -EAGAIN || /* Not a NAK condition OR */
|
||||
elapsed >= STM32_DATANAK_DELAY || /* Timeout has elapsed OR */
|
||||
chan->buflen != buflen) /* Data has been partially transferred */
|
||||
@@ -1474,8 +1481,8 @@ static int stm32_out_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
|
||||
FAR uint8_t *buffer, size_t buflen)
|
||||
{
|
||||
FAR struct stm32_chan_s *chan;
|
||||
uint16_t start;
|
||||
uint16_t elapsed;
|
||||
uint32_t start;
|
||||
uint32_t elapsed;
|
||||
size_t xfrlen;
|
||||
int ret = OK;
|
||||
|
||||
@@ -1484,7 +1491,7 @@ static int stm32_out_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
|
||||
*/
|
||||
|
||||
chan = &priv->chan[chidx];
|
||||
start = stm32_getframe();
|
||||
start = clock_systimer();
|
||||
|
||||
while (buflen > 0)
|
||||
{
|
||||
@@ -1569,7 +1576,7 @@ static int stm32_out_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
|
||||
* buffer pointer and buffer size will be unaltered.
|
||||
*/
|
||||
|
||||
elapsed = stm32_getframe() - start;
|
||||
elapsed = clock_systimer() - start;
|
||||
if (ret != -EAGAIN || /* Not a NAK condition OR */
|
||||
elapsed >= STM32_DATANAK_DELAY || /* Timeout has elapsed OR */
|
||||
chan->buflen != xfrlen) /* Data has been partially transferred */
|
||||
@@ -3540,8 +3547,8 @@ static int stm32_ctrlin(FAR struct usbhost_driver_s *drvr,
|
||||
{
|
||||
struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr;
|
||||
uint16_t buflen;
|
||||
uint16_t start;
|
||||
uint16_t elapsed;
|
||||
uint32_t start;
|
||||
uint32_t elapsed;
|
||||
int retries;
|
||||
int ret;
|
||||
|
||||
@@ -3573,7 +3580,7 @@ static int stm32_ctrlin(FAR struct usbhost_driver_s *drvr,
|
||||
|
||||
/* Get the start time. Loop again until the timeout expires */
|
||||
|
||||
start = stm32_getframe();
|
||||
start = clock_systimer();
|
||||
do
|
||||
{
|
||||
/* Handle the IN data phase (if any) */
|
||||
@@ -3606,7 +3613,7 @@ static int stm32_ctrlin(FAR struct usbhost_driver_s *drvr,
|
||||
|
||||
/* Get the elapsed time (in frames) */
|
||||
|
||||
elapsed = stm32_getframe() - start;
|
||||
elapsed = clock_systimer() - start;
|
||||
}
|
||||
while (elapsed < STM32_DATANAK_DELAY);
|
||||
}
|
||||
@@ -3623,8 +3630,8 @@ static int stm32_ctrlout(FAR struct usbhost_driver_s *drvr,
|
||||
{
|
||||
struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr;
|
||||
uint16_t buflen;
|
||||
uint16_t start;
|
||||
uint16_t elapsed;
|
||||
uint32_t start;
|
||||
uint32_t elapsed;
|
||||
int retries;
|
||||
int ret;
|
||||
|
||||
@@ -3658,7 +3665,7 @@ static int stm32_ctrlout(FAR struct usbhost_driver_s *drvr,
|
||||
|
||||
/* Get the start time. Loop again until the timeout expires */
|
||||
|
||||
start = stm32_getframe();
|
||||
start = clock_systimer();
|
||||
do
|
||||
{
|
||||
/* Handle the data OUT phase (if any) */
|
||||
@@ -3693,7 +3700,7 @@ static int stm32_ctrlout(FAR struct usbhost_driver_s *drvr,
|
||||
|
||||
/* Get the elapsed time (in frames) */
|
||||
|
||||
elapsed = stm32_getframe() - start;
|
||||
elapsed = clock_systimer() - start;
|
||||
}
|
||||
while (elapsed < STM32_DATANAK_DELAY);
|
||||
}
|
||||
|
||||
@@ -96,6 +96,19 @@
|
||||
# endif
|
||||
# endif
|
||||
|
||||
/* Currently RS-485 support cannot be enabled when RXDMA is in use due to lack
|
||||
* of testing - RS-485 support was developed on STM32F1x
|
||||
*/
|
||||
|
||||
# if (defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_RS485)) || \
|
||||
(defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_RS485)) || \
|
||||
(defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_RS485)) || \
|
||||
(defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_RS485)) || \
|
||||
(defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_RS485)) || \
|
||||
(defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_RS485))
|
||||
# error "RXDMA and RS-485 cannot be enabled at the same time for the same U[S]ART"
|
||||
# endif
|
||||
|
||||
/* For the F4, there are alternate DMA channels for USART1 and 6.
|
||||
* Logic in the board.h file make the DMA channel selection by defining
|
||||
* the following in the board.h file.
|
||||
@@ -185,15 +198,11 @@ struct up_dev_s
|
||||
uint8_t parity; /* 0=none, 1=odd, 2=even */
|
||||
uint8_t bits; /* Number of bits (7 or 8) */
|
||||
bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */
|
||||
bool iflow; /* input flow control (RTS) enabled */
|
||||
bool oflow; /* output flow control (CTS) enabled */
|
||||
uint32_t baud; /* Configured baud */
|
||||
#else
|
||||
const uint8_t parity; /* 0=none, 1=odd, 2=even */
|
||||
const uint8_t bits; /* Number of bits (7 or 8) */
|
||||
const bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */
|
||||
const bool iflow; /* input flow control (RTS) enabled */
|
||||
const bool oflow; /* output flow control (CTS) enabled */
|
||||
const uint32_t baud; /* Configured baud */
|
||||
#endif
|
||||
|
||||
@@ -219,13 +228,18 @@ struct up_dev_s
|
||||
uint32_t rxdmanext; /* Next byte in the DMA buffer to be read */
|
||||
char *const rxfifo; /* Receive DMA buffer */
|
||||
#endif
|
||||
|
||||
#ifdef HAVE_RS485
|
||||
const uint32_t rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin configuration */
|
||||
const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */
|
||||
#endif
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Private Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
static void up_set_format(struct uart_dev_s *dev);
|
||||
static void up_setspeed(struct uart_dev_s *dev);
|
||||
static int up_setup(struct uart_dev_s *dev);
|
||||
static void up_shutdown(struct uart_dev_s *dev);
|
||||
static int up_attach(struct uart_dev_s *dev);
|
||||
@@ -397,8 +411,6 @@ static struct up_dev_s g_usart1priv =
|
||||
.parity = CONFIG_USART1_PARITY,
|
||||
.bits = CONFIG_USART1_BITS,
|
||||
.stopbits2 = CONFIG_USART1_2STOP,
|
||||
.iflow = false,
|
||||
.oflow = false,
|
||||
.baud = CONFIG_USART1_BAUD,
|
||||
.apbclock = STM32_PCLK2_FREQUENCY,
|
||||
.usartbase = STM32_USART1_BASE,
|
||||
@@ -415,6 +427,15 @@ static struct up_dev_s g_usart1priv =
|
||||
.rxfifo = g_usart1rxfifo,
|
||||
#endif
|
||||
.vector = up_interrupt_usart1,
|
||||
|
||||
#ifdef CONFIG_USART1_RS485
|
||||
.rs485_dir_gpio = GPIO_USART1_RS485_DIR,
|
||||
# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
|
||||
.rs485_dir_polarity = false,
|
||||
# else
|
||||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
@@ -450,8 +471,6 @@ static struct up_dev_s g_usart2priv =
|
||||
.parity = CONFIG_USART2_PARITY,
|
||||
.bits = CONFIG_USART2_BITS,
|
||||
.stopbits2 = CONFIG_USART2_2STOP,
|
||||
.iflow = false,
|
||||
.oflow = false,
|
||||
.baud = CONFIG_USART2_BAUD,
|
||||
.apbclock = STM32_PCLK1_FREQUENCY,
|
||||
.usartbase = STM32_USART2_BASE,
|
||||
@@ -468,6 +487,15 @@ static struct up_dev_s g_usart2priv =
|
||||
.rxfifo = g_usart2rxfifo,
|
||||
#endif
|
||||
.vector = up_interrupt_usart2,
|
||||
|
||||
#ifdef CONFIG_USART2_RS485
|
||||
.rs485_dir_gpio = GPIO_USART2_RS485_DIR,
|
||||
# if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
|
||||
.rs485_dir_polarity = false,
|
||||
# else
|
||||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
@@ -503,8 +531,6 @@ static struct up_dev_s g_usart3priv =
|
||||
.parity = CONFIG_USART3_PARITY,
|
||||
.bits = CONFIG_USART3_BITS,
|
||||
.stopbits2 = CONFIG_USART3_2STOP,
|
||||
.iflow = false,
|
||||
.oflow = false,
|
||||
.baud = CONFIG_USART3_BAUD,
|
||||
.apbclock = STM32_PCLK1_FREQUENCY,
|
||||
.usartbase = STM32_USART3_BASE,
|
||||
@@ -521,6 +547,15 @@ static struct up_dev_s g_usart3priv =
|
||||
.rxfifo = g_usart3rxfifo,
|
||||
#endif
|
||||
.vector = up_interrupt_usart3,
|
||||
|
||||
#ifdef CONFIG_USART3_RS485
|
||||
.rs485_dir_gpio = GPIO_USART3_RS485_DIR,
|
||||
# if (CONFIG_USART3_RS485_DIR_POLARITY == 0)
|
||||
.rs485_dir_polarity = false,
|
||||
# else
|
||||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
@@ -556,20 +591,31 @@ static struct up_dev_s g_uart4priv =
|
||||
.parity = CONFIG_UART4_PARITY,
|
||||
.bits = CONFIG_UART4_BITS,
|
||||
.stopbits2 = CONFIG_UART4_2STOP,
|
||||
.iflow = false,
|
||||
.oflow = false,
|
||||
.baud = CONFIG_UART4_BAUD,
|
||||
.apbclock = STM32_PCLK1_FREQUENCY,
|
||||
.usartbase = STM32_UART4_BASE,
|
||||
.tx_gpio = GPIO_UART4_TX,
|
||||
.rx_gpio = GPIO_UART4_RX,
|
||||
.cts_gpio = 0, /* flow control not supported on this port */
|
||||
.rts_gpio = 0, /* flow control not supported on this port */
|
||||
#ifdef GPIO_UART4_CTS
|
||||
.cts_gpio = GPIO_UART4_CTS,
|
||||
#endif
|
||||
#ifdef GPIO_UART4_RTS
|
||||
.rts_gpio = GPIO_UART4_RTS,
|
||||
#endif
|
||||
#ifdef CONFIG_UART4_RXDMA
|
||||
.rxdma_channel = DMAMAP_UART4_RX,
|
||||
.rxfifo = g_uart4rxfifo,
|
||||
#endif
|
||||
.vector = up_interrupt_uart4,
|
||||
|
||||
#ifdef CONFIG_UART4_RS485
|
||||
.rs485_dir_gpio = GPIO_UART4_RS485_DIR,
|
||||
# if (CONFIG_UART4_RS485_DIR_POLARITY == 0)
|
||||
.rs485_dir_polarity = false,
|
||||
# else
|
||||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
@@ -605,20 +651,31 @@ static struct up_dev_s g_uart5priv =
|
||||
.parity = CONFIG_UART5_PARITY,
|
||||
.bits = CONFIG_UART5_BITS,
|
||||
.stopbits2 = CONFIG_UART5_2STOP,
|
||||
.iflow = false,
|
||||
.oflow = false,
|
||||
.baud = CONFIG_UART5_BAUD,
|
||||
.apbclock = STM32_PCLK1_FREQUENCY,
|
||||
.usartbase = STM32_UART5_BASE,
|
||||
.tx_gpio = GPIO_UART5_TX,
|
||||
.rx_gpio = GPIO_UART5_RX,
|
||||
.cts_gpio = 0, /* flow control not supported on this port */
|
||||
.rts_gpio = 0, /* flow control not supported on this port */
|
||||
#ifdef GPIO_UART5_CTS
|
||||
.cts_gpio = GPIO_UART5_CTS,
|
||||
#endif
|
||||
#ifdef GPIO_UART5_RTS
|
||||
.rts_gpio = GPIO_UART5_RTS,
|
||||
#endif
|
||||
#ifdef CONFIG_UART5_RXDMA
|
||||
.rxdma_channel = DMAMAP_UART5_RX,
|
||||
.rxfifo = g_uart5rxfifo,
|
||||
#endif
|
||||
.vector = up_interrupt_uart5,
|
||||
|
||||
#ifdef CONFIG_UART5_RS485
|
||||
.rs485_dir_gpio = GPIO_UART5_RS485_DIR,
|
||||
# if (CONFIG_UART5_RS485_DIR_POLARITY == 0)
|
||||
.rs485_dir_polarity = false,
|
||||
# else
|
||||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
@@ -654,8 +711,6 @@ static struct up_dev_s g_usart6priv =
|
||||
.parity = CONFIG_USART6_PARITY,
|
||||
.bits = CONFIG_USART6_BITS,
|
||||
.stopbits2 = CONFIG_USART6_2STOP,
|
||||
.iflow = false,
|
||||
.oflow = false,
|
||||
.baud = CONFIG_USART6_BAUD,
|
||||
.apbclock = STM32_PCLK2_FREQUENCY,
|
||||
.usartbase = STM32_USART6_BASE,
|
||||
@@ -672,6 +727,15 @@ static struct up_dev_s g_usart6priv =
|
||||
.rxfifo = g_usart6rxfifo,
|
||||
#endif
|
||||
.vector = up_interrupt_usart6,
|
||||
|
||||
#ifdef CONFIG_USART6_RS485
|
||||
.rs485_dir_gpio = GPIO_USART6_RS485_DIR,
|
||||
# if (CONFIG_USART6_RS485_DIR_POLARITY == 0)
|
||||
.rs485_dir_polarity = false,
|
||||
# else
|
||||
.rs485_dir_polarity = true,
|
||||
# endif
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
@@ -744,8 +808,8 @@ static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie)
|
||||
/* And restore the interrupt state (see the interrupt enable/usage table above) */
|
||||
|
||||
cr = up_serialin(priv, STM32_USART_CR1_OFFSET);
|
||||
cr &= ~(USART_CR1_RXNEIE|USART_CR1_TXEIE|USART_CR1_PEIE);
|
||||
cr |= (ie & (USART_CR1_RXNEIE|USART_CR1_TXEIE|USART_CR1_PEIE));
|
||||
cr &= ~(USART_CR1_USED_INTS);
|
||||
cr |= (ie & (USART_CR1_USED_INTS));
|
||||
up_serialout(priv, STM32_USART_CR1_OFFSET, cr);
|
||||
|
||||
cr = up_serialin(priv, STM32_USART_CR3_OFFSET);
|
||||
@@ -772,7 +836,7 @@ static inline void up_disableusartint(struct up_dev_s *priv, uint16_t *ie)
|
||||
* USART_CR1_IDLEIE 4 USART_SR_IDLE Idle Line Detected (not used)
|
||||
* USART_CR1_RXNEIE 5 USART_SR_RXNE Received Data Ready to be Read
|
||||
* " " USART_SR_ORE Overrun Error Detected
|
||||
* USART_CR1_TCIE 6 USART_SR_TC Transmission Complete (not used)
|
||||
* USART_CR1_TCIE 6 USART_SR_TC Transmission Complete (used only for RS-485)
|
||||
* USART_CR1_TXEIE 7 USART_SR_TXE Transmit Data Register Empty
|
||||
* USART_CR1_PEIE 8 USART_SR_PE Parity Error
|
||||
*
|
||||
@@ -791,7 +855,7 @@ static inline void up_disableusartint(struct up_dev_s *priv, uint16_t *ie)
|
||||
* overlap. This logic would fail if we needed the break interrupt!
|
||||
*/
|
||||
|
||||
*ie = (cr1 & (USART_CR1_RXNEIE|USART_CR1_TXEIE|USART_CR1_PEIE)) | (cr3 & USART_CR3_EIE);
|
||||
*ie = (cr1 & (USART_CR1_USED_INTS)) | (cr3 & USART_CR3_EIE);
|
||||
}
|
||||
|
||||
/* Disable all interrupts */
|
||||
@@ -820,22 +884,21 @@ static int up_dma_nextrx(struct up_dev_s *priv)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_set_format
|
||||
* Name: up_setspeed
|
||||
*
|
||||
* Description:
|
||||
* Set the serial line format and speed.
|
||||
* Set the serial line speed.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef CONFIG_SUPPRESS_UART_CONFIG
|
||||
static void up_set_format(struct uart_dev_s *dev)
|
||||
static void up_setspeed(struct uart_dev_s *dev)
|
||||
{
|
||||
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
|
||||
uint32_t usartdiv32;
|
||||
uint32_t mantissa;
|
||||
uint32_t fraction;
|
||||
uint32_t brr;
|
||||
uint32_t regval;
|
||||
|
||||
/* Configure the USART Baud Rate. The baud rate for the receiver and
|
||||
* transmitter (Rx and Tx) are both set to the same value as programmed
|
||||
@@ -853,64 +916,20 @@ static void up_set_format(struct uart_dev_s *dev)
|
||||
* usartdiv32 = 32 * usartdiv = fCK / (baud/2)
|
||||
*/
|
||||
|
||||
usartdiv32 = priv->apbclock / (priv->baud >> 1);
|
||||
usartdiv32 = priv->apbclock / (priv->baud >> 1);
|
||||
|
||||
/* The mantissa part is then */
|
||||
/* The mantissa part is then */
|
||||
|
||||
mantissa = usartdiv32 >> 5;
|
||||
brr = mantissa << USART_BRR_MANT_SHIFT;
|
||||
mantissa = usartdiv32 >> 5;
|
||||
brr = mantissa << USART_BRR_MANT_SHIFT;
|
||||
|
||||
/* The fractional remainder (with rounding) */
|
||||
|
||||
fraction = (usartdiv32 - (mantissa << 5) + 1) >> 1;
|
||||
brr |= fraction << USART_BRR_FRAC_SHIFT;
|
||||
up_serialout(priv, STM32_USART_BRR_OFFSET, brr);
|
||||
|
||||
/* Configure parity mode */
|
||||
|
||||
regval = up_serialin(priv, STM32_USART_CR1_OFFSET);
|
||||
regval &= ~(USART_CR1_PCE|USART_CR1_PS);
|
||||
|
||||
if (priv->parity == 1) /* Odd parity */
|
||||
{
|
||||
regval |= (USART_CR1_PCE|USART_CR1_PS);
|
||||
}
|
||||
else if (priv->parity == 2) /* Even parity */
|
||||
{
|
||||
regval |= USART_CR1_PCE;
|
||||
}
|
||||
|
||||
up_serialout(priv, STM32_USART_CR1_OFFSET, regval);
|
||||
|
||||
/* Configure STOP bits */
|
||||
|
||||
regval = up_serialin(priv, STM32_USART_CR2_OFFSET);
|
||||
regval &= ~(USART_CR2_STOP_MASK);
|
||||
|
||||
if (priv->stopbits2)
|
||||
{
|
||||
regval |= USART_CR2_STOP2;
|
||||
}
|
||||
up_serialout(priv, STM32_USART_CR2_OFFSET, regval);
|
||||
|
||||
/* Configure hardware flow control */
|
||||
|
||||
regval = up_serialin(priv, STM32_USART_CR3_OFFSET);
|
||||
regval &= ~(USART_CR3_CTSE|USART_CR3_RTSE);
|
||||
|
||||
if (priv->iflow && (priv->rts_gpio != 0))
|
||||
{
|
||||
regval |= USART_CR3_RTSE;
|
||||
}
|
||||
if (priv->oflow && (priv->cts_gpio != 0))
|
||||
{
|
||||
regval |= USART_CR3_CTSE;
|
||||
}
|
||||
|
||||
up_serialout(priv, STM32_USART_CR3_OFFSET, regval);
|
||||
/* The fractional remainder (with rounding) */
|
||||
|
||||
fraction = (usartdiv32 - (mantissa << 5) + 1) >> 1;
|
||||
brr |= fraction << USART_BRR_FRAC_SHIFT;
|
||||
up_serialout(priv, STM32_USART_BRR_OFFSET, brr);
|
||||
}
|
||||
#endif /* CONFIG_SUPPRESS_UART_CONFIG */
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_setup
|
||||
@@ -946,29 +965,52 @@ static int up_setup(struct uart_dev_s *dev)
|
||||
stm32_configgpio(priv->rts_gpio);
|
||||
}
|
||||
|
||||
#if HAVE_RS485
|
||||
if (priv->rs485_dir_gpio != 0)
|
||||
{
|
||||
stm32_configgpio(priv->rs485_dir_gpio);
|
||||
stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Configure CR2 */
|
||||
/* Clear CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */
|
||||
/* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */
|
||||
|
||||
regval = up_serialin(priv, STM32_USART_CR2_OFFSET);
|
||||
regval &= ~(USART_CR2_CLKEN|USART_CR2_CPOL|
|
||||
regval &= ~(USART_CR2_STOP_MASK|USART_CR2_CLKEN|USART_CR2_CPOL|
|
||||
USART_CR2_CPHA|USART_CR2_LBCL|USART_CR2_LBDIE);
|
||||
|
||||
/* Configure STOP bits */
|
||||
|
||||
if (priv->stopbits2)
|
||||
{
|
||||
regval |= USART_CR2_STOP2;
|
||||
}
|
||||
up_serialout(priv, STM32_USART_CR2_OFFSET, regval);
|
||||
|
||||
/* Configure CR1 */
|
||||
/* Clear M, TE, REm and all interrupt enable bits */
|
||||
/* Clear M, PCE, PS, TE, REm and all interrupt enable bits */
|
||||
|
||||
regval = up_serialin(priv, STM32_USART_CR1_OFFSET);
|
||||
regval &= ~(USART_CR1_M|USART_CR1_TE|
|
||||
regval &= ~(USART_CR1_M|USART_CR1_PCE|USART_CR1_PS|USART_CR1_TE|
|
||||
USART_CR1_RE|USART_CR1_ALLINTS);
|
||||
|
||||
/* Configure word length */
|
||||
/* Configure word length and parity mode */
|
||||
|
||||
if (priv->bits == 9) /* Default: 1 start, 8 data, n stop */
|
||||
{
|
||||
regval |= USART_CR1_M; /* 1 start, 9 data, n stop */
|
||||
}
|
||||
|
||||
if (priv->parity == 1) /* Odd parity */
|
||||
{
|
||||
regval |= (USART_CR1_PCE|USART_CR1_PS);
|
||||
}
|
||||
else if (priv->parity == 2) /* Even parity */
|
||||
{
|
||||
regval |= USART_CR1_PCE;
|
||||
}
|
||||
|
||||
up_serialout(priv, STM32_USART_CR1_OFFSET, regval);
|
||||
|
||||
/* Configure CR3 */
|
||||
@@ -981,22 +1023,20 @@ static int up_setup(struct uart_dev_s *dev)
|
||||
|
||||
up_serialout(priv, STM32_USART_CR3_OFFSET, regval);
|
||||
|
||||
/* Configure the USART line format and speed. */
|
||||
/* Configure the USART Baud Rate. */
|
||||
|
||||
up_set_format(dev);
|
||||
up_setspeed(dev);
|
||||
|
||||
/* Enable Rx, Tx, and the USART */
|
||||
|
||||
regval = up_serialin(priv, STM32_USART_CR1_OFFSET);
|
||||
regval |= (USART_CR1_UE|USART_CR1_TE|USART_CR1_RE);
|
||||
up_serialout(priv, STM32_USART_CR1_OFFSET, regval);
|
||||
|
||||
#endif /* CONFIG_SUPPRESS_UART_CONFIG */
|
||||
#endif
|
||||
|
||||
/* Set up the cached interrupt enables value */
|
||||
|
||||
up_restoreusartint(priv, 0);
|
||||
|
||||
priv->ie = 0;
|
||||
return OK;
|
||||
}
|
||||
|
||||
@@ -1016,15 +1056,12 @@ static int up_dma_setup(struct uart_dev_s *dev)
|
||||
int result;
|
||||
uint32_t regval;
|
||||
|
||||
/* Do the basic UART setup first, unless we are the console */
|
||||
/* Do the basic UART setup first */
|
||||
|
||||
if (!dev->isconsole)
|
||||
{
|
||||
result = up_setup(dev);
|
||||
if (result != OK)
|
||||
{
|
||||
return result;
|
||||
}
|
||||
result = up_setup(dev);
|
||||
if (result != OK)
|
||||
{
|
||||
return result;
|
||||
}
|
||||
|
||||
/* Acquire the DMA channel. This should always succeed. */
|
||||
@@ -1217,7 +1254,7 @@ static int up_interrupt_common(struct up_dev_s *priv)
|
||||
* USART_CR1_IDLEIE 4 USART_SR_IDLE Idle Line Detected (not used)
|
||||
* USART_CR1_RXNEIE 5 USART_SR_RXNE Received Data Ready to be Read
|
||||
* " " USART_SR_ORE Overrun Error Detected
|
||||
* USART_CR1_TCIE 6 USART_SR_TC Transmission Complete (not used)
|
||||
* USART_CR1_TCIE 6 USART_SR_TC Transmission Complete (used only for RS-485)
|
||||
* USART_CR1_TXEIE 7 USART_SR_TXE Transmit Data Register Empty
|
||||
* USART_CR1_PEIE 8 USART_SR_PE Parity Error
|
||||
*
|
||||
@@ -1232,6 +1269,21 @@ static int up_interrupt_common(struct up_dev_s *priv)
|
||||
* being used.
|
||||
*/
|
||||
|
||||
#ifdef HAVE_RS485
|
||||
/* Transmission of whole buffer is over - TC is set, TXEIE is cleared.
|
||||
* Note - this should be first, to have the most recent TC bit value from
|
||||
* SR register - sending data affects TC, but without refresh we will not
|
||||
* know that...
|
||||
*/
|
||||
|
||||
if ((priv->sr & USART_SR_TC) != 0 && (priv->ie & USART_CR1_TCIE) != 0 &&
|
||||
(priv->ie & USART_CR1_TXEIE) == 0)
|
||||
{
|
||||
stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity);
|
||||
up_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Handle incoming, receive bytes. */
|
||||
|
||||
if ((priv->sr & USART_SR_RXNE) != 0 && (priv->ie & USART_CR1_RXNEIE) != 0)
|
||||
@@ -1265,13 +1317,14 @@ static int up_interrupt_common(struct up_dev_s *priv)
|
||||
|
||||
if ((priv->sr & USART_SR_TXE) != 0 && (priv->ie & USART_CR1_TXEIE) != 0)
|
||||
{
|
||||
/* Transmit data regiser empty ... process outgoing bytes */
|
||||
/* Transmit data register empty ... process outgoing bytes */
|
||||
|
||||
uart_xmitchars(&priv->dev);
|
||||
handled = true;
|
||||
}
|
||||
}
|
||||
return OK;
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -1318,21 +1371,12 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
|
||||
break;
|
||||
}
|
||||
|
||||
cfsetispeed(termiosp, priv->baud);
|
||||
|
||||
/* Note that since we only support 8/9 bit modes and
|
||||
* there is no way to report 9-bit mode, we always claim 8.
|
||||
/* TODO: Other termios fields are not yet returned.
|
||||
* Note that only cfsetospeed is not necessary because we have
|
||||
* knowledge that only one speed is supported.
|
||||
*/
|
||||
|
||||
termiosp->c_cflag =
|
||||
((priv->parity != 0) ? PARENB : 0) |
|
||||
((priv->parity == 1) ? PARODD : 0) |
|
||||
((priv->stopbits2) ? CSTOPB : 0) |
|
||||
((priv->oflow) ? CCTS_OFLOW : 0) |
|
||||
((priv->iflow) ? CRTS_IFLOW : 0) |
|
||||
CS8;
|
||||
|
||||
/* TODO: CCTS_IFLOW, CCTS_OFLOW */
|
||||
cfsetispeed(termiosp, priv->baud);
|
||||
}
|
||||
break;
|
||||
|
||||
@@ -1346,48 +1390,16 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
|
||||
break;
|
||||
}
|
||||
|
||||
/* Perform some sanity checks before accepting any changes */
|
||||
|
||||
if (((termiosp->c_cflag & CSIZE) != CS8) ||
|
||||
((termiosp->c_cflag & CCTS_OFLOW) && (priv->cts_gpio == 0)) ||
|
||||
((termiosp->c_cflag & CRTS_IFLOW) && (priv->rts_gpio == 0)))
|
||||
{
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
if (termiosp->c_cflag & PARENB)
|
||||
{
|
||||
priv->parity = (termiosp->c_cflag & PARODD) ? 1 : 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
priv->parity = 0;
|
||||
}
|
||||
|
||||
priv->stopbits2 = (termiosp->c_cflag & CSTOPB) != 0;
|
||||
priv->oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0;
|
||||
priv->iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0;
|
||||
|
||||
/* Note that since there is no way to request 9-bit mode
|
||||
* and no way to support 5/6/7-bit modes, we ignore them
|
||||
* all here.
|
||||
*/
|
||||
|
||||
/* Note that only cfgetispeed is used because we have knowledge
|
||||
/* TODO: Handle other termios settings.
|
||||
* Note that only cfgetispeed is used besued we have knowledge
|
||||
* that only one speed is supported.
|
||||
*/
|
||||
|
||||
priv->baud = cfgetispeed(termiosp);
|
||||
|
||||
/* effect the changes immediately - note that we do not implement
|
||||
* TCSADRAIN / TCSAFLUSH
|
||||
*/
|
||||
|
||||
up_set_format(dev);
|
||||
up_setspeed(dev);
|
||||
}
|
||||
break;
|
||||
#endif /* CONFIG_SERIAL_TERMIOS */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USART_BREAKS
|
||||
case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
|
||||
@@ -1611,6 +1623,10 @@ static bool up_dma_rxavailable(struct uart_dev_s *dev)
|
||||
static void up_send(struct uart_dev_s *dev, int ch)
|
||||
{
|
||||
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
|
||||
#ifdef HAVE_RS485
|
||||
if (priv->rs485_dir_gpio != 0)
|
||||
stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity);
|
||||
#endif
|
||||
up_serialout(priv, STM32_USART_DR_OFFSET, (uint32_t)ch);
|
||||
}
|
||||
|
||||
@@ -1631,7 +1647,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
|
||||
*
|
||||
* Enable Bit Status Meaning Usage
|
||||
* ------------------ --- --------------- ---------------------------- ----------
|
||||
* USART_CR1_TCIE 6 USART_SR_TC Transmission Complete (not used)
|
||||
* USART_CR1_TCIE 6 USART_SR_TC Transmission Complete (used only for RS-485)
|
||||
* USART_CR1_TXEIE 7 USART_SR_TXE Transmit Data Register Empty
|
||||
* USART_CR3_CTSIE 10 USART_SR_CTS CTS flag (not used)
|
||||
*/
|
||||
@@ -1642,7 +1658,20 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
|
||||
/* Set to receive an interrupt when the TX data register is empty */
|
||||
|
||||
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
|
||||
up_restoreusartint(priv, priv->ie | USART_CR1_TXEIE);
|
||||
uint16_t ie = priv->ie | USART_CR1_TXEIE;
|
||||
|
||||
/* If RS-485 is supported on this U[S]ART, then also enable the
|
||||
* transmission complete interrupt.
|
||||
*/
|
||||
|
||||
# ifdef HAVE_RS485
|
||||
if (priv->rs485_dir_gpio != 0)
|
||||
{
|
||||
ie |= USART_CR1_TCIE;
|
||||
}
|
||||
# endif
|
||||
|
||||
up_restoreusartint(priv, ie);
|
||||
|
||||
/* Fake a TX interrupt here by just calling uart_xmitchars() with
|
||||
* interrupts disabled (note this may recurse).
|
||||
@@ -1657,6 +1686,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
|
||||
|
||||
up_restoreusartint(priv, priv->ie & ~USART_CR1_TXEIE);
|
||||
}
|
||||
|
||||
irqrestore(flags);
|
||||
}
|
||||
|
||||
|
||||
@@ -631,7 +631,11 @@ static void stm32_stdclockconfig(void)
|
||||
|
||||
/* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */
|
||||
|
||||
#ifdef STM32_FLASH_PREFETCH
|
||||
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN);
|
||||
#else
|
||||
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
|
||||
#endif
|
||||
putreg32(regval, STM32_FLASH_ACR);
|
||||
|
||||
/* Select the main PLL as system clock source */
|
||||
|
||||
@@ -633,7 +633,11 @@ static void stm32_stdclockconfig(void)
|
||||
|
||||
/* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */
|
||||
|
||||
#ifdef STM32_FLASH_PREFETCH
|
||||
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN);
|
||||
#else
|
||||
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
|
||||
#endif
|
||||
putreg32(regval, STM32_FLASH_ACR);
|
||||
|
||||
/* Select the main PLL as system clock source */
|
||||
|
||||
Reference in New Issue
Block a user