From bf36d272bf6675c8b645ae8596ec5bead6904c10 Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Fri, 13 Jul 2018 11:34:07 -0700 Subject: [PATCH] nxphlite-v3:extend board_rc_input to pass UxART --- src/drivers/boards/nxphlite-v3/init.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/drivers/boards/nxphlite-v3/init.c b/src/drivers/boards/nxphlite-v3/init.c index 5f15a372ec..c88fe165cf 100644 --- a/src/drivers/boards/nxphlite-v3/init.c +++ b/src/drivers/boards/nxphlite-v3/init.c @@ -173,13 +173,13 @@ int board_read_VBUS_state(void) * ************************************************************************************/ -__EXPORT void board_rc_input(bool invert_on) +__EXPORT void board_rc_input(bool invert_on, uint32_t uxart_base) { irqstate_t irqstate = px4_enter_critical_section(); - uint8_t s2 = getreg8(KINETIS_UART_S2_OFFSET + RC_UXART_BASE); - uint8_t c3 = getreg8(KINETIS_UART_C3_OFFSET + RC_UXART_BASE); + uint8_t s2 = getreg8(KINETIS_UART_S2_OFFSET + uxart_base); + uint8_t c3 = getreg8(KINETIS_UART_C3_OFFSET + uxart_base); /* {R|T}XINV bit fields can written any time */ @@ -192,8 +192,8 @@ __EXPORT void board_rc_input(bool invert_on) c3 &= ~(UART_C3_TXINV); } - putreg8(s2, KINETIS_UART_S2_OFFSET + RC_UXART_BASE); - putreg8(c3, KINETIS_UART_C3_OFFSET + RC_UXART_BASE); + putreg8(s2, KINETIS_UART_S2_OFFSET + uxart_base); + putreg8(c3, KINETIS_UART_C3_OFFSET + uxart_base); leave_critical_section(irqstate); }