Adding px4fmu-v5

2026-10-16 03:23:34 +08:00 · 2016-12-21 08:34:21 +01:00
parent 925102464b
commit bca8767981
20 changed files with 5240 additions and 0 deletions
@@ -0,0 +1,49 @@
+############################################################################
+#
+#   Copyright (c) 2016 PX4 Development Team. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name PX4 nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+px4_add_module(
+	MODULE drivers__boards__px4fmu-v5
+	COMPILE_FLAGS
+		-Os
+	SRCS
+		../common/board_name.c
+		../common/board_dma_alloc.c
+#		WIP px4fmu_can.c
+		px4fmu_init.c
+		px4fmu_sdio.c
+		px4fmu_timer_config.c
+		px4fmu_spi.c
+		px4fmu_usb.c
+		px4fmu_led.c
+	DEPENDS
+		platforms__common
+	)
@@ -0,0 +1,453 @@
+/****************************************************************************
+ *
+ *   Copyright (c) 2016 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file board_config.h
+ *
+ * PX4FMU-v5 internal definitions
+ */
+
+#pragma once
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <px4_config.h>
+#include <nuttx/compiler.h>
+#include <stdint.h>
+
+__BEGIN_DECLS
+
+/* these headers are not C++ safe */
+#include <chip.h>
+#include <stm32_gpio.h>
+#include <arch/board/board.h>
+
+/****************************************************************************************************
+ * Definitions
+ ****************************************************************************************************/
+/* Configuration ************************************************************************************/
+
+/* PX4FMU GPIOs ***********************************************************************************/
+/* LEDs */
+#define GPIO_LED1              /* PB1 */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_LED2              /* PC6 */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN6)
+#define GPIO_LED3              /* PC7 */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN7)
+
+#define GPIO_LED_RED 	GPIO_LED1
+#define GPIO_LED_GREEN 	GPIO_LED2
+#define GPIO_LED_BLUE   GPIO_LED3
+
+/*  Define the Chip Selects */
+
+#define GPIO_SPI_CS_ICM20689    /* PF2 */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTF|GPIO_PIN2)
+#define GPIO_SPI_CS_ICM20602    /* PF3 */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTF|GPIO_PIN3)
+#define GPIO_SPI_CS_BMI055_GYR  /* PF4 */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTF|GPIO_PIN4)
+#define GPIO_SPI_CS_MEMORY      /* PF5 */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTF|GPIO_PIN5)
+#define GPIO_SPI_CS_MS5611      /* PF10 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTF|GPIO_PIN10)
+#define GPIO_SPI_CS_BMI055_ACC  /* PG10 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTG|GPIO_PIN10)
+
+#define SPI6_EXTERNAL1_CS1     /* PI4  */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTI|GPIO_PIN4)
+#define SPI6_EXTERNAL1_CS2     /* PI10 */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTI|GPIO_PIN10)
+#define SPI6_EXTERNAL1_CS3     /* PI11 */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTI|GPIO_PIN11)
+#define SPI6_EXTERNAL2_CS1     /* PI6  */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTI|GPIO_PIN6)
+#define SPI6_EXTERNAL2_CS2     /* PI7  */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTI|GPIO_PIN7)
+#define SPI6_EXTERNAL2_CS3     /* PI8  */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTI|GPIO_PIN8)
+
+/*  Define the Ready interrupts */ /* NOT FMUv5 test HW ONLY*/
+
+#define GPIO_ICM20689_DRDY1    /* PB4 */   (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTB|GPIO_PIN4)
+#define GPIO_BMI055_DRDY2_GYRO /* PB14 */  (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_BMI055_DRDY3_ACC  /* PB15 */  (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTB|GPIO_PIN15)
+#define GPIO_ICM20602_DRDY4    /* PC5  */  (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTC|GPIO_PIN5)
+#define GPIO_BMI055_DRDY5_GYRO /* PC13 */  (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTC|GPIO_PIN13)
+#define GPIO_BMI055_DRDY6_ACC  /* PD10 */  (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTD|GPIO_PIN10)
+
+/*
+ *  Define the ability to shut off off the sensor signals
+ *  by changing the signals to inputs
+ */
+
+#define _PIN_OFF(def) (((def) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | (GPIO_INPUT|GPIO_PULLDOWN|GPIO_SPEED_2MHz))
+
+
+#define GPIO_DRDY_OFF_ICM20689_DRDY1    _PIN_OFF(GPIO_ICM20689_DRDY1)
+#define GPIO_DRDY_OFF_BMI055_DRDY2_GYRO _PIN_OFF(GPIO_BMI055_DRDY2_GYRO)
+#define GPIO_DRDY_OFF_BMI055_DRDY3_ACC  _PIN_OFF(GPIO_BMI055_DRDY3_ACC)
+#define GPIO_DRDY_OFF_ICM20602_DRDY4    _PIN_OFF(GPIO_ICM20602_DRDY4)
+#define GPIO_DRDY_OFF_BMI055_DRDY5_GYRO _PIN_OFF(GPIO_BMI055_DRDY5_GYRO)
+#define GPIO_DRDY_OFF_BMI055_DRDY6_ACC  _PIN_OFF(GPIO_BMI055_DRDY6_ACC)
+
+
+/* SPI1 off */
+#define GPIO_SPI1_SCK_OFF	_PIN_OFF(GPIO_SPI1_SCK)
+#define GPIO_SPI1_MISO_OFF	_PIN_OFF(GPIO_SPI1_MISO)
+#define GPIO_SPI1_MOSI_OFF	_PIN_OFF(GPIO_SPI1_MOSI)
+
+/* SENSORS are on SPI1
+ * MEMORY is on bus SPI2
+ * MS5611 is on bus SPI4
+ */
+#define PX4_SPI_BUS_SENSORS  1
+#define PX4_SPI_BUS_MEMORY   2
+#define PX4_SPI_BUS_BARO     4
+#define PX4_SPI_BUS_EXTERNAL 6
+
+/* v BEGIN Legacy SPI defines TODO: fix this with enumeration */
+#define PX4_SPI_BUS_RAMTRON  PX4_SPI_BUS_MEMORY
+#define PX4_SPIDEV_BMA 0
+#define PX4_SPIDEV_BMI 0
+/* ^ END Legacy SPI defines TODO: fix this with enumeration */
+
+
+#define PX4_SPIDEV_ICM_20689      PX4_MK_SPI_SEL(PX4_SPI_BUS_SENSORS,0)
+#define PX4_SPIDEV_ICM_20602      PX4_MK_SPI_SEL(PX4_SPI_BUS_SENSORS,1)
+#define PX4_SPIDEV_BMI055_GYRO    PX4_MK_SPI_SEL(PX4_SPI_BUS_SENSORS,2)
+#define PX4_SPIDEV_BMI055_ACCEL   PX4_MK_SPI_SEL(PX4_SPI_BUS_SENSORS,3)
+
+#define PX4_SENSOR_BUS_CS_GPIO    {GPIO_SPI_CS_ICM20689, GPIO_SPI_CS_ICM20602, GPIO_SPI_CS_BMI055_GYR, GPIO_SPI_CS_BMI055_ACC}
+#define PX4_SENSORS_BUS_FIRST_CS  PX4_SPIDEV_ICM_20689
+#define PX4_SENSORS_BUS_LAST_CS   PX4_SPIDEV_BMI055_ACCEL
+
+#define PX4_SPIDEV_MEMORY         PX4_MK_SPI_SEL(PX4_SPI_BUS_MEMORY,0)
+#define PX4_MEMORY_BUS_CS_GPIO    {GPIO_SPI_CS_MEMORY}
+#define PX4_MEMORY_BUS_FIRST_CS   PX4_SPIDEV_MEMORY
+#define PX4_MEMORY_BUS_LAST_CS    PX4_SPIDEV_MEMORY
+
+#define PX4_SPIDEV_BARO           PX4_MK_SPI_SEL(PX4_SPI_BUS_BARO,0)
+#define PX4_BARO_BUS_CS_GPIO      {GPIO_SPI_CS_MS5611}
+#define PX4_BARO_BUS_FIRST_CS     PX4_SPIDEV_BARO
+#define PX4_BARO_BUS_LAST_CS      PX4_SPIDEV_BARO
+
+#define PX4_SPIDEV_EXTERNAL1      PX4_MK_SPI_SEL(PX4_SPI_BUS_EXTERNAL,0)
+#define PX4_SPIDEV_EXTERNAL2      PX4_MK_SPI_SEL(PX4_SPI_BUS_EXTERNAL,1)
+#define PX4_SPIDEV_EXTERNAL3      PX4_MK_SPI_SEL(PX4_SPI_BUS_EXTERNAL,2)
+#define PX4_SPIDEV_EXTERNAL4      PX4_MK_SPI_SEL(PX4_SPI_BUS_EXTERNAL,3)
+#define PX4_SPIDEV_EXTERNAL5      PX4_MK_SPI_SEL(PX4_SPI_BUS_EXTERNAL,4)
+#define PX4_SPIDEV_EXTERNAL6      PX4_MK_SPI_SEL(PX4_SPI_BUS_EXTERNAL,5)
+#define PX4_EXTERNAL_BUS_CS_GPIO  {SPI6_EXTERNAL1_CS1, SPI6_EXTERNAL1_CS2, \
+		SPI6_EXTERNAL1_CS3, \
+		SPI6_EXTERNAL2_CS1, SPI6_EXTERNAL2_CS2, \
+		SPI6_EXTERNAL2_CS3}
+#define PX4_EXTERNAL_BUS_FIRST_CS  PX4_SPIDEV_EXTERNAL1
+#define PX4_EXTERNAL_BUS_LAST_CS   PX4_SPIDEV_EXTERNAL6
+
+
+/* I2C busses */
+#define PX4_I2C_BUS_EXPANSION	1
+#define PX4_I2C_BUS_EXPANSION2	2
+#define PX4_I2C_BUS_EXPANSION3	4
+#define PX4_I2C_BUS_LED			PX4_I2C_BUS_EXPANSION
+
+/* Devices on the external bus.
+ *
+ * Note that these are unshifted addresses.
+ */
+#define PX4_I2C_OBDEV_LED	    0x55
+#define PX4_I2C_OBDEV_HMC5883	0x1e
+#define PX4_I2C_OBDEV_LIS3MDL	0x1e
+
+/*
+ * ADC channels
+ *
+ * These are the channel numbers of the ADCs of the microcontroller that
+ * can be used by the Px4 Firmware in the adc driver
+ */
+#define ADC_CHANNELS (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) | \
+	(1 << 8) | \
+	(1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14)
+
+// ADC defines to be used in sensors.cpp to read from a particular channel
+
+#define ADC_BATTERY_VOLTAGE_CHANNEL     0
+#define ADC_BATTERY_CURRENT_CHANNEL     1
+#define ADC_BATTERY1_VOLTAGE_CHANNEL    2
+#define ADC_BATTERY1_CURRENT_CHANNEL    3
+#define ADC_5V_RAIL_SENSE               4 /* NOT FMUv5 test HW ONLY*/
+#define ADC_RC_RSSI_CHANNEL             8
+#define ADC_INT_1                       10
+#define ADC_INT_2                       11
+#define ADC_INT_3                       12
+#define ADC_INT_4                       13
+#define ADC_INT_5                       14
+
+/* CAN Silence
+ *
+ * Silent mode control
+ */
+
+#define GPIO_CAN1_SILENCE  /* PH2  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTH|GPIO_PIN2)
+#define GPIO_CAN2_SILENCE  /* PH3  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTH|GPIO_PIN3)
+#define GPIO_CAN3_SILENCE  /* PH4  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTH|GPIO_PIN4)
+
+/* HEATER
+ * PWM in future
+ */
+#define GPIO_HEATER        /* PA7  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN7)
+
+/* PWM
+ *
+ * 4  PWM outputs are configured.
+ *
+ * Pins:
+ *
+ * FMU_CH1 : PE14 : TIM1_CH4
+ * FMU_CH2 : PA10 : TIM1_CH3
+ * FMU_CH3 : PE11 : TIM1_CH2
+ * FMU_CH4 : PE9  : TIM1_CH1
+ * FMU_CH5 : PD13 : TIM4_CH2
+ * FMU_CH6 : PD14 : TIM4_CH3
+ *
+ */
+#define GPIO_TIM4_CH3OUT       /* PD14  T4C3  FMU6 */ GPIO_TIM4_CH3OUT_2
+#define GPIO_TIM4_CH2OUT       /* PD13  T4C2  FMU5 */ GPIO_TIM4_CH2OUT_2
+#define GPIO_TIM1_CH1OUT       /* PE9   T1C1  FMU4 */ GPIO_TIM1_CH1OUT_2
+#define GPIO_TIM1_CH2OUT       /* PE11  T1C2  FMU3 */ GPIO_TIM1_CH2OUT_2
+#define GPIO_TIM1_CH3OUT       /* PA10  T1C3  FMU2 */ GPIO_TIM1_CH3OUT_1
+#define GPIO_TIM1_CH4OUT       /* PE14  T1C4  FMU1 */ GPIO_TIM1_CH4OUT_2
+#define DIRECT_PWM_OUTPUT_CHANNELS  6
+
+
+#define GPIO_TIM4_CH3IN       /* PD14  T4C3  FMU6 */ GPIO_TIM4_CH3IN_2
+#define GPIO_TIM4_CH2IN       /* PD13  T4C2  FMU5 */ GPIO_TIM4_CH2IN_2
+#define GPIO_TIM1_CH1IN       /* PE9   T1C1  FMU4 */ GPIO_TIM1_CH1IN_2
+#define GPIO_TIM1_CH2IN       /* PE11  T1C2  FMU3 */ GPIO_TIM1_CH2IN_2
+#define GPIO_TIM1_CH3IN       /* PA10  T1C3  FMU2 */ GPIO_TIM1_CH3IN_1
+#define GPIO_TIM1_CH4IN       /* PE14  T1C4  FMU1 */ GPIO_TIM1_CH4IN_2
+
+#define DIRECT_INPUT_TIMER_CHANNELS  6
+
+/* User GPIOs
+ *
+ * GPIO0-5 are the PWM servo outputs.
+ */
+
+#define _MK_GPIO_INPUT(def) (((def) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | (GPIO_INPUT|GPIO_PULLUP))
+
+#define GPIO_GPIO5_INPUT        /* PD14  T4C3  FMU6 */ _MK_GPIO_INPUT(GPIO_TIM4_CH3IN)
+#define GPIO_GPIO4_INPUT        /* PD13  T4C2  FMU5 */ _MK_GPIO_INPUT(GPIO_TIM4_CH2IN)
+#define GPIO_GPIO3_INPUT        /* PE9   T1C1  FMU4 */ _MK_GPIO_INPUT(GPIO_TIM1_CH1IN)
+#define GPIO_GPIO2_INPUT        /* PE11  T1C2  FMU3 */ _MK_GPIO_INPUT(GPIO_TIM1_CH2IN)
+#define GPIO_GPIO1_INPUT        /* PA10  T1C3  FMU2 */ _MK_GPIO_INPUT(GPIO_TIM1_CH3IN)
+#define GPIO_GPIO0_INPUT        /* PE14  T1C4  FMU1 */ _MK_GPIO_INPUT(GPIO_TIM1_CH4IN)
+
+#define _MK_GPIO_OUTPUT(def) (((def) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR))
+
+#define GPIO_GPIO5_OUTPUT        /* PD14  T4C3  FMU6 */ _MK_GPIO_OUTPUT(GPIO_TIM4_CH3OUT)
+#define GPIO_GPIO4_OUTPUT        /* PD13  T4C2  FMU5 */ _MK_GPIO_OUTPUT(GPIO_TIM4_CH2OUT)
+#define GPIO_GPIO3_OUTPUT        /* PE9   T1C1  FMU4 */ _MK_GPIO_OUTPUT(GPIO_TIM1_CH1OUT)
+#define GPIO_GPIO2_OUTPUT        /* PE11  T1C2  FMU3 */ _MK_GPIO_OUTPUT(GPIO_TIM1_CH2OUT)
+#define GPIO_GPIO1_OUTPUT        /* PA10  T1C3  FMU2 */ _MK_GPIO_OUTPUT(GPIO_TIM1_CH3OUT)
+#define GPIO_GPIO0_OUTPUT        /* PE14  T1C4  FMU1 */ _MK_GPIO_OUTPUT(GPIO_TIM1_CH4OUT)
+
+
+/* Power supply control and monitoring GPIOs */
+
+#define GPIO_POWER_IN_A           /* PG1  */ (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTG|GPIO_PIN1)
+#define GPIO_POWER_IN_B           /* PG2  */ (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTG|GPIO_PIN2)
+#define GPIO_POWER_IN_C           /* PG3  */ (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTG|GPIO_PIN3)
+
+#define GPIO_VDD_BRICK_VALID      /* PB10 */ (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_VDD_3V3_SENSORS_EN   /* PE3  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN3)
+#define GPIO_SPEKTRUM_POWER_EN    /* PE4  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN4)
+#define GPIO_PERIPH_5V_EN         /* PG4  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTG|GPIO_PIN4)
+#define GPIO_VDD_5V_RC_EN         /* PG5  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTG|GPIO_PIN5)
+#define GPIO_VDD_5V_WIFI_EN       /* PG6  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTG|GPIO_PIN5)
+#define GPIO_VDD_3V3V_SD_CARD_EN  /* PG7  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTG|GPIO_PIN7)
+
+#define GPIO_VDD_5V_PERIPH_OC     /* PE15 */ (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN15)
+
+/* Tone alarm output */
+#define TONE_ALARM_TIMER		12	/* timer 12 */
+#define TONE_ALARM_CHANNEL      /* PH6 TIM12_CH1 */ 1	/* channel 1 */
+#define GPIO_TONE_ALARM_IDLE    /* PH6 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTH|GPIO_PIN6)
+#define GPIO_TONE_ALARM         /* PH6 */ (GPIO_ALT|GPIO_AF1|GPIO_SPEED_2MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN6)
+
+/* USB OTG FS
+ *
+ * PA9  OTG_FS_VBUS VBUS sensing
+ */
+#define GPIO_OTGFS_VBUS         /* PA9 */ (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN9)
+
+/* High-resolution timer */
+#define HRT_TIMER		    8	/* use timer8 for the HRT */
+#define HRT_TIMER_CHANNEL   3	/* use capture/compare channel 3 */
+
+#define HRT_PPM_CHANNEL         /* T8C1 */  1	/* use capture/compare channel 1 */
+#define GPIO_PPM_IN             /* PI5 T8C1 */ GPIO_TIM8_CH1IN_2
+
+#define RC_UXART_BASE        STM32_USART6_BASE /* NOT FMUv5 test HW ONLY*/
+#define RC_SERIAL_PORT       "/dev/ttyS5"      /* NOT FMUv5 test HW ONLY*/
+
+/* PWM input driver. Use FMU AUX5 pins attached to timer4 channel 2 */
+#define PWMIN_TIMER             4
+#define PWMIN_TIMER_CHANNEL     /* T4C2 */ 2
+#define GPIO_PWM_IN             /* PD13 */ GPIO_TIM4_CH2IN
+
+#define GPIO_RSSI_IN            /* PB0  */ (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN0)
+
+#define GPIO_LED_SAFETY         /* PE12 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN12)
+#define GPIO_BTN_SAFETY         /* PE10 */ (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN10)
+
+#define INVERT_RC_INPUT(_s)		board_rc_input(_s);
+
+
+/* Power switch controls ******************************************************/
+
+#define POWER_SPEKTRUM(_s)      px4_arch_gpiowrite(GPIO_SPEKTRUM_POWER_EN, (1-_s))
+#define SPEKTRUM_RX_AS_UART()   px4_arch_configgpio(GPIO_USART6_RX) /* NOT FMUv5 test HW ONLY*/
+
+// FMUv5 has a separate GPIO for serial RC output
+#define GPIO_RC_OUT            /* PG9 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTG|GPIO_PIN9)
+#define SPEKTRUM_RX_AS_GPIO()   px4_arch_configgpio(GPIO_RC_OUT)
+#define SPEKTRUM_RX_HIGH(_s)    px4_arch_gpiowrite(GPIO_RC_OUT, (_s))
+
+#define SDIO_SLOTNO             0  /* Only one slot */
+#define SDIO_MINOR              0
+
+/* SD card bringup does not work if performed on the IDLE thread because it
+ * will cause waiting.  Use either:
+ *
+ *  CONFIG_LIB_BOARDCTL=y, OR
+ *  CONFIG_BOARD_INITIALIZE=y && CONFIG_BOARD_INITTHREAD=y
+ */
+
+#if defined(CONFIG_BOARD_INITIALIZE) && !defined(CONFIG_LIB_BOARDCTL) && \
+   !defined(CONFIG_BOARD_INITTHREAD)
+#  warning SDIO initialization cannot be perfomed on the IDLE thread
+#endif
+
+#define	BOARD_NAME "PX4FMU_V5"
+
+/* By Providing BOARD_ADC_USB_CONNECTED (using the px4_arch abstraction)
+ * this board support the ADC system_power interface, and therefore
+ * provides the true logic GPIO BOARD_ADC_xxxx macros.
+ */
+#define BOARD_ADC_USB_CONNECTED (px4_arch_gpioread(GPIO_OTGFS_VBUS))
+#define BOARD_ADC_BRICK_VALID   (px4_arch_gpioread(GPIO_VDD_BRICK_VALID))
+#define BOARD_ADC_SERVO_VALID   (1)
+#define BOARD_ADC_PERIPH_5V_OC  (px4_arch_gpioread(GPIO_VDD_5V_PERIPH_OC))
+#define BOARD_ADC_HIPOWER_5V_OC (0)
+
+#define BOARD_HAS_PWM	DIRECT_PWM_OUTPUT_CHANNELS
+
+#define BOARD_FMU_GPIO_TAB { \
+		{GPIO_GPIO0_INPUT,       GPIO_GPIO0_OUTPUT,       0}, \
+		{GPIO_GPIO1_INPUT,       GPIO_GPIO1_OUTPUT,       0}, \
+		{GPIO_GPIO2_INPUT,       GPIO_GPIO2_OUTPUT,       0}, \
+		{GPIO_GPIO3_INPUT,       GPIO_GPIO3_OUTPUT,       0}, \
+		{GPIO_GPIO4_INPUT,       GPIO_GPIO4_OUTPUT,       0}, \
+		{GPIO_GPIO5_INPUT,       GPIO_GPIO5_OUTPUT,       0}, \
+		{0,                      GPIO_VDD_3V3_SENSORS_EN, 0}, \
+		{GPIO_VDD_BRICK_VALID,   0,                       0}, }
+
+/* This board provides a DMA pool and APIs */
+
+#define BOARD_DMA_ALLOC_POOL_SIZE 5120
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public data
+ ****************************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_sdio_initialize
+ *
+ * Description:
+ *   Initialize SDIO-based MMC/SD card support
+ *
+ ****************************************************************************/
+
+int stm32_sdio_initialize(void);
+
+/****************************************************************************************************
+ * Name: stm32_spiinitialize
+ *
+ * Description:
+ *   Called to configure SPI chip select GPIO pins for the PX4FMU board.
+ *
+ ****************************************************************************************************/
+
+extern void stm32_spiinitialize(void);
+
+/************************************************************************************
+ * Name: stm32_spi_bus_initialize
+ *
+ * Description:
+ *   Called to configure SPI Buses.
+ *
+ ************************************************************************************/
+
+extern int stm32_spi_bus_initialize(void);
+
+void board_spi_reset(int ms);
+
+extern void stm32_usbinitialize(void);
+
+extern void board_peripheral_reset(int ms);
+
+
+/****************************************************************************
+ * Name: nsh_archinitialize
+ *
+ * Description:
+ *   Perform architecture specific initialization for NSH.
+ *
+ *   CONFIG_NSH_ARCHINIT=y :
+ *     Called from the NSH library
+ *
+ *   CONFIG_BOARD_INITIALIZE=y, CONFIG_NSH_LIBRARY=y, &&
+ *   CONFIG_NSH_ARCHINIT=n :
+ *     Called from board_initialize().
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_NSH_LIBRARY
+int nsh_archinitialize(void);
+#endif
+
+#include "../common/board_common.h"
+
+#endif /* __ASSEMBLY__ */
+
+__END_DECLS
@@ -0,0 +1,129 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file px4fmu_can.c
+ *
+ * Board-specific CAN functions.
+ */
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <px4_config.h>
+
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/can.h>
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "up_arch.h"
+
+#include "chip.h"
+#include "stm32_can.h"
+#include "board_config.h"
+
+#ifdef CONFIG_CAN
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* Configuration ********************************************************************/
+
+#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2)
+#  warning "Both CAN1 and CAN2 are enabled.  Assuming only CAN1."
+#  undef CONFIG_STM32_CAN2
+#endif
+
+#ifdef CONFIG_STM32_CAN1
+#  define CAN_PORT 1
+#else
+#  define CAN_PORT 2
+#endif
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: can_devinit
+ *
+ * Description:
+ *   All STM32 architectures must provide the following interface to work with
+ *   examples/can.
+ *
+ ************************************************************************************/
+
+int can_devinit(void)
+{
+	static bool initialized = false;
+	struct can_dev_s *can;
+	int ret;
+
+	/* Check if we have already initialized */
+
+	if (!initialized) {
+		/* Call stm32_caninitialize() to get an instance of the CAN interface */
+
+		can = stm32_caninitialize(CAN_PORT);
+
+		if (can == NULL) {
+			canerr("ERROR:  Failed to get CAN interface\n");
+			return -ENODEV;
+		}
+
+		/* Register the CAN driver at "/dev/can0" */
+
+		ret = can_register("/dev/can0", can);
+
+		if (ret < 0) {
+			canerr("ERROR: can_register failed: %d\n", ret);
+			return ret;
+		}
+
+		/* Now we are initialized */
+
+		initialized = true;
+	}
+
+	return OK;
+}
+
+#endif
@@ -0,0 +1,654 @@
+/****************************************************************************
+ *
+ *   Copyright (c) 2012-2016 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file px4fmu_init.c
+ *
+ * PX4FMU-specific early startup code.  This file implements the
+ * nsh_archinitialize() function that is called early by nsh during startup.
+ *
+ * Code here is run before the rcS script is invoked; it should start required
+ * subsystems and perform board-specific initialisation.
+ */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <px4_config.h>
+
+#include <stdbool.h>
+#include <stdio.h>
+#include <string.h>
+#include <debug.h>
+#include <errno.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <nuttx/spi/spi.h>
+#include <nuttx/i2c/i2c_master.h>
+#include <nuttx/sdio.h>
+#include <nuttx/mmcsd.h>
+#include <nuttx/analog/adc.h>
+#include <nuttx/mm/gran.h>
+
+#include <chip.h>
+#include "board_config.h"
+#include <stm32_uart.h>
+
+#include <arch/board/board.h>
+
+#include <drivers/drv_hrt.h>
+#include <drivers/drv_led.h>
+
+#include <systemlib/px4_macros.h>
+#include <systemlib/cpuload.h>
+#include <systemlib/perf_counter.h>
+#include <systemlib/err.h>
+
+#include <systemlib/hardfault_log.h>
+
+#include <systemlib/systemlib.h>
+
+#include "up_internal.h"
+/****************************************************************************
+ * Pre-Processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+/* Debug ********************************************************************/
+
+#ifdef CONFIG_CPP_HAVE_VARARGS
+#  ifdef CONFIG_DEBUG
+#    define message(...) syslog(__VA_ARGS__)
+#  else
+#    define message(...) printf(__VA_ARGS__)
+#  endif
+#else
+#  ifdef CONFIG_DEBUG
+#    define message syslog
+#  else
+#    define message printf
+#  endif
+#endif
+
+/*
+ * Ideally we'd be able to get these from up_internal.h,
+ * but since we want to be able to disable the NuttX use
+ * of leds for system indication at will and there is no
+ * separate switch, we need to build independent of the
+ * CONFIG_ARCH_LEDS configuration switch.
+ */
+__BEGIN_DECLS
+extern void led_init(void);
+extern void led_on(int led);
+extern void led_off(int led);
+__END_DECLS
+
+/****************************************************************************
+ * Protected Functions
+ ****************************************************************************/
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+/************************************************************************************
+ * Name: board_rc_input
+ *
+ * Description:
+ *   All boards my optionally provide this API to invert the Serial RC input.
+ *   This is needed on SoCs that support the notion RXINV or TXINV as apposed to
+ *   and external XOR controlled by a GPIO
+ *
+ ************************************************************************************/
+
+__EXPORT void board_rc_input(bool invert_on)
+{
+
+	irqstate_t irqstate = px4_enter_critical_section();
+
+	uint32_t cr1 =  getreg32(STM32_USART_CR1_OFFSET + RC_UXART_BASE);
+	uint32_t cr2 =  getreg32(STM32_USART_CR2_OFFSET + RC_UXART_BASE);
+	uint32_t regval = cr1;
+
+	/* {R|T}XINV bit fields can only be written when the USART is disabled (UE=0). */
+
+	regval &= ~USART_CR1_UE;
+
+	putreg32(regval, STM32_USART_CR1_OFFSET + RC_UXART_BASE);
+
+	if (invert_on) {
+		cr2 |= (USART_CR2_RXINV | USART_CR2_TXINV);
+
+	} else {
+		cr2 &= ~(USART_CR2_RXINV | USART_CR2_TXINV);
+	}
+
+	putreg32(cr2, STM32_USART_CR1_OFFSET + RC_UXART_BASE);
+	putreg32(cr1, STM32_USART_CR1_OFFSET + RC_UXART_BASE);
+
+	leave_critical_section(irqstate);
+}
+
+/************************************************************************************
+ * Name: board_peripheral_reset
+ *
+ * Description:
+ *
+ ************************************************************************************/
+__EXPORT void board_peripheral_reset(int ms)
+{
+	/* set the peripheral rails off */
+
+	stm32_gpiowrite(GPIO_PERIPH_5V_EN, 0);
+	stm32_gpiowrite(GPIO_VDD_3V3_SENSORS_EN, 0);
+
+	bool last = stm32_gpioread(GPIO_SPEKTRUM_POWER_EN);
+	/* Keep Spektum on to discharge rail*/
+	stm32_gpiowrite(GPIO_SPEKTRUM_POWER_EN, 1);
+
+	/* wait for the peripheral rail to reach GND */
+	usleep(ms * 1000);
+	warnx("reset done, %d ms", ms);
+
+	/* re-enable power */
+
+	/* switch the peripheral rail back on */
+	stm32_gpiowrite(GPIO_SPEKTRUM_POWER_EN, last);
+	stm32_gpiowrite(GPIO_VDD_3V3_SENSORS_EN, 1);
+	stm32_gpiowrite(GPIO_PERIPH_5V_EN, 1);
+
+}
+
+/************************************************************************************
+ * Name: stm32_boardinitialize
+ *
+ * Description:
+ *   All STM32 architectures must provide the following entry point.  This entry point
+ *   is called early in the initialization -- after all memory has been configured
+ *   and mapped but before any devices have been initialized.
+ *
+ ************************************************************************************/
+
+__EXPORT void
+stm32_boardinitialize(void)
+{
+	/* configure LEDs */
+	board_autoled_initialize();
+
+	/* configure the GPIO pins to outputs and keep them low */
+	stm32_configgpio(GPIO_GPIO0_OUTPUT);
+	stm32_configgpio(GPIO_GPIO1_OUTPUT);
+	stm32_configgpio(GPIO_GPIO2_OUTPUT);
+	stm32_configgpio(GPIO_GPIO3_OUTPUT);
+	stm32_configgpio(GPIO_GPIO4_OUTPUT);
+	stm32_configgpio(GPIO_GPIO5_OUTPUT);
+
+	/* configure ADC pins */
+	stm32_configgpio(GPIO_ADC1_IN0);	/* ADC_BATTERY_VOLTAGE_CHANNEL  */
+	stm32_configgpio(GPIO_ADC1_IN1);	/* ADC_BATTERY_CURRENT_CHANNEL */
+	stm32_configgpio(GPIO_ADC1_IN2);	/* ADC_BATTERY1_VOLTAGE_CHANNEL */
+	stm32_configgpio(GPIO_ADC1_IN3);	/* ADC_BATTERY1_CURRENT_CHANNEL */
+	stm32_configgpio(GPIO_ADC1_IN4);	/* ADC_5V_RAIL_SENSE */
+	stm32_configgpio(GPIO_ADC1_IN8);	/* ADC_RC_RSSI_CHANNEL */
+	stm32_configgpio(GPIO_ADC1_IN10);	/* ADC_INT_1 */
+	stm32_configgpio(GPIO_ADC1_IN11);	/* ADC_INT_2 */
+	stm32_configgpio(GPIO_ADC1_IN12);	/* ADC_INT_3 */
+	stm32_configgpio(GPIO_ADC1_IN13);	/* ADC_INT_4 */
+	stm32_configgpio(GPIO_ADC1_IN14);	/* ADC_INT_5 */
+
+	/* Configure the HEATER off */
+
+	stm32_configgpio(GPIO_HEATER);
+
+
+	/* Configure the CAN Silent Control pins and keep them low */
+
+	stm32_configgpio(GPIO_CAN1_SILENCE);
+	stm32_configgpio(GPIO_CAN2_SILENCE);
+	stm32_configgpio(GPIO_CAN3_SILENCE);
+
+	/* configure power supply control/sense pins */
+
+	stm32_configgpio(GPIO_POWER_IN_A);
+	stm32_configgpio(GPIO_POWER_IN_B);
+	stm32_configgpio(GPIO_POWER_IN_C);
+
+	stm32_configgpio(GPIO_VDD_BRICK_VALID);
+	stm32_configgpio(GPIO_PERIPH_5V_EN);
+	stm32_configgpio(GPIO_VDD_3V3_SENSORS_EN);
+	stm32_configgpio(GPIO_VDD_3V3V_SD_CARD_EN);
+	stm32_configgpio(GPIO_VDD_5V_RC_EN);
+	stm32_configgpio(GPIO_VDD_5V_WIFI_EN);
+	stm32_configgpio(GPIO_SPEKTRUM_POWER_EN);
+
+	stm32_configgpio(GPIO_LED_SAFETY);
+	stm32_configgpio(GPIO_BTN_SAFETY);
+
+#ifdef GPIO_RC_OUT
+	stm32_configgpio(GPIO_RC_OUT);      /* Serial RC output pin */
+#endif
+
+	/* configure SPI interfaces */
+	stm32_spiinitialize();
+
+}
+
+/****************************************************************************
+ * Name: board_app_initialize
+ *
+ * Description:
+ *   Perform application specific initialization.  This function is never
+ *   called directly from application code, but only indirectly via the
+ *   (non-standard) boardctl() interface using the command BOARDIOC_INIT.
+ *
+ * Input Parameters:
+ *   arg - The boardctl() argument is passed to the board_app_initialize()
+ *         implementation without modification.  The argument has no
+ *         meaning to NuttX; the meaning of the argument is a contract
+ *         between the board-specific initalization logic and the the
+ *         matching application logic.  The value cold be such things as a
+ *         mode enumeration value, a set of DIP switch switch settings, a
+ *         pointer to configuration data read from a file or serial FLASH,
+ *         or whatever you would like to do with it.  Every implementation
+ *         should accept zero/NULL as a default configuration.
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success; a negated errno value is returned on
+ *   any failure to indicate the nature of the failure.
+ *
+ ****************************************************************************/
+
+
+__EXPORT int board_app_initialize(uintptr_t arg)
+{
+
+#if defined(CONFIG_HAVE_CXX) && defined(CONFIG_HAVE_CXXINITIALIZE)
+
+	/* run C++ ctors before we go any further */
+
+	up_cxxinitialize();
+
+#	if defined(CONFIG_EXAMPLES_NSH_CXXINITIALIZE)
+#  		error CONFIG_EXAMPLES_NSH_CXXINITIALIZE Must not be defined! Use CONFIG_HAVE_CXX and CONFIG_HAVE_CXXINITIALIZE.
+#	endif
+
+#else
+#  error platform is dependent on c++ both CONFIG_HAVE_CXX and CONFIG_HAVE_CXXINITIALIZE must be defined.
+#endif
+
+	/* configure the high-resolution time/callout interface */
+	hrt_init();
+
+	/* configure the DMA allocator */
+
+	if (board_dma_alloc_init() < 0) {
+		message("DMA alloc FAILED");
+	}
+
+	/* configure CPU load estimation */
+#ifdef CONFIG_SCHED_INSTRUMENTATION
+	cpuload_initialize_once();
+#endif
+
+	/* set up the serial DMA polling */
+	static struct hrt_call serial_dma_call;
+	struct timespec ts;
+
+	/*
+	 * Poll at 1ms intervals for received bytes that have not triggered
+	 * a DMA event.
+	 */
+	ts.tv_sec = 0;
+	ts.tv_nsec = 1000000;
+
+	hrt_call_every(&serial_dma_call,
+		       ts_to_abstime(&ts),
+		       ts_to_abstime(&ts),
+		       (hrt_callout)stm32_serial_dma_poll,
+		       NULL);
+
+#if defined(CONFIG_STM32_BBSRAM)
+
+	/* NB. the use of the console requires the hrt running
+	 * to poll the DMA
+	 */
+
+	/* Using Battery Backed Up SRAM */
+
+	int filesizes[CONFIG_STM32_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES;
+
+	stm32_bbsraminitialize(BBSRAM_PATH, filesizes);
+
+#if defined(CONFIG_STM32_SAVE_CRASHDUMP)
+
+	/* Panic Logging in Battery Backed Up Files */
+
+	/*
+	 * In an ideal world, if a fault happens in flight the
+	 * system save it to BBSRAM will then reboot. Upon
+	 * rebooting, the system will log the fault to disk, recover
+	 * the flight state and continue to fly.  But if there is
+	 * a fault on the bench or in the air that prohibit the recovery
+	 * or committing the log to disk, the things are too broken to
+	 * fly. So the question is:
+	 *
+	 * Did we have a hard fault and not make it far enough
+	 * through the boot sequence to commit the fault data to
+	 * the SD card?
+	 */
+
+	/* Do we have an uncommitted hard fault in BBSRAM?
+	 *  - this will be reset after a successful commit to SD
+	 */
+	int hadCrash = hardfault_check_status("boot");
+
+	if (hadCrash == OK) {
+
+		message("[boot] There is a hard fault logged. Hold down the SPACE BAR," \
+			" while booting to halt the system!\n");
+
+		/* Yes. So add one to the boot count - this will be reset after a successful
+		 * commit to SD
+		 */
+
+		int reboots = hardfault_increment_reboot("boot", false);
+
+		/* Also end the misery for a user that holds for a key down on the console */
+
+		int bytesWaiting;
+		ioctl(fileno(stdin), FIONREAD, (unsigned long)((uintptr_t) &bytesWaiting));
+
+		if (reboots > 2 || bytesWaiting != 0) {
+
+			/* Since we can not commit the fault dump to disk. Display it
+			 * to the console.
+			 */
+
+			hardfault_write("boot", fileno(stdout), HARDFAULT_DISPLAY_FORMAT, false);
+
+			message("[boot] There were %d reboots with Hard fault that were not committed to disk - System halted %s\n",
+				reboots,
+				(bytesWaiting == 0 ? "" : " Due to Key Press\n"));
+
+
+			/* For those of you with a debugger set a break point on up_assert and
+			 * then set dbgContinue = 1 and go.
+			 */
+
+			/* Clear any key press that got us here */
+
+			static volatile bool dbgContinue = false;
+			int c = '>';
+
+			while (!dbgContinue) {
+
+				switch (c) {
+
+				case EOF:
+
+
+				case '\n':
+				case '\r':
+				case ' ':
+					continue;
+
+				default:
+
+					putchar(c);
+					putchar('\n');
+
+					switch (c) {
+
+					case 'D':
+					case 'd':
+						hardfault_write("boot", fileno(stdout), HARDFAULT_DISPLAY_FORMAT, false);
+						break;
+
+					case 'C':
+					case 'c':
+						hardfault_rearm("boot");
+						hardfault_increment_reboot("boot", true);
+						break;
+
+					case 'B':
+					case 'b':
+						dbgContinue = true;
+						break;
+
+					default:
+						break;
+					} // Inner Switch
+
+					message("\nEnter B - Continue booting\n" \
+						"Enter C - Clear the fault log\n" \
+						"Enter D - Dump fault log\n\n?>");
+					fflush(stdout);
+
+					if (!dbgContinue) {
+						c = getchar();
+					}
+
+					break;
+
+				} // outer switch
+			} // for
+
+		} // inner if
+	} // outer if
+
+#endif // CONFIG_STM32_SAVE_CRASHDUMP
+#endif // CONFIG_STM32_BBSRAM
+
+	/* initial LED state */
+	drv_led_start();
+	led_off(LED_RED);
+	led_off(LED_GREEN);
+	led_off(LED_BLUE);
+
+#ifdef CONFIG_SPI
+	int ret = stm32_spi_bus_initialize();
+
+	if (ret != OK) {
+		board_autoled_on(LED_RED);
+		return ret;
+	}
+
+#endif
+
+#ifdef CONFIG_MMCSD
+	ret = stm32_sdio_initialize();
+
+	if (ret != OK) {
+		board_autoled_on(LED_RED);
+		return ret;
+	}
+
+#endif
+
+	return OK;
+}
+
+static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size)
+{
+	while (size--) {
+		*dest++ = *src--;
+	}
+}
+
+__EXPORT void board_crashdump(uintptr_t currentsp, FAR void *tcb, FAR const uint8_t *filename, int lineno)
+{
+	/* We need a chunk of ram to save the complete context in.
+	 * Since we are going to reboot we will use &_sdata
+	 * which is the lowest memory and the amount we will save
+	 * _should be_ below any resources we need herein.
+	 * Unfortunately this is hard to test. See dead below
+	 */
+
+	fullcontext_s *pdump = (fullcontext_s *)&_sdata;
+
+	(void)enter_critical_section();
+
+	struct tcb_s *rtcb = (struct tcb_s *)tcb;
+
+	/* Zero out everything */
+
+	memset(pdump, 0, sizeof(fullcontext_s));
+
+	/* Save Info */
+
+	pdump->info.lineno = lineno;
+
+	if (filename) {
+
+		int offset = 0;
+		unsigned int len = strlen((char *)filename) + 1;
+
+		if (len > sizeof(pdump->info.filename)) {
+			offset = len - sizeof(pdump->info.filename) ;
+		}
+
+		strncpy(pdump->info.filename, (char *)&filename[offset], sizeof(pdump->info.filename));
+	}
+
+	/* Save the value of the pointer for current_regs as debugging info.
+	 * It should be NULL in case of an ASSERT and will aid in cross
+	 * checking the validity of system memory at the time of the
+	 * fault.
+	 */
+
+	pdump->info.current_regs = (uintptr_t) CURRENT_REGS;
+
+	/* Save Context */
+
+
+#if CONFIG_TASK_NAME_SIZE > 0
+	strncpy(pdump->info.name, rtcb->name, CONFIG_TASK_NAME_SIZE);
+#endif
+
+	pdump->info.pid = rtcb->pid;
+
+
+	/* If  current_regs is not NULL then we are in an interrupt context
+	 * and the user context is in current_regs else we are running in
+	 * the users context
+	 */
+
+	if (CURRENT_REGS) {
+		pdump->info.stacks.interrupt.sp = currentsp;
+
+		pdump->info.flags |= (eRegsPresent | eUserStackPresent | eIntStackPresent);
+		memcpy(pdump->info.regs, (void *)CURRENT_REGS, sizeof(pdump->info.regs));
+		pdump->info.stacks.user.sp = pdump->info.regs[REG_R13];
+
+	} else {
+
+		/* users context */
+		pdump->info.flags |= eUserStackPresent;
+
+		pdump->info.stacks.user.sp = currentsp;
+	}
+
+	if (pdump->info.pid == 0) {
+
+		pdump->info.stacks.user.top = g_idle_topstack - 4;
+		pdump->info.stacks.user.size = CONFIG_IDLETHREAD_STACKSIZE;
+
+	} else {
+		pdump->info.stacks.user.top = (uint32_t) rtcb->adj_stack_ptr;
+		pdump->info.stacks.user.size = (uint32_t) rtcb->adj_stack_size;;
+	}
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+
+	/* Get the limits on the interrupt stack memory */
+
+	pdump->info.stacks.interrupt.top = (uint32_t)&g_intstackbase;
+	pdump->info.stacks.interrupt.size  = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
+
+	/* If In interrupt Context save the interrupt stack data centered
+	 * about the interrupt stack pointer
+	 */
+
+	if ((pdump->info.flags & eIntStackPresent) != 0) {
+		stack_word_t *ps = (stack_word_t *) pdump->info.stacks.interrupt.sp;
+		copy_reverse(pdump->istack, &ps[arraySize(pdump->istack) / 2], arraySize(pdump->istack));
+	}
+
+	/* Is it Invalid? */
+
+	if (!(pdump->info.stacks.interrupt.sp <= pdump->info.stacks.interrupt.top &&
+	      pdump->info.stacks.interrupt.sp > pdump->info.stacks.interrupt.top - pdump->info.stacks.interrupt.size)) {
+		pdump->info.flags |= eInvalidIntStackPrt;
+	}
+
+#endif
+
+	/* If In interrupt context or User save the user stack data centered
+	 * about the user stack pointer
+	 */
+	if ((pdump->info.flags & eUserStackPresent) != 0) {
+		stack_word_t *ps = (stack_word_t *) pdump->info.stacks.user.sp;
+		copy_reverse(pdump->ustack, &ps[arraySize(pdump->ustack) / 2], arraySize(pdump->ustack));
+	}
+
+	/* Is it Invalid? */
+
+	if (!(pdump->info.stacks.user.sp <= pdump->info.stacks.user.top &&
+	      pdump->info.stacks.user.sp > pdump->info.stacks.user.top - pdump->info.stacks.user.size)) {
+		pdump->info.flags |= eInvalidUserStackPtr;
+	}
+
+	int rv = stm32_bbsram_savepanic(HARDFAULT_FILENO, (uint8_t *)pdump, sizeof(fullcontext_s));
+
+	/* Test if memory got wiped because of using _sdata */
+
+	if (rv == -ENXIO) {
+		char *dead = "Memory wiped - dump not saved!";
+
+		while (*dead) {
+			up_lowputc(*dead++);
+		}
+
+	} else if (rv == -ENOSPC) {
+
+		/* hard fault again */
+
+		up_lowputc('!');
+	}
+
+
+#if defined(CONFIG_BOARD_RESET_ON_CRASH)
+	px4_systemreset(false);
+#endif
+}
@@ -0,0 +1,229 @@
+/****************************************************************************
+ *
+ *   Copyright (c) 2013 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file px4fmu2_led.c
+ *
+ * PX4FMU LED backend.
+ */
+
+#include <px4_config.h>
+
+#include <stdbool.h>
+
+#include "chip.h"
+#include "stm32_gpio.h"
+#include "board_config.h"
+
+#include <nuttx/board.h>
+#include <arch/board/board.h>
+
+/*
+ * Ideally we'd be able to get these from up_internal.h,
+ * but since we want to be able to disable the NuttX use
+ * of leds for system indication at will and there is no
+ * separate switch, we need to build independent of the
+ * CONFIG_ARCH_LEDS configuration switch.
+ */
+__BEGIN_DECLS
+extern void led_init(void);
+extern void led_on(int led);
+extern void led_off(int led);
+extern void led_toggle(int led);
+__END_DECLS
+
+#ifdef CONFIG_ARCH_LEDS
+static bool nuttx_owns_leds = true;
+//                                B  R  S  G
+//                                0  1  2  3
+static const uint8_t xlatpx4[] = {1, 2, 4, 0};
+#  define xlat(p) xlatpx4[(p)]
+static uint32_t g_ledmap[] = {
+	GPIO_LED_GREEN,   // Indexed by BOARD_LED_GREEN
+	GPIO_LED_BLUE,    // Indexed by BOARD_LED_BLUE
+	GPIO_LED_RED,     // Indexed by BOARD_LED_RED
+	GPIO_LED_SAFETY,  // Indexed by LED_SAFETY by xlatpx4
+};
+
+#else
+
+#  define xlat(p)
+static uint32_t g_ledmap[] = {
+	GPIO_LED_BLUE,    // Indexed by LED_BLUE
+	GPIO_LED_RED,     // Indexed by LED_RED, LED_AMBER
+	GPIO_LED_SAFETY,  // Indexed by LED_SAFETY
+	GPIO_LED_GREEN,   // Indexed by LED_GREEN
+};
+
+#endif
+
+__EXPORT void led_init(void)
+{
+	/* Configure LED GPIOs for output */
+	for (size_t l = 0; l < (sizeof(g_ledmap) / sizeof(g_ledmap[0])); l++) {
+		stm32_configgpio(g_ledmap[l]);
+	}
+}
+
+static void phy_set_led(int led, bool state)
+{
+	/* Drive High to switch on */
+
+	stm32_gpiowrite(g_ledmap[led], state);
+}
+
+static bool phy_get_led(int led)
+{
+
+	return stm32_gpioread(g_ledmap[led]);
+}
+
+__EXPORT void led_on(int led)
+{
+	phy_set_led(xlat(led), true);
+}
+
+__EXPORT void led_off(int led)
+{
+	phy_set_led(xlat(led), false);
+}
+
+__EXPORT void led_toggle(int led)
+{
+
+	phy_set_led(xlat(led), !phy_get_led(xlat(led)));
+}
+
+#ifdef CONFIG_ARCH_LEDS
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_autoled_initialize
+ ****************************************************************************/
+
+void board_autoled_initialize(void)
+{
+	led_init();
+}
+
+/****************************************************************************
+ * Name: board_autoled_on
+ ****************************************************************************/
+
+void board_autoled_on(int led)
+{
+	if (!nuttx_owns_leds) {
+		return;
+	}
+
+	switch (led) {
+	default:
+		break;
+
+	case LED_HEAPALLOCATE:
+		phy_set_led(BOARD_LED_BLUE, true);
+		break;
+
+	case LED_IRQSENABLED:
+		phy_set_led(BOARD_LED_BLUE, false);
+		phy_set_led(BOARD_LED_GREEN, true);
+		break;
+
+	case LED_STACKCREATED:
+		phy_set_led(BOARD_LED_GREEN, true);
+		phy_set_led(BOARD_LED_BLUE, true);
+		break;
+
+	case LED_INIRQ:
+		phy_set_led(BOARD_LED_BLUE, true);
+		break;
+
+	case LED_SIGNAL:
+		phy_set_led(BOARD_LED_GREEN, true);
+		break;
+
+	case LED_ASSERTION:
+		phy_set_led(BOARD_LED_RED, true);
+		phy_set_led(BOARD_LED_BLUE, true);
+		break;
+
+	case LED_PANIC:
+		phy_set_led(BOARD_LED_RED, true);
+		break;
+
+	case LED_IDLE : /* IDLE */
+		phy_set_led(BOARD_LED_RED, true);
+		break;
+	}
+}
+
+/****************************************************************************
+ * Name: board_autoled_off
+ ****************************************************************************/
+
+void board_autoled_off(int led)
+{
+	if (!nuttx_owns_leds) {
+		return;
+	}
+
+	switch (led) {
+	default:
+		break;
+
+	case LED_SIGNAL:
+		phy_set_led(BOARD_LED_GREEN, false);
+		break;
+
+	case LED_INIRQ:
+		phy_set_led(BOARD_LED_BLUE, false);
+		break;
+
+	case LED_ASSERTION:
+		phy_set_led(BOARD_LED_RED, false);
+		phy_set_led(BOARD_LED_BLUE, false);
+		break;
+
+	case LED_PANIC:
+		phy_set_led(BOARD_LED_RED, false);
+		break;
+
+	case LED_IDLE : /* IDLE */
+		phy_set_led(BOARD_LED_RED, false);
+		break;
+	}
+}
+
+#endif /* CONFIG_ARCH_LEDS */
@@ -0,0 +1,193 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <px4_config.h>
+
+#include <stdbool.h>
+#include <stdio.h>
+#include <debug.h>
+#include <errno.h>
+
+#include <nuttx/sdio.h>
+#include <nuttx/mmcsd.h>
+
+#include "chip.h"
+#include "board_config.h"
+#include "stm32_gpio.h"
+#include "stm32_sdmmc.h"
+
+#ifdef CONFIG_MMCSD
+
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+/* Debug ********************************************************************/
+
+#ifdef CONFIG_CPP_HAVE_VARARGS
+#  ifdef CONFIG_DEBUG
+#    define message(...) syslog(__VA_ARGS__)
+#  else
+#    define message(...) printf(__VA_ARGS__)
+#  endif
+#else
+#  ifdef CONFIG_DEBUG
+#    define message syslog
+#  else
+#    define message printf
+#  endif
+#endif
+
+/* Card detections requires card support and a card detection GPIO */
+
+#define HAVE_NCD   1
+#if !defined(GPIO_SDMMC1_NCD)
+#  undef HAVE_NCD
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static FAR struct sdio_dev_s *sdio_dev;
+#ifdef HAVE_NCD
+static bool g_sd_inserted = 0xff; /* Impossible value */
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_ncd_interrupt
+ *
+ * Description:
+ *   Card detect interrupt handler.
+ *
+ ****************************************************************************/
+
+#ifdef HAVE_NCD
+static int stm32_ncd_interrupt(int irq, FAR void *context)
+{
+	bool present;
+
+	present = !stm32_gpioread(GPIO_SDMMC1_NCD);
+
+	if (sdio_dev && present != g_sd_inserted) {
+		sdio_mediachange(sdio_dev, present);
+		g_sd_inserted = present;
+	}
+
+	return OK;
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_sdio_initialize
+ *
+ * Description:
+ *   Initialize SDIO-based MMC/SD card support
+ *
+ ****************************************************************************/
+
+int stm32_sdio_initialize(void)
+{
+	int ret;
+
+#ifdef HAVE_NCD
+	/* Card detect */
+
+	bool cd_status;
+
+	/* Configure the card detect GPIO */
+
+	stm32_configgpio(GPIO_SDMMC1_NCD);
+
+	/* Register an interrupt handler for the card detect pin */
+
+	stm32_gpiosetevent(GPIO_SDMMC1_NCD, true, true, true, stm32_ncd_interrupt);
+#endif
+
+	/* Mount the SDIO-based MMC/SD block driver */
+	/* First, get an instance of the SDIO interface */
+
+	finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO);
+
+	sdio_dev = sdio_initialize(SDIO_SLOTNO);
+
+	if (!sdio_dev) {
+		message("[boot] Failed to initialize SDIO slot %d\n", SDIO_SLOTNO);
+		return -ENODEV;
+	}
+
+	/* Now bind the SDIO interface to the MMC/SD driver */
+
+	finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR);
+
+	ret = mmcsd_slotinitialize(SDIO_MINOR, sdio_dev);
+
+	if (ret != OK) {
+		message("[boot] Failed to bind SDIO to the MMC/SD driver: %d\n", ret);
+		return ret;
+	}
+
+	finfo("Successfully bound SDIO to the MMC/SD driver\n");
+
+#ifdef HAVE_NCD
+	/* Use SD card detect pin to check if a card is g_sd_inserted */
+
+	cd_status = !stm32_gpioread(GPIO_SDMMC1_NCD);
+	finfo("Card detect : %d\n", cd_status);
+
+	sdio_mediachange(sdio_dev, cd_status);
+#else
+	/* Assume that the SD card is inserted.  What choice do we have? */
+
+	sdio_mediachange(sdio_dev, true);
+#endif
+
+	return OK;
+}
+
+#endif /* CONFIG_MMCSD */
@@ -0,0 +1,534 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file px4fmu_spi.c
+ *
+ * Board-specific SPI functions.
+ */
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <px4_config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+#include <unistd.h>
+
+#include <nuttx/spi/spi.h>
+#include <arch/board/board.h>
+#include <systemlib/px4_macros.h>
+
+#include <up_arch.h>
+#include <chip.h>
+#include <stm32_gpio.h>
+#include "board_config.h"
+#include <systemlib/err.h>
+
+/****************************************************************************
+ * Pre-Processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+/* Debug ********************************************************************/
+
+#ifdef CONFIG_CPP_HAVE_VARARGS
+#  ifdef CONFIG_DEBUG
+#    define message(...) syslog(__VA_ARGS__)
+#  else
+#    define message(...) printf(__VA_ARGS__)
+#  endif
+#else
+#  ifdef CONFIG_DEBUG
+#    define message syslog
+#  else
+#    define message printf
+#  endif
+#endif
+
+/* Define CS GPIO array */
+static const uint32_t spi1selects_gpio[] = PX4_SENSOR_BUS_CS_GPIO;
+static const uint32_t spi2selects_gpio[] = PX4_MEMORY_BUS_CS_GPIO;
+#ifdef CONFIG_STM32F7_SPI3
+static const uint32_t spi3selects_gpio[] = {FIXME};
+#error Need to define SPI3 Usage
+#endif
+static const uint32_t spi4selects_gpio[] = PX4_BARO_BUS_CS_GPIO;
+#ifdef CONFIG_STM32F7_SPI3
+static const uint32_t spi5selects_gpio[] = {FIXME};;
+#error Need to define SPI5 Usage
+#endif
+static const uint32_t spi6selects_gpio[] = PX4_EXTERNAL_BUS_CS_GPIO;
+
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32_spiinitialize
+ *
+ * Description:
+ *   Called to configure SPI chip select GPIO pins for the PX4FMU board.
+ *
+ ************************************************************************************/
+
+__EXPORT void stm32_spiinitialize(void)
+{
+#ifdef CONFIG_STM32F7_SPI1
+
+	for (int cs = 0; cs < arraySize(spi1selects_gpio); cs++) {
+		if (spi1selects_gpio[cs] != 0) {
+			stm32_configgpio(spi1selects_gpio[cs]);
+		}
+	}
+
+#endif
+
+#ifdef CONFIG_STM32F7_SPI2
+
+	for (int cs = 0; cs < arraySize(spi2selects_gpio); cs++) {
+		if (spi2selects_gpio[cs] != 0) {
+			stm32_configgpio(spi2selects_gpio[cs]);
+		}
+	}
+
+#endif
+#ifdef CONFIG_STM32F7_SPI3
+
+	for (int cs = 0; cs < arraySize(spi3selects_gpio); cs++) {
+		if (spi3selects_gpio[cs] != 0) {
+			stm32_configgpio(spi3selects_gpio[cs]);
+		}
+	}
+
+#endif
+#ifdef CONFIG_STM32F7_SPI4
+
+	for (int cs = 0; cs < arraySize(spi4selects_gpio); cs++) {
+		if (spi4selects_gpio[cs] != 0) {
+			stm32_configgpio(spi4selects_gpio[cs]);
+		}
+	}
+
+#endif
+#ifdef CONFIG_STM32F7_SPI5
+
+	for (int cs = 0; cs < arraySize(spi5selects_gpio); cs++) {
+		if (spi5selects_gpio[cs] != 0) {
+			stm32_configgpio(spi5selects_gpio[cs]);
+		}
+	}
+
+#endif
+#ifdef CONFIG_STM32F7_SPI6
+
+	for (int cs = 0; cs < arraySize(spi6selects_gpio); cs++) {
+		if (spi6selects_gpio[cs] != 0) {
+			stm32_configgpio(spi6selects_gpio[cs]);
+		}
+	}
+
+#endif
+
+}
+
+/************************************************************************************
+ * Name: stm32_spi_bus_initialize
+ *
+ * Description:
+ *   Called to configure SPI buses on PX4FMU board.
+ *
+ ************************************************************************************/
+static struct spi_dev_s *spi_sensors;
+static struct spi_dev_s *spi_memory;
+static struct spi_dev_s *spi_baro;
+static struct spi_dev_s *spi_ext;
+
+__EXPORT int stm32_spi_bus_initialize(void)
+{
+	/* Configure SPI-based devices */
+
+	/* Get the SPI port for the Sensors */
+
+	spi_sensors = stm32_spibus_initialize(PX4_SPI_BUS_SENSORS);
+
+	if (!spi_sensors) {
+		message("[boot] FAILED to initialize SPI port %d\n", PX4_SPI_BUS_SENSORS);
+		return -ENODEV;
+	}
+
+	/* Default PX4_SPI_BUS_SENSORS to 1MHz and de-assert the known chip selects. */
+
+	SPI_SETFREQUENCY(spi_sensors, 10000000);
+	SPI_SETBITS(spi_sensors, 8);
+	SPI_SETMODE(spi_sensors, SPIDEV_MODE3);
+
+	for (int cs = PX4_SENSORS_BUS_FIRST_CS; cs <= PX4_SENSORS_BUS_LAST_CS; cs++) {
+		SPI_SELECT(spi_sensors, cs, false);
+	}
+
+	/* Get the SPI port for the Memory */
+
+	spi_memory = stm32_spibus_initialize(PX4_SPI_BUS_MEMORY);
+
+	if (!spi_memory) {
+		message("[boot] FAILED to initialize SPI port %d\n", PX4_SPI_BUS_MEMORY);
+		return -ENODEV;
+	}
+
+	/* Default PX4_SPI_BUS_MEMORY to 12MHz and de-assert the known chip selects.
+	 */
+
+	SPI_SETFREQUENCY(spi_memory, 12 * 1000 * 1000);
+	SPI_SETBITS(spi_memory, 8);
+	SPI_SETMODE(spi_memory, SPIDEV_MODE3);
+
+	for (int cs = PX4_MEMORY_BUS_FIRST_CS; cs <= PX4_MEMORY_BUS_LAST_CS; cs++) {
+		SPI_SELECT(spi_memory, cs, false);
+	}
+
+	/* Get the SPI port for the BARO */
+
+	spi_baro = stm32_spibus_initialize(PX4_SPI_BUS_BARO);
+
+	if (!spi_baro) {
+		message("[boot] FAILED to initialize SPI port %d\n", PX4_SPI_BUS_BARO);
+		return -ENODEV;
+	}
+
+	/* MS5611 has max SPI clock speed of 20MHz
+	 */
+
+	SPI_SETFREQUENCY(spi_baro, 20 * 1000 * 1000);
+	SPI_SETBITS(spi_baro, 8);
+	SPI_SETMODE(spi_baro, SPIDEV_MODE3);
+
+	for (int cs = PX4_BARO_BUS_FIRST_CS; cs <= PX4_BARO_BUS_LAST_CS; cs++) {
+		SPI_SELECT(spi_baro, cs, false);
+	}
+
+	/* Get the SPI port for the PX4_SPI_EXTERNAL */
+
+	spi_ext = stm32_spibus_initialize(PX4_SPI_BUS_EXTERNAL);
+
+	if (!spi_ext) {
+		message("[boot] FAILED to initialize SPI port %d\n", PX4_SPI_BUS_EXTERNAL);
+		return -ENODEV;
+	}
+
+	SPI_SETFREQUENCY(spi_ext, 8 * 1000 * 1000);
+	SPI_SETBITS(spi_ext, 8);
+	SPI_SETMODE(spi_ext, SPIDEV_MODE3);
+
+	for (int cs = PX4_EXTERNAL_BUS_FIRST_CS; cs <= PX4_EXTERNAL_BUS_LAST_CS; cs++) {
+		SPI_SELECT(spi_ext, cs, false);
+	}
+
+	return OK;
+
+}
+
+/************************************************************************************
+ * Name: stm32_spi1select and stm32_spi1status
+ *
+ * Description:
+ *   Called by stm32 spi driver on bus 1.
+ *
+ ************************************************************************************/
+
+__EXPORT void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
+{
+	/* SPI select is active low, so write !selected to select the device */
+
+	int sel = (int) devid;
+	ASSERT(PX4_SPI_BUS_ID(sel) == PX4_SPI_BUS_SENSORS);
+
+	/* Making sure the other peripherals are not selected */
+
+	for (int cs = 0;  arraySize(spi1selects_gpio) > 1 && cs < arraySize(spi1selects_gpio); cs++) {
+		if (spi1selects_gpio[cs] != 0) {
+			stm32_gpiowrite(spi1selects_gpio[cs], 1);
+		}
+	}
+
+	uint32_t gpio = spi1selects_gpio[PX4_SPI_DEV_ID(sel)];
+
+	if (gpio) {
+		stm32_gpiowrite(gpio, !selected);
+	}
+}
+
+__EXPORT uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
+{
+	return SPI_STATUS_PRESENT;
+}
+
+
+/************************************************************************************
+ * Name: stm32_spi2select and stm32_spi2status
+ *
+ * Description:
+ *   Called by stm32 spi driver on bus 2.
+ *
+ ************************************************************************************/
+
+__EXPORT void stm32_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
+{
+	/* SPI select is active low, so write !selected to select the device */
+
+	int sel = (int) devid;
+
+	if (devid == SPIDEV_FLASH) {
+		sel = PX4_SPIDEV_MEMORY;
+	}
+
+	ASSERT(PX4_SPI_BUS_ID(sel) == PX4_SPI_BUS_MEMORY);
+
+	/* Making sure the other peripherals are not selected */
+
+	for (int cs = 0;  arraySize(spi2selects_gpio) > 1 && cs < arraySize(spi2selects_gpio); cs++) {
+		if (spi2selects_gpio[cs] != 0) {
+			stm32_gpiowrite(spi2selects_gpio[cs], 1);
+		}
+	}
+
+	uint32_t gpio = spi2selects_gpio[PX4_SPI_DEV_ID(sel)];
+
+	if (gpio) {
+		stm32_gpiowrite(gpio, !selected);
+	}
+}
+
+__EXPORT uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
+{
+	return SPI_STATUS_PRESENT;
+}
+
+/************************************************************************************
+ * Name: stm32_spi3select and stm32_spi2status
+ *
+ * Description:
+ *   Called by stm32 spi driver on bus 3.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_STM32F7_SPI3
+__EXPORT void stm32_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
+{
+	/* SPI select is active low, so write !selected to select the device */
+
+	int sel = (int) devid;
+	ASSERT(PX4_SPI_BUS_ID(sel) == FIXME);
+
+	/* Making sure the other peripherals are not selected */
+
+	for (int cs = 0;  arraySize(spi3selects_gpio) > 1 && cs < arraySize(spi3selects_gpio); cs++) {
+		if (spi3selects_gpio[cs] != 0) {
+			stm32_gpiowrite(spi3selects_gpio[cs], 1);
+		}
+	}
+
+	uint32_t gpio = spi3selects_gpio[PX4_SPI_DEV_ID(sel)];
+
+	if (gpio) {
+		stm32_gpiowrite(gpio, !selected);
+	}
+}
+
+__EXPORT uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
+{
+	return SPI_STATUS_PRESENT;
+}
+#endif
+/************************************************************************************
+ * Name: stm32_spi4select and stm32_spi4status
+ *
+ * Description:
+ *   Called by stm32 spi driver on bus 4.
+ *
+ ************************************************************************************/
+
+__EXPORT void stm32_spi4select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
+{
+	int sel = (int) devid;
+
+	ASSERT(PX4_SPI_BUS_ID(sel) == PX4_SPI_BUS_BARO);
+
+	/* Making sure the other peripherals are not selected */
+	for (int cs = 0; arraySize(spi4selects_gpio) > 1 && cs < arraySize(spi4selects_gpio); cs++) {
+		stm32_gpiowrite(spi4selects_gpio[cs], 1);
+	}
+
+	uint32_t gpio = spi4selects_gpio[PX4_SPI_DEV_ID(sel)];
+
+	if (gpio) {
+		stm32_gpiowrite(gpio, !selected);
+	}
+}
+
+__EXPORT uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
+{
+	return SPI_STATUS_PRESENT;
+}
+
+/************************************************************************************
+ * Name: stm32_spi5select and stm32_spi5status
+ *
+ * Description:
+ *   Called by stm32 spi driver on bus 5.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_STM32F7_SPI5
+__EXPORT void stm32_spi5select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
+{
+	/* SPI select is active low, so write !selected to select the device */
+
+	int sel = (int) devid;
+
+	ASSERT(PX4_SPI_BUS_ID(sel) == FIXME);
+
+	/* Making sure the other peripherals are not selected */
+	for (int cs = 0; arraySize(spi5selects_gpio) > 1 && cs < arraySize(spi5selects_gpio); cs++) {
+		stm32_gpiowrite(spi5selects_gpio[cs], 1);
+	}
+
+	uint32_t gpio = spi5selects_gpio[PX4_SPI_DEV_ID(sel)];
+
+	if (gpio) {
+		stm32_gpiowrite(gpio, !selected);
+	}
+}
+
+__EXPORT uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
+{
+	return SPI_STATUS_PRESENT;
+}
+#endif
+
+/************************************************************************************
+ * Name: stm32_spi6select and stm32_spi6status
+ *
+ * Description:
+ *   Called by stm32 spi driver on bus 6.
+ *
+ ************************************************************************************/
+
+__EXPORT void stm32_spi6select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
+{
+	/* SPI select is active low, so write !selected to select the device */
+
+	int sel = (int) devid;
+
+	ASSERT(PX4_SPI_BUS_ID(sel) == PX4_SPI_BUS_EXTERNAL);
+
+	/* Making sure the other peripherals are not selected */
+	for (int cs = 0; arraySize(spi6selects_gpio) > 1 && cs < arraySize(spi6selects_gpio); cs++) {
+		stm32_gpiowrite(spi6selects_gpio[cs], 1);
+	}
+
+	uint32_t gpio = spi6selects_gpio[PX4_SPI_DEV_ID(sel)];
+
+	if (gpio) {
+		stm32_gpiowrite(gpio, !selected);
+	}
+}
+
+__EXPORT uint8_t stm32_spi6status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
+{
+	return SPI_STATUS_PRESENT;
+}
+
+__EXPORT void board_spi_reset(int ms)
+{
+	/* disable SPI bus */
+	for (int cs = 0;  arraySize(spi1selects_gpio) > 1 && cs < arraySize(spi1selects_gpio); cs++) {
+		if (spi1selects_gpio[cs] != 0) {
+			stm32_configgpio(_PIN_OFF(spi1selects_gpio[cs]));
+		}
+	}
+
+	stm32_configgpio(GPIO_SPI1_SCK_OFF);
+	stm32_configgpio(GPIO_SPI1_MISO_OFF);
+	stm32_configgpio(GPIO_SPI1_MOSI_OFF);
+
+
+#if BOARD_USE_DRDY
+	stm32_configgpio(GPIO_DRDY_OFF_ICM20689_DRDY1);
+	stm32_configgpio(GPIO_DRDY_OFF_BMI055_DRDY2_GYRO);
+	stm32_configgpio(GPIO_DRDY_OFF_BMI055_DRDY3_ACC);
+	stm32_configgpio(GPIO_DRDY_OFF_ICM20602_DRDY4);
+	stm32_configgpio(GPIO_DRDY_OFF_BMI055_DRDY5_GYRO);
+	stm32_configgpio(GPIO_DRDY_OFF_BMI055_DRDY6_ACC);
+#endif
+	/* set the sensor rail off */
+	stm32_gpiowrite(GPIO_VDD_3V3_SENSORS_EN, 0);
+
+	/* wait for the sensor rail to reach GND */
+	usleep(ms * 1000);
+	warnx("reset done, %d ms", ms);
+
+	/* re-enable power */
+
+	/* switch the sensor rail back on */
+	stm32_gpiowrite(GPIO_VDD_3V3_SENSORS_EN, 1);
+
+	/* wait a bit before starting SPI, different times didn't influence results */
+	usleep(100);
+
+	/* reconfigure the SPI pins */
+	for (int cs = 0;  arraySize(spi1selects_gpio) > 1 && cs < arraySize(spi1selects_gpio); cs++) {
+		if (spi1selects_gpio[cs] != 0) {
+			stm32_configgpio(spi1selects_gpio[cs]);
+		}
+	}
+
+	stm32_configgpio(GPIO_SPI1_SCK);
+	stm32_configgpio(GPIO_SPI1_MISO);
+	stm32_configgpio(GPIO_SPI1_MOSI);
+
+#if BOARD_USE_DRDY
+	stm32_configgpio(GPIO_ICM20689_DRDY1);
+	stm32_configgpio(GPIO_BMI055_DRDY2_GYRO);
+	stm32_configgpio(GPIO_BMI055_DRDY3_ACC);
+	stm32_configgpio(GPIO_ICM20602_DRDY4);
+	stm32_configgpio(GPIO_BMI055_DRDY5_GYRO);
+	stm32_configgpio(GPIO_BMI055_DRDY6_ACC);
+#endif
+
+}
@@ -0,0 +1,126 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2012 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/*
+ * @file px4fmu_timer_config.c
+ *
+ * Configuration data for the stm32 pwm_servo, input capture and pwm input driver.
+ *
+ * Note that these arrays must always be fully-sized.
+ */
+
+#include <stdint.h>
+
+#include <chip.h>
+#include <stm32_gpio.h>
+#include <stm32_tim.h>
+
+#include <drivers/drv_pwm_output.h>
+#include <drivers/stm32/drv_io_timer.h>
+
+#include "board_config.h"
+
+__EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
+	{
+		.base = STM32_TIM1_BASE,
+		.clock_register = STM32_RCC_APB2ENR,
+		.clock_bit = RCC_APB2ENR_TIM1EN,
+		.clock_freq = STM32_APB2_TIM1_CLKIN,
+		.first_channel_index = 0,
+		.last_channel_index = 3,
+		.handler = io_timer_handler0,
+		.vectorno =  STM32_IRQ_TIM1CC,
+
+	},
+	{
+		.base = STM32_TIM4_BASE,
+		.clock_register = STM32_RCC_APB1ENR,
+		.clock_bit = RCC_APB1ENR_TIM4EN,
+		.clock_freq = STM32_APB1_TIM4_CLKIN,
+		.first_channel_index = 4,
+		.last_channel_index = 5,
+		.handler = io_timer_handler1,
+		.vectorno =  STM32_IRQ_TIM4,
+	}
+};
+
+__EXPORT const timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
+	{
+		.gpio_out = GPIO_TIM1_CH4OUT,
+		.gpio_in  = GPIO_TIM1_CH4IN,
+		.timer_index = 0,
+		.timer_channel = 4,
+		.ccr_offset = STM32_GTIM_CCR4_OFFSET,
+		.masks  = GTIM_SR_CC4IF | GTIM_SR_CC4OF
+	},
+	{
+		.gpio_out = GPIO_TIM1_CH3OUT,
+		.gpio_in = GPIO_TIM1_CH3IN,
+		.timer_index = 0,
+		.timer_channel = 3,
+		.ccr_offset = STM32_GTIM_CCR3_OFFSET,
+		.masks  = GTIM_SR_CC3IF | GTIM_SR_CC3OF
+	},
+	{
+		.gpio_out = GPIO_TIM1_CH2OUT,
+		.gpio_in = GPIO_TIM1_CH2IN,
+		.timer_index = 0,
+		.timer_channel = 2,
+		.ccr_offset = STM32_GTIM_CCR2_OFFSET,
+		.masks  = GTIM_SR_CC2IF | GTIM_SR_CC2OF
+	},
+	{
+		.gpio_out = GPIO_TIM1_CH1OUT,
+		.gpio_in = GPIO_TIM1_CH1IN,
+		.timer_index = 0,
+		.timer_channel = 1,
+		.ccr_offset = STM32_GTIM_CCR1_OFFSET,
+		.masks  = GTIM_SR_CC1IF | GTIM_SR_CC1OF
+	},
+	{
+		.gpio_out = GPIO_TIM4_CH2OUT,
+		.gpio_in = GPIO_TIM4_CH2IN,
+		.timer_index = 1,
+		.timer_channel = 2,
+		.ccr_offset = STM32_GTIM_CCR2_OFFSET,
+		.masks  = GTIM_SR_CC2IF | GTIM_SR_CC2OF
+	},
+	{
+		.gpio_out = GPIO_TIM4_CH3OUT,
+		.gpio_in = GPIO_TIM4_CH3IN,
+		.timer_index = 1,
+		.timer_channel = 3,
+		.ccr_offset = STM32_GTIM_CCR3_OFFSET,
+		.masks  = GTIM_SR_CC3IF | GTIM_SR_CC3OF
+	}
+};
@@ -0,0 +1,105 @@
+/****************************************************************************
+ *
+ *   Copyright (C) 2016 PX4 Development Team. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name PX4 nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/**
+ * @file px4fmu_usb.c
+ *
+ * Board-specific USB functions.
+ */
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <px4_config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+
+#include <nuttx/usb/usbdev.h>
+#include <nuttx/usb/usbdev_trace.h>
+
+#include <up_arch.h>
+#include <chip.h>
+#include <stm32_gpio.h>
+#include <stm32_otg.h>
+#include "board_config.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32_usbinitialize
+ *
+ * Description:
+ *   Called to setup USB-related GPIO pins for the PX4FMU board.
+ *
+ ************************************************************************************/
+
+__EXPORT void stm32_usbinitialize(void)
+{
+	/* The OTG FS has an internal soft pull-up */
+
+	/* Configure the OTG FS VBUS sensing GPIO, Power On, and Overcurrent GPIOs */
+
+#ifdef CONFIG_STM32F7_OTGFS
+	stm32_configgpio(GPIO_OTGFS_VBUS);
+#endif
+}
+
+/************************************************************************************
+ * Name:  stm32_usbsuspend
+ *
+ * Description:
+ *   Board logic must provide the stm32_usbsuspend logic if the USBDEV driver is
+ *   used.  This function is called whenever the USB enters or leaves suspend mode.
+ *   This is an opportunity for the board logic to shutdown clocks, power, etc.
+ *   while the USB is suspended.
+ *
+ ************************************************************************************/
+
+__EXPORT void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
+{
+	uinfo("resume: %d\n", resume);
+}