HOTFIX: disable interrupt-driven I2C mode, configure pessimistic I2C timeout, correct handling of the NAK generation for I2C master reads.

This looks like it addresses the recent I2C lockup issue, unfortunately it also increases CPU consumption by ~5% for the I2C sensor bus.
This commit is contained in:
px4dev
2013-01-18 00:43:57 -08:00
parent 7d7c352fb4
commit bc35bb23dd
4 changed files with 56 additions and 12 deletions
+10 -8
View File
@@ -352,17 +352,19 @@ CONFIG_CAN2_BAUD=700000
# I2C configuration
#
CONFIG_I2C=y
#CONFIG_I2C_POLLED=y
CONFIG_I2C_POLLED=y
CONFIG_I2C_TRANSFER=y
CONFIG_I2C_TRACE=n
CONFIG_I2C_RESET=y
# Allow 180 us per byte, a wide margin for the 400 KHz clock we're using
# e.g. 9.6 ms for an EEPROM page write, 0.9 ms for a MAG update
CONFIG_STM32_I2CTIMEOUS_PER_BYTE=200
# Constant overhead for generating I2C start / stop conditions
CONFIG_STM32_I2CTIMEOUS_START_STOP=700
# XXX this is bad and we want it gone
CONFIG_I2C_WRITEREAD=y
# Dynamic timeout
#CONFIG_STM32_I2C_DYNTIMEO=y
#CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP=500
#CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE=200
# Fixed per-transaction timeout
CONFIG_STM32_I2CTIMEOSEC=0
CONFIG_STM32_I2CTIMEOMS=10
#
# General build options