mro pixracerpro:Properly configure BDMA

This commit is contained in:
David Sidrane 2021-03-22 11:05:30 -07:00 committed by David Sidrane
parent a8ece584e5
commit bbdb671dd2
3 changed files with 3 additions and 3 deletions

View File

@ -90,7 +90,6 @@ CONFIG_MEMSET_OPTSPEED=y
CONFIG_MMCSD=y
CONFIG_MMCSD_SDIO=y
CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE=y
CONFIG_MM_REGIONS=3
CONFIG_MTD=y
CONFIG_MTD_BYTE_WRITE=y
CONFIG_MTD_PARTITION=y
@ -159,6 +158,7 @@ CONFIG_STM32H7_ADC1=y
CONFIG_STM32H7_ADC3=y
CONFIG_STM32H7_BBSRAM=y
CONFIG_STM32H7_BBSRAM_FILES=5
CONFIG_STM32H7_BDMA=y
CONFIG_STM32H7_BKPSRAM=y
CONFIG_STM32H7_DMA1=y
CONFIG_STM32H7_DMA2=y

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@ -197,7 +197,7 @@ SECTIONS
} > AXI_SRAM
/* Emit the the D3 power domain section for locating BDMA data */
.SRAM4 (NOLOAD) :
.sram4 (NOLOAD) :
{
} > SRAM4

View File

@ -197,7 +197,7 @@ SECTIONS
} > AXI_SRAM
/* Emit the the D3 power domain section for locating BDMA data */
.SRAM4 (NOLOAD) :
.sram4 (NOLOAD) :
{
} > SRAM4