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reduce make verbosity

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This commit is contained in:
Daniel Agar
2015-08-29 19:32:02 -04:00
parent fbe5ef6087
commit bb696b756b
7 changed files with 14 additions and 13 deletions
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makefiles/module.mk
+4
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@@ -113,7 +113,9 @@
ifeq ($(MODULE_MK),)
$(error No module makefile specified)
endif
ifeq ($(V),1)
$(info %% MODULE_MK = $(MODULE_MK))
endif
#
# Get the board/toolchain config
@@ -125,10 +127,12 @@ include $(BOARD_FILE)
#
include $(MODULE_MK)
MODULE_SRC := $(dir $(MODULE_MK))
ifeq ($(V),1)
$(info % MODULE_NAME = $(MODULE_NAME))
$(info % MODULE_SRC = $(MODULE_SRC))
$(info % MODULE_OBJ = $(MODULE_OBJ))
$(info % MODULE_WORK_DIR = $(MODULE_WORK_DIR))
endif
#
# Things that, if they change, might affect everything