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Add z180 interrupt vectors

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git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5432 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2012-12-12 16:38:50 +00:00
parent 092c435c46
commit a71e9d8104
7 changed files with 520 additions and 253 deletions
Download Patch File Download Diff File Expand all files Collapse all files
nuttx/arch/z80/src/z180/Make.defs
+8
View File
@@ -49,6 +49,14 @@ CMN_CSRCS += up_releasestack.c up_reprioritizertr.c up_unblocktask.c
CMN_CSRCS += up_udelay.c up_usestack.c
CHIP_ASRCS = z180_restoreusercontext.asm z180_saveusercontext.asm
CHIP_ASRCS += z180_vectcommon.asm
ifeq ($(CONFIG_LINKER_ROM_AT_0000),y)
CHIP_ASRCS += z180_romvectors.asm
else
CHIP_ASRCS += z180_vectors.asm
endif
CHIP_CSRCS = z180_copystate.c z180_initialstate.c z180_io.c z180_irq.c
CHIP_CSRCS += z180_mmu.c z180_registerdump.c z180_schedulesigaction.c
CHIP_CSRCS += z180_sigdeliver.c
nuttx/arch/z80/src/z180/z180_head.asm
+16 -114
View File
@@ -40,18 +40,6 @@
; Constants
;**************************************************************************
; Register save area layout
XCPT_I == 0 ; Offset 0: Saved I w/interrupt state in carry
XCPT_BC == 2 ; Offset 1: Saved BC register
XCPT_DE == 4 ; Offset 2: Saved DE register
XCPT_IX == 6 ; Offset 3: Saved IX register
XCPT_IY == 8 ; Offset 4: Saved IY register
XCPT_SP == 10 ; Offset 5: Offset to SP at time of interrupt
XCPT_HL == 12 ; Offset 6: Saved HL register
XCPT_AF == 14 ; Offset 7: Saved AF register
XCPT_PC == 16 ; Offset 8: Offset to PC at time of interrupt
; Default stack base (needs to be fixed)
.include "asm_mem.h"
@@ -61,8 +49,9 @@
;**************************************************************************
.globl _os_start ; OS entry point
.globl _up_doirq ; Interrupt decoding logic
.globl _up_vectcommon ; Common interrupt handling logic
.globl _z180_mmu_lowinit ; MMU initialization logic
.globl s__HEAP ; Start of the heap
;**************************************************************************
; Reset entry point
@@ -77,16 +66,6 @@
;**************************************************************************
; Other reset handlers
;
; Interrupt mode 1 behavior:
;
; 1. M1 cycle: 7 ticks
; Acknowledge interrupt and decrements SP
; 2. M2 cycle: 3 ticks
; Writes the MS byte of the PC onto the stack and decrements SP
; 3. M3 cycle: 3 ticks
; Writes the LS byte of the PC onto the stack and sets the PC to 0x0038.
;
;**************************************************************************
.org 0x0008 ; RST 1
@@ -95,8 +74,8 @@
; common reset handling logic.
; Offset 8: Return PC is already on the stack
push af ; Offset 7: AF (retaining flags)
ld a, #1 ; 1 = Z180_RST1
jr _up_rstcommon ; Remaining RST handling is common
ld a, #0 ; 0 = Z180_RST1
jp _up_vectcommon ; Remaining RST handling is common
.org 0x0010 ; RST 2
@@ -104,8 +83,8 @@
; common reset handling logic.
; Offset 8: Return PC is already on the stack
push af ; Offset 7: AF (retaining flags)
ld a, #2 ; 2 = Z180_RST2
jr _up_rstcommon ; Remaining RST handling is common
ld a, #1 ; 1 = Z180_RST2
jp _up_vectcommon ; Remaining RST handling is common
.org 0x0018 ; RST 3
@@ -113,8 +92,8 @@
; common reset handling logic.
; Offset 8: Return PC is already on the stack
push af ; Offset 7: AF (retaining flags)
ld a, #3 ; 1 = Z180_RST3
jr _up_rstcommon ; Remaining RST handling is common
ld a, #2 ; 2 = Z180_RST3
jp _up_vectcommon ; Remaining RST handling is common
.org 0x0020 ; RST 4
@@ -122,8 +101,8 @@
; common reset handling logic.
; Offset 8: Return PC is already on the stack
push af ; Offset 7: AF (retaining flags)
ld a, #4 ; 1 = Z180_RST4
jr _up_rstcommon ; Remaining RST handling is common
ld a, #3 ; 3 = Z180_RST4
jp _up_vectcommon ; Remaining RST handling is common
.org 0x0028 ; RST 5
@@ -131,8 +110,8 @@
; common reset handling logic.
; Offset 8: Return PC is already on the stack
push af ; Offset 7: AF (retaining flags)
ld a, #5 ; 1 = Z180_RST5
jr _up_rstcommon ; Remaining RST handling is common
ld a, #4 ; 4 = Z180_RST5
jp _up_vectcommon ; Remaining RST handling is common
.org 0x0030 ; RST 6
@@ -140,8 +119,8 @@
; common reset handling logic.
; Offset 8: Return PC is already on the stack
push af ; Offset 7: AF (retaining flags)
ld a, #6 ; 1 = Z180_RST6
jr _up_rstcommon ; Remaining RST handling is common
ld a, #5 ; 5 = Z180_RST6
jp _up_vectcommon ; Remaining RST handling is common
.org 0x0038 ; Int mode 1 / RST 7
@@ -149,8 +128,8 @@
; common reset handling logic.
; Offset 8: Return PC is already on the stack
push af ; Offset 7: AF (retaining flags)
ld a, #7 ; 7 = Z180_RST7
jr _up_rstcommon ; Remaining RST handling is common
ld a, #6 ; 6 = Z180_RST7
jp _up_vectcommon ; Remaining RST handling is common
;**************************************************************************
; NMI interrupt handler
@@ -188,83 +167,6 @@ _up_halt::
halt ; We should never get here
jp _up_halt
;**************************************************************************
; Common Interrupt handler
;**************************************************************************
_up_rstcommon::
; Create a register frame. SP points to top of frame + 4, pushes
; decrement the stack pointer. Already have
;
; Offset 8: Return PC is already on the stack
; Offset 7: AF (retaining flags)
;
; IRQ number is in A
push hl ; Offset 6: HL
ld hl, #(3*2) ; HL is the value of the stack pointer before
add hl, sp ; the interrupt occurred
push hl ; Offset 5: Stack pointer
push iy ; Offset 4: IY
push ix ; Offset 3: IX
push de ; Offset 2: DE
push bc ; Offset 1: BC
ld b, a ; Save the reset number in B
ld a, i ; Parity bit holds interrupt state
push af ; Offset 0: I with interrupt state in parity
di
; Call the interrupt decode logic. SP points to the beginning of the reg structure
ld hl, #0 ; Argument #2 is the beginning of the reg structure
add hl, sp ;
push hl ; Place argument #2 at the top of stack
push bc ; Argument #1 is the Reset number
inc sp ; (make byte sized)
call _up_doirq ; Decode the IRQ
; On return, HL points to the beginning of the reg structure to restore
; Note that (1) the arguments pushed on the stack are not popped, and (2) the
; original stack pointer is lost. In the normal case (no context switch),
; HL will contain the value of the SP before the arguments were pushed.
ld sp, hl ; Use the new stack pointer
; Restore registers. HL points to the beginning of the reg structure to restore
ex af, af' ; Select alternate AF
pop af ; Offset 0: AF' = I with interrupt state in carry
ex af, af' ; Restore original AF
pop bc ; Offset 1: BC
pop de ; Offset 2: DE
pop ix ; Offset 3: IX
pop iy ; Offset 4: IY
exx ; Use alternate BC/DE/HL
ld hl, #-2 ; Offset of SP to account for ret addr on stack
pop de ; Offset 5: HL' = Stack pointer after return
add hl, de ; HL = Stack pointer value before return
exx ; Restore original BC/DE/HL
pop hl ; Offset 6: HL
pop af ; Offset 7: AF
; Restore the stack pointer
exx ; Use alternate BC/DE/HL
ld sp, hl ; Set SP = saved stack pointer value before return
exx ; Restore original BC/DE/HL
; Restore interrupt state
ex af, af' ; Recover interrupt state
jp po, nointenable ; Odd parity, IFF2=0, means disabled
ex af, af' ; Restore AF (before enabling interrupts)
ei ; yes
reti
nointenable::
ex af, af' ; Restore AF
reti
;**************************************************************************
; Ordering of segments for the linker (SDCC only)
;**************************************************************************
nuttx/arch/z80/src/z180/z180_rom.asm
+18 -115
View File
@@ -40,18 +40,6 @@
; Constants
;**************************************************************************
; Register save area layout
XCPT_I == 0 ; Offset 0: Saved I w/interrupt state in carry
XCPT_BC == 2 ; Offset 1: Saved BC register
XCPT_DE == 4 ; Offset 2: Saved DE register
XCPT_IX == 6 ; Offset 3: Saved IX register
XCPT_IY == 8 ; Offset 4: Saved IY register
XCPT_SP == 10 ; Offset 5: Offset to SP at time of interrupt
XCPT_HL == 12 ; Offset 6: Saved HL register
XCPT_AF == 14 ; Offset 7: Saved AF register
XCPT_PC == 16 ; Offset 8: Offset to PC at time of interrupt
; Default stack base (needs to be fixed)
.include "asm_mem.h"
@@ -60,8 +48,10 @@
; Global symbols used
;**************************************************************************
.globl _os_start ; OS entry point
.globl _up_doirq ; Interrupt decoding logic
.globl _os_start ; OS entry point
.globl _up_vectcommon ; Common interrupt handling logic
.globl _z180_mmu_lowinit ; MMU initialization logic
.globl s__HEAP ; Start of the heap
;**************************************************************************
; System start logic
@@ -107,16 +97,6 @@ _up_rstvectors:
;**************************************************************************
; Other reset handlers
;
; Interrupt mode 1 behavior:
;
; 1. M1 cycle: 7 ticks
; Acknowledge interrupt and decrements SP
; 2. M2 cycle: 3 ticks
; Writes the MS byte of the PC onto the stack and decrements SP
; 3. M3 cycle: 3 ticks
; Writes the LS byte of the PC onto the stack and sets the PC to 0x0038.
;
;**************************************************************************
_up_rst1: ; RST 1
@@ -124,133 +104,56 @@ _up_rst1: ; RST 1
; common reset handling logic.
; Offset 8: Return PC is already on the stack
push af ; Offset 7: AF (retaining flags)
ld a, #1 ; 1 = Z180_RST1
jr _up_rstcommon ; Remaining RST handling is common
ld a, #0 ; 0 = Z180_RST1
jp _up_vectcommon ; Remaining RST handling is common
_up_rst2: ; RST 2
; Save AF on the stack, set the interrupt number and jump to the
; common reset handling logic.
; Offset 8: Return PC is already on the stack
push af ; Offset 7: AF (retaining flags)
ld a, #2 ; 2 = Z180_RST2
jr _up_rstcommon ; Remaining RST handling is common
ld a, #1 ; 1 = Z180_RST2
jp _up_vectcommon ; Remaining RST handling is common
_up_rst3: ; RST 3
; Save AF on the stack, set the interrupt number and jump to the
; common reset handling logic.
; Offset 8: Return PC is already on the stack
push af ; Offset 7: AF (retaining flags)
ld a, #3 ; 1 = Z180_RST3
jr _up_rstcommon ; Remaining RST handling is common
ld a, #2 ; 2 = Z180_RST3
jp _up_vectcommon ; Remaining RST handling is common
_up_rst4: ; RST 4
; Save AF on the stack, set the interrupt number and jump to the
; common reset handling logic.
; Offset 8: Return PC is already on the stack
push af ; Offset 7: AF (retaining flags)
ld a, #4 ; 1 = Z180_RST4
jr _up_rstcommon ; Remaining RST handling is common
ld a, #3 ; 3 = Z180_RST4
jp _up_vectcommon ; Remaining RST handling is common
_up_rst5: ; RST 5
; Save AF on the stack, set the interrupt number and jump to the
; common reset handling logic.
; Offset 8: Return PC is already on the stack
push af ; Offset 7: AF (retaining flags)
ld a, #5 ; 1 = Z180_RST5
jr _up_rstcommon ; Remaining RST handling is common
ld a, #4 ; 4 = Z180_RST5
jp _up_vectcommon ; Remaining RST handling is common
_up_rst6: ; RST 6
; Save AF on the stack, set the interrupt number and jump to the
; common reset handling logic.
; Offset 8: Return PC is already on the stack
push af ; Offset 7: AF (retaining flags)
ld a, #6 ; 1 = Z180_RST6
jr _up_rstcommon ; Remaining RST handling is common
ld a, #5 ; 5 = Z180_RST6
jp _up_vectcommon ; Remaining RST handling is common
_up_rst7: ; RST 7
; Save AF on the stack, set the interrupt number and jump to the
; common reset handling logic.
; Offset 8: Return PC is already on the stack
push af ; Offset 7: AF (retaining flags)
ld a, #7 ; 7 = Z180_RST7
jr _up_rstcommon ; Remaining RST handling is common
;**************************************************************************
; Common Interrupt handler
;**************************************************************************
_up_rstcommon:
; Create a register frame. SP points to top of frame + 4, pushes
; decrement the stack pointer. Already have
;
; Offset 8: Return PC is already on the stack
; Offset 7: AF (retaining flags)
;
; IRQ number is in A
push hl ; Offset 6: HL
ld hl, #(3*2) ; HL is the value of the stack pointer before
add hl, sp ; the interrupt occurred
push hl ; Offset 5: Stack pointer
push iy ; Offset 4: IY
push ix ; Offset 3: IX
push de ; Offset 2: DE
push bc ; Offset 1: BC
ld b, a ; Save the reset number in B
ld a, i ; Parity bit holds interrupt state
push af ; Offset 0: I with interrupt state in parity
di
; Call the interrupt decode logic. SP points to the beginning of the reg structure
ld hl, #0 ; Argument #2 is the beginning of the reg structure
add hl, sp ;
push hl ; Place argument #2 at the top of stack
push bc ; Argument #1 is the Reset number
inc sp ; (make byte sized)
call _up_doirq ; Decode the IRQ
; On return, HL points to the beginning of the reg structure to restore
; Note that (1) the arguments pushed on the stack are not popped, and (2) the
; original stack pointer is lost. In the normal case (no context switch),
; HL will contain the value of the SP before the arguments were pushed.
ld sp, hl ; Use the new stack pointer
; Restore registers. HL points to the beginning of the reg structure to restore
ex af, af' ; Select alternate AF
pop af ; Offset 0: AF' = I with interrupt state in carry
ex af, af' ; Restore original AF
pop bc ; Offset 1: BC
pop de ; Offset 2: DE
pop ix ; Offset 3: IX
pop iy ; Offset 4: IY
exx ; Use alternate BC/DE/HL
ld hl, #-2 ; Offset of SP to account for ret addr on stack
pop de ; Offset 5: HL' = Stack pointer after return
add hl, de ; HL = Stack pointer value before return
exx ; Restore original BC/DE/HL
pop hl ; Offset 6: HL
pop af ; Offset 7: AF
; Restore the stack pointer
exx ; Use alternate BC/DE/HL
ld sp, hl ; Set SP = saved stack pointer value before return
exx ; Restore original BC/DE/HL
; Restore interrupt state
ex af, af' ; Recover interrupt state
jp po, nointenable ; Odd parity, IFF2=0, means disabled
ex af, af' ; Restore AF (before enabling interrupts)
ei ; yes
reti
nointenable::
ex af, af' ; Restore AF
reti
ld a, #6 ; 6 = Z180_RST7
jp _up_vectcommon ; Remaining RST handling is common
;**************************************************************************
; Ordering of segments for the linker (SDCC only)
nuttx/arch/z80/src/z180/z180_romvectors.asm
+89
View File
@@ -0,0 +1,89 @@
;**************************************************************************
; arch/z80/src/z180/z180_romvectors.asm
;
; Copyright (C) 2012 Gregory Nutt. All rights reserved.
; Author: Gregory Nutt <gnutt@nuttx.org>
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions
; are met:
;
; 1. Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; 2. Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in
; the documentation and/or other materials provided with the
; distribution.
; 3. Neither the name NuttX nor the names of its contributors may be
; used to endorse or promote products derived from this software
; without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
; FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
; COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
; OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
; ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;
;**************************************************************************
.title NuttX for the Z180
.module z180_romvectors
;**************************************************************************
; Constants
;**************************************************************************
;**************************************************************************
; Global symbols used
;**************************************************************************
.globl _up_int1 ; Vector offset 0: External /INT1
.globl _up_int2 ; Vector offset 2: External /INT2
.globl _up_prt0 ; Vector offset 4: PRT channel 0
.globl _up_prt1 ; Vector offset 6: PRT channel 1
.globl _up_dma0 ; Vector offset 8: DMA channel 0
.globl _up_dma1 ; Vector offset 8: DMA channel 1
.globl _up_csio ; Vector offset 12: Clocked serial I/O
.globl _up_asci0 ; Vector offset 14: Async channel 0
.globl _up_asci1 ; Vector offset 16: Async channel 1
.globl _up_unused ; Vector offset 18: Unused
.globl _up_unused ; Vector offset 20: Unused
.globl _up_unused ; Vector offset 22: Unused
.globl _up_unused ; Vector offset 24: Unused
.globl _up_unused ; Vector offset 26: Unused
.globl _up_unused ; Vector offset 28: Unused
.globl _up_unused ; Vector offset 30: Unused
;**************************************************************************
; Interrupt Vector Table
;**************************************************************************
; The start of the _VECTORS area must be set by the linker to lie at some
; 32-byte-aligned address
.area _VECTORS
_up_vectors::
.dw up_int1 ; Vector offset 0: External /INT1
.dw up_int2 ; Vector offset 2: External /INT2
.dw up_prt0 ; Vector offset 4: PRT channel 0
.dw up_prt1 ; Vector offset 6: PRT channel 1
.dw up_dma0 ; Vector offset 8: DMA channel 0
.dw up_dma1 ; Vector offset 8: DMA channel 1
.dw up_csio ; Vector offset 12: Clocked serial I/O
.dw up_asci0 ; Vector offset 14: Async channel 0
.dw up_asci1 ; Vector offset 16: Async channel 1
.dw up_unused ; Vector offset 18: Unused
.dw up_unused ; Vector offset 20: Unused
.dw up_unused ; Vector offset 22: Unused
.dw up_unused ; Vector offset 24: Unused
.dw up_unused ; Vector offset 26: Unused
.dw up_unused ; Vector offset 28: Unused
.dw up_unused ; Vector offset 30: Unused
nuttx/arch/z80/src/z180/z180_vectcommon.asm
+223
View File
@@ -0,0 +1,223 @@
;**************************************************************************
; arch/z80/src/z180/z180_vectcommon.asm
;
; Copyright (C) 2012 Gregory Nutt. All rights reserved.
; Author: Gregory Nutt <gnutt@nuttx.org>
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions
; are met:
;
; 1. Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; 2. Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in
; the documentation and/or other materials provided with the
; distribution.
; 3. Neither the name NuttX nor the names of its contributors may be
; used to endorse or promote products derived from this software
; without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
; FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
; COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
; OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
; ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;
;**************************************************************************
.title NuttX for the Z180
.module z180_vectcommon
;**************************************************************************
; Constants
;**************************************************************************
; Register save area layout
XCPT_I == 0 ; Offset 0: Saved I w/interrupt state in carry
XCPT_BC == 2 ; Offset 1: Saved BC register
XCPT_DE == 4 ; Offset 2: Saved DE register
XCPT_IX == 6 ; Offset 3: Saved IX register
XCPT_IY == 8 ; Offset 4: Saved IY register
XCPT_SP == 10 ; Offset 5: Offset to SP at time of interrupt
XCPT_HL == 12 ; Offset 6: Saved HL register
XCPT_AF == 14 ; Offset 7: Saved AF register
XCPT_PC == 16 ; Offset 8: Offset to PC at time of interrupt
;**************************************************************************
; Global symbols used
;**************************************************************************
.globl _up_doirq ; Interrupt decoding logic
;**************************************************************************
; Vector Handlers
;**************************************************************************
.area _CODE
up_int1:: ; Vector offset 0: External /INT1
; Save AF on the stack, set the interrupt number and jump to the
; common reset handling logic.
; Offset 8: Return PC is already on the stack
push af ; Offset 7: AF (retaining flags)
ld a, #9 ; 9 = Z180_INT1
jr _up_vectcommon ; Remaining RST handling is common
up_int2:: ; Vector offset 2: External /INT2
; Save AF on the stack, set the interrupt number and jump to the
; common reset handling logic.
; Offset 8: Return PC is already on the stack
push af ; Offset 7: AF (retaining flags)
ld a, #10 ; 10 = Z180_INT2
jr _up_vectcommon ; Remaining RST handling is common
up_prt0:: ; Vector offset 4: PRT channel 0
; Save AF on the stack, set the interrupt number and jump to the
; common reset handling logic.
; Offset 8: Return PC is already on the stack
push af ; Offset 7: AF (retaining flags)
ld a, #11 ; 11 = Z180_PRT0
jr _up_vectcommon ; Remaining RST handling is common
up_prt1:: ; Vector offset 6: PRT channel 1
; Save AF on the stack, set the interrupt number and jump to the
; common reset handling logic.
; Offset 8: Return PC is already on the stack
push af ; Offset 7: AF (retaining flags)
ld a, #12 ; 12 = Z180_PRT1
jr _up_vectcommon ; Remaining RST handling is common
up_dma0:: ; Vector offset 8: DMA channel 0
; Save AF on the stack, set the interrupt number and jump to the
; common reset handling logic.
; Offset 8: Return PC is already on the stack
push af ; Offset 7: AF (retaining flags)
ld a, #13 ; 13 = Z180_DMA0
jr _up_vectcommon ; Remaining RST handling is common
up_dma1:: ; Vector offset 8: DMA channel 1
; Save AF on the stack, set the interrupt number and jump to the
; common reset handling logic.
; Offset 8: Return PC is already on the stack
push af ; Offset 7: AF (retaining flags)
ld a, #14 ; 14 = Z180_DMA1
jr _up_vectcommon ; Remaining RST handling is common
up_csio:: ; Vector offset 12: Clocked serial I/O
; Save AF on the stack, set the interrupt number and jump to the
; common reset handling logic.
; Offset 8: Return PC is already on the stack
push af ; Offset 7: AF (retaining flags)
ld a, #15 ; 15 = Z180_CSIO
jr _up_vectcommon ; Remaining RST handling is common
up_asci0:: ; Vector offset 14: Async channel 0
; Save AF on the stack, set the interrupt number and jump to the
; common reset handling logic.
; Offset 8: Return PC is already on the stack
push af ; Offset 7: AF (retaining flags)
ld a, #16 ; 16 = Z180_ASCI0
jr _up_vectcommon ; Remaining RST handling is common
up_asci1:: ; Vector offset 16: Async channel 1
; Save AF on the stack, set the interrupt number and jump to the
; common reset handling logic.
; Offset 8: Return PC is already on the stack
push af ; Offset 7: AF (retaining flags)
ld a, #17 ; 17 = Z180_ASCI1
jr _up_vectcommon ; Remaining RST handling is common
up_unused:: ; Vector offset 18: Unused
; Save AF on the stack, set the interrupt number and jump to the
; common reset handling logic.
; Offset 8: Return PC is already on the stack
push af ; Offset 7: AF (retaining flags)
ld a, #18 ; 18 = Z180_UNUSED
jr _up_vectcommon ; Remaining RST handling is common
;**************************************************************************
; Common Interrupt handler
;**************************************************************************
_up_vectcommon::
; Create a register frame. SP points to top of frame + 4, pushes
; decrement the stack pointer. Already have
;
; Offset 8: Return PC is already on the stack
; Offset 7: AF (retaining flags)
;
; IRQ number is in A
push hl ; Offset 6: HL
ld hl, #(3*2) ; HL is the value of the stack pointer before
add hl, sp ; the interrupt occurred
push hl ; Offset 5: Stack pointer
push iy ; Offset 4: IY
push ix ; Offset 3: IX
push de ; Offset 2: DE
push bc ; Offset 1: BC
ld b, a ; Save the reset number in B
ld a, i ; Parity bit holds interrupt state
push af ; Offset 0: I with interrupt state in parity
di
; Call the interrupt decode logic. SP points to the beginning of the reg structure
ld hl, #0 ; Argument #2 is the beginning of the reg structure
add hl, sp ;
push hl ; Place argument #2 at the top of stack
push bc ; Argument #1 is the Reset number
inc sp ; (make byte sized)
call _up_doirq ; Decode the IRQ
; On return, HL points to the beginning of the reg structure to restore
; Note that (1) the arguments pushed on the stack are not popped, and (2) the
; original stack pointer is lost. In the normal case (no context switch),
; HL will contain the value of the SP before the arguments were pushed.
ld sp, hl ; Use the new stack pointer
; Restore registers. HL points to the beginning of the reg structure to restore
ex af, af' ; Select alternate AF
pop af ; Offset 0: AF' = I with interrupt state in carry
ex af, af' ; Restore original AF
pop bc ; Offset 1: BC
pop de ; Offset 2: DE
pop ix ; Offset 3: IX
pop iy ; Offset 4: IY
exx ; Use alternate BC/DE/HL
ld hl, #-2 ; Offset of SP to account for ret addr on stack
pop de ; Offset 5: HL' = Stack pointer after return
add hl, de ; HL = Stack pointer value before return
exx ; Restore original BC/DE/HL
pop hl ; Offset 6: HL
pop af ; Offset 7: AF
; Restore the stack pointer
exx ; Use alternate BC/DE/HL
ld sp, hl ; Set SP = saved stack pointer value before return
exx ; Restore original BC/DE/HL
; Restore interrupt state
ex af, af' ; Recover interrupt state
jp po, nointenable ; Odd parity, IFF2=0, means disabled
ex af, af' ; Restore AF (before enabling interrupts)
ei ; yes
reti
nointenable::
ex af, af' ; Restore AF
reti
nuttx/arch/z80/src/z180/z180_vectors.asm
+90
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;**************************************************************************
; arch/z80/src/z180/z180_vectors.asm
;
; Copyright (C) 2012 Gregory Nutt. All rights reserved.
; Author: Gregory Nutt <gnutt@nuttx.org>
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions
; are met:
;
; 1. Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; 2. Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in
; the documentation and/or other materials provided with the
; distribution.
; 3. Neither the name NuttX nor the names of its contributors may be
; used to endorse or promote products derived from this software
; without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
; FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
; COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
; OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
; ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;
;**************************************************************************
.title NuttX for the Z180
.module z180_vectors
;**************************************************************************
; Constants
;**************************************************************************
;**************************************************************************
; Global symbols used
;**************************************************************************
.globl _up_int1 ; Vector offset 0: External /INT1
.globl _up_int2 ; Vector offset 2: External /INT2
.globl _up_prt0 ; Vector offset 4: PRT channel 0
.globl _up_prt1 ; Vector offset 6: PRT channel 1
.globl _up_dma0 ; Vector offset 8: DMA channel 0
.globl _up_dma1 ; Vector offset 8: DMA channel 1
.globl _up_csio ; Vector offset 12: Clocked serial I/O
.globl _up_asci0 ; Vector offset 14: Async channel 0
.globl _up_asci1 ; Vector offset 16: Async channel 1
.globl _up_unused ; Vector offset 18: Unused
.globl _up_unused ; Vector offset 20: Unused
.globl _up_unused ; Vector offset 22: Unused
.globl _up_unused ; Vector offset 24: Unused
.globl _up_unused ; Vector offset 26: Unused
.globl _up_unused ; Vector offset 28: Unused
.globl _up_unused ; Vector offset 30: Unused
;**************************************************************************
; Interrupt Vector Table
;**************************************************************************
; The Vector Table is located at address 0x0040, between the RST vectors
; and the NMI vector
.area _VECTORS (ABS)
.org 0x0040
_up_vectors::
.dw up_int1 ; Vector offset 0: External /INT1
.dw up_int2 ; Vector offset 2: External /INT2
.dw up_prt0 ; Vector offset 4: PRT channel 0
.dw up_prt1 ; Vector offset 6: PRT channel 1
.dw up_dma0 ; Vector offset 8: DMA channel 0
.dw up_dma1 ; Vector offset 8: DMA channel 1
.dw up_csio ; Vector offset 12: Clocked serial I/O
.dw up_asci0 ; Vector offset 14: Async channel 0
.dw up_asci1 ; Vector offset 16: Async channel 1
.dw up_unused ; Vector offset 18: Unused
.dw up_unused ; Vector offset 20: Unused
.dw up_unused ; Vector offset 22: Unused
.dw up_unused ; Vector offset 24: Unused
.dw up_unused ; Vector offset 26: Unused
.dw up_unused ; Vector offset 28: Unused
.dw up_unused ; Vector offset 30: Unused