mirror of
https://gitee.com/mirrors_PX4/PX4-Autopilot.git
synced 2026-04-30 01:04:08 +08:00
Rework PWM LED Driver
This commit is contained in:
David Sidrane
Lorenz Meier
parent
da96144e80
commit
a36f392b58
@ -36,7 +36,6 @@ px4_add_module(
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COMPILE_FLAGS
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-Os
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SRCS
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drv_led_pwm.cpp
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rgbled_pwm.cpp
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DEPENDS
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platforms__common
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@ -39,6 +39,7 @@ px4_add_module(
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drv_io_timer.c
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drv_pwm_servo.c
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drv_input_capture.c
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drv_led_pwm.cpp
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DEPENDS
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platforms__common
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)
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@ -47,6 +47,10 @@ __BEGIN_DECLS
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/* configuration limits */
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#define MAX_IO_TIMERS 4
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#define MAX_TIMER_IO_CHANNELS 8
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#define MAX_LED_TIMERS 1
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#define MAX_TIMER_LED_CHANNELS 3
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#define IO_TIMER_ALL_MODES_CHANNELS 0
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typedef enum io_timer_channel_mode_t {
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@ -90,6 +94,10 @@ typedef void (*channel_handler_t)(void *context, const io_timers_t *timer, uint3
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/* supplied by board-specific code */
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__EXPORT extern const io_timers_t io_timers[MAX_IO_TIMERS];
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__EXPORT extern const timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS];
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__EXPORT extern const io_timers_t led_pwm_timers[MAX_LED_TIMERS];
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__EXPORT extern const timer_io_channels_t led_pwm_channels[MAX_TIMER_LED_CHANNELS];
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__EXPORT extern io_timer_channel_allocation_t allocations[IOTimerChanModeSize];
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__EXPORT int io_timer_handler0(int irq, void *context);
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__EXPORT int io_timer_handler1(int irq, void *context);
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@ -54,6 +54,7 @@
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#include <systemlib/perf_counter.h>
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#include <systemlib/err.h>
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#include <systemlib/systemlib.h>
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#include <systemlib/px4_macros.h>
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#include <drivers/drv_pwm_output.h>
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#include <drivers/stm32/drv_io_timer.h>
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@ -61,7 +62,7 @@
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#include <board_config.h>
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#if defined(BOARD_HAS_LED_PWM)
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#define REG(_tmr, _reg) (*(volatile uint32_t *)(led_pwm_timers[_tmr].base + _reg))
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#define rCR1(_tmr) REG(_tmr, STM32_GTIM_CR1_OFFSET)
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@ -96,103 +97,41 @@ void led_pwm_servo_arm(bool armed);
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unsigned led_pwm_timer_get_period(unsigned timer);
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const struct io_timers_t led_pwm_timers[3] = {
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{
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.base = STM32_TIM3_BASE,
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.clock_register = STM32_RCC_APB1ENR,
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.clock_bit = RCC_APB1ENR_TIM3EN,
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.clock_freq = STM32_APB1_TIM3_CLKIN,
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.vectorno = STM32_IRQ_TIM3,
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.first_channel_index = 4,
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.last_channel_index = 7,
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.handler = io_timer_handler0,
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},
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{
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.base = STM32_TIM3_BASE,
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.clock_register = STM32_RCC_APB1ENR,
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.clock_bit = RCC_APB1ENR_TIM3EN,
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.clock_freq = STM32_APB1_TIM3_CLKIN,
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.vectorno = STM32_IRQ_TIM3,
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.first_channel_index = 4,
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.last_channel_index = 7,
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.handler = io_timer_handler1,
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},
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{
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.base = STM32_TIM3_BASE,
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.clock_register = STM32_RCC_APB1ENR,
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.clock_bit = RCC_APB1ENR_TIM3EN,
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.clock_freq = STM32_APB1_TIM3_CLKIN,
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.vectorno = STM32_IRQ_TIM3,
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.first_channel_index = 4,
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.last_channel_index = 7,
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.handler = io_timer_handler2,
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}
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};
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#define LED_TIM3_CH3OUT (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN0)
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#define LED_TIM3_CH2OUT (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN7)
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#define LED_TIM3_CH4OUT (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN1)
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#define LED_TIM3_CH3IN (GPIO_INPUT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN0)
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#define LED_TIM3_CH2IN (GPIO_INPUT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN7)
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#define LED_TIM3_CH4IN (GPIO_INPUT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN1)
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const struct timer_io_channels_t led_pwm_channels[3] = {
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{
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.gpio_out = LED_TIM3_CH3OUT,
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.gpio_in = LED_TIM3_CH3IN,
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.timer_index = 0,
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.timer_channel = 3,
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.masks = GTIM_SR_CC3IF | GTIM_SR_CC3OF,
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.ccr_offset = STM32_GTIM_CCR3_OFFSET,
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},
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{
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.gpio_out = LED_TIM3_CH2OUT,
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.gpio_in = LED_TIM3_CH2IN,
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.timer_index = 1,
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.timer_channel = 2,
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.masks = GTIM_SR_CC2IF | GTIM_SR_CC2OF,
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.ccr_offset = STM32_GTIM_CCR2_OFFSET,
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},
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{
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.gpio_out = LED_TIM3_CH4OUT,
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.gpio_in = LED_TIM3_CH4IN,
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.timer_index = 2,
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.timer_channel = 4,
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.masks = GTIM_SR_CC4IF | GTIM_SR_CC4OF,
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.ccr_offset = STM32_GTIM_CCR4_OFFSET,
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}
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};
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static void
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led_pwm_timer_init(unsigned timer)
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{
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/* enable the timer clock before we try to talk to it */
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modifyreg32(led_pwm_timers[timer].clock_register, 0, led_pwm_timers[timer].clock_bit);
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/* valid Timer */
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/* disable and configure the timer */
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rCR1(timer) = 0;
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rCR2(timer) = 0;
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rSMCR(timer) = 0;
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rDIER(timer) = 0;
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rCCER(timer) = 0;
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rCCMR1(timer) = 0;
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rCCMR2(timer) = 0;
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rCCER(timer) = 0;
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rDCR(timer) = 0;
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if (led_pwm_timers[timer].base != 0) {
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if ((led_pwm_timers[timer].base == STM32_TIM1_BASE) || (led_pwm_timers[timer].base == STM32_TIM8_BASE)) {
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/* master output enable = on */
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rBDTR(timer) = ATIM_BDTR_MOE;
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/* enable the timer clock before we try to talk to it */
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modifyreg32(led_pwm_timers[timer].clock_register, 0, led_pwm_timers[timer].clock_bit);
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/* disable and configure the timer */
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rCR1(timer) = 0;
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rCR2(timer) = 0;
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rSMCR(timer) = 0;
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rDIER(timer) = 0;
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rCCER(timer) = 0;
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rCCMR1(timer) = 0;
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rCCMR2(timer) = 0;
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rCCER(timer) = 0;
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rDCR(timer) = 0;
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if ((led_pwm_timers[timer].base == STM32_TIM1_BASE) || (led_pwm_timers[timer].base == STM32_TIM8_BASE)) {
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/* master output enable = on */
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rBDTR(timer) = ATIM_BDTR_MOE;
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}
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/* configure the timer to free-run at 1MHz */
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rPSC(timer) = (led_pwm_timers[timer].clock_freq / 1000000) - 1;
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/* default to updating at 50Hz */
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led_pwm_timer_set_rate(timer, 50);
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/* note that the timer is left disabled - arming is performed separately */
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}
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/* configure the timer to free-run at 1MHz */
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rPSC(timer) = (led_pwm_timers[timer].clock_freq / 1000000) - 1;
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/* default to updating at 50Hz */
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led_pwm_timer_set_rate(timer, 50);
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/* note that the timer is left disabled - arming is performed separately */
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}
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unsigned
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led_pwm_timer_get_period(unsigned timer)
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@ -216,31 +155,28 @@ led_pwm_channel_init(unsigned channel)
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unsigned timer = led_pwm_channels[channel].timer_index;
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/* configure the GPIO first */
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px4_arch_configgpio(led_pwm_channels[channel].gpio_out);
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/* configure the channel */
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switch (led_pwm_channels[channel].timer_channel) {
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case 1:
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rCCMR1(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) | GTIM_CCMR1_OC1PE;
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//rCCR1(timer) = led_pwm_channels[channel].default_value;
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rCCER(timer) |= GTIM_CCER_CC1E;
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break;
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case 2:
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rCCMR1(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC2M_SHIFT) | GTIM_CCMR1_OC2PE;
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//rCCR2(timer) = led_pwm_channels[channel].default_value;
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rCCER(timer) |= GTIM_CCER_CC2E;
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break;
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case 3:
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rCCMR2(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR2_OC3M_SHIFT) | GTIM_CCMR2_OC3PE;
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//rCCR3(timer) = led_pwm_channels[channel].default_value;
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rCCER(timer) |= GTIM_CCER_CC3E;
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break;
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case 4:
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rCCMR2(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR2_OC4M_SHIFT) | GTIM_CCMR2_OC4PE;
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//rCCR4(timer) = led_pwm_channels[channel].default_value;
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rCCER(timer) |= GTIM_CCER_CC4E;
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break;
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}
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@ -249,7 +185,7 @@ led_pwm_channel_init(unsigned channel)
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int
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led_pwm_servo_set(unsigned channel, uint8_t cvalue)
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{
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if (channel >= 3) {
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if (channel >= arraySize(led_pwm_channels)) {
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return -1;
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}
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@ -263,7 +199,11 @@ led_pwm_servo_set(unsigned channel, uint8_t cvalue)
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unsigned period = led_pwm_timer_get_period(timer);
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#if defined(BOARD_LED_PWM_DRIVE_ACTIVE_LOW)
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unsigned value = period - (unsigned)cvalue * period / 255;
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#else
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unsigned value = (unsigned)cvalue * period / 255;
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#endif
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/* configure the channel */
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if (value > 0) {
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@ -336,12 +276,12 @@ int
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led_pwm_servo_init(void)
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{
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/* do basic timer initialisation first */
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for (unsigned i = 0; i < 3; i++) {
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for (unsigned i = 0; i < arraySize(led_pwm_timers); i++) {
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led_pwm_timer_init(i);
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}
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/* now init channels */
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for (unsigned i = 0; i < 3; i++) {
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for (unsigned i = 0; i < arraySize(led_pwm_channels); i++) {
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led_pwm_channel_init(i);
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}
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@ -359,7 +299,7 @@ void
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led_pwm_servo_arm(bool armed)
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{
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/* iterate timers and arm/disarm appropriately */
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for (unsigned i = 0; i < 3; i++) {
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for (unsigned i = 0; i < arraySize(led_pwm_timers); i++) {
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if (led_pwm_timers[i].base != 0) {
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if (armed) {
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/* force an update to preload all registers */
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@ -369,14 +309,10 @@ led_pwm_servo_arm(bool armed)
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rCR1(i) |= GTIM_CR1_CEN | GTIM_CR1_ARPE;
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} else {
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// XXX This leads to FMU PWM being still active
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// but uncontrollable. Just disable the timer
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// and risk a runt.
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///* on disarm, just stop auto-reload so we don't generate runts */
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//rCR1(i) &= ~GTIM_CR1_ARPE;
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rCR1(i) = 0;
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}
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}
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}
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}
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#endif // BOARD_HAS_LED_PWM
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