diff --git a/src/drivers/boards/auav-x21/board_config.h b/src/drivers/boards/auav-x21/board_config.h index e10976462b..a84b2b74e6 100644 --- a/src/drivers/boards/auav-x21/board_config.h +++ b/src/drivers/boards/auav-x21/board_config.h @@ -61,6 +61,8 @@ #define PX4IO_SERIAL_VECTOR STM32_IRQ_USART6 #define PX4IO_SERIAL_TX_DMAMAP DMAMAP_USART6_TX_2 #define PX4IO_SERIAL_RX_DMAMAP DMAMAP_USART6_RX_2 +#define PX4IO_SERIAL_RCC_REG STM32_RCC_APB2ENR +#define PX4IO_SERIAL_RCC_EN RCC_APB2ENR_USART6EN #define PX4IO_SERIAL_CLOCK STM32_PCLK2_FREQUENCY #define PX4IO_SERIAL_BITRATE 1500000 /* 1.5Mbps -> max rate for IO */ diff --git a/src/drivers/boards/px4fmu-v2/board_config.h b/src/drivers/boards/px4fmu-v2/board_config.h index 1b19f245af..dc6d244cb8 100644 --- a/src/drivers/boards/px4fmu-v2/board_config.h +++ b/src/drivers/boards/px4fmu-v2/board_config.h @@ -72,6 +72,8 @@ #define PX4IO_SERIAL_VECTOR STM32_IRQ_USART6 #define PX4IO_SERIAL_TX_DMAMAP DMAMAP_USART6_TX_2 #define PX4IO_SERIAL_RX_DMAMAP DMAMAP_USART6_RX_2 +#define PX4IO_SERIAL_RCC_REG STM32_RCC_APB2ENR +#define PX4IO_SERIAL_RCC_EN RCC_APB2ENR_USART6EN #define PX4IO_SERIAL_CLOCK STM32_PCLK2_FREQUENCY #define PX4IO_SERIAL_BITRATE 1500000 /* 1.5Mbps -> max rate for IO */ diff --git a/src/drivers/boards/px4fmu-v4pro/board_config.h b/src/drivers/boards/px4fmu-v4pro/board_config.h index f21f884d3f..1048feb9a1 100644 --- a/src/drivers/boards/px4fmu-v4pro/board_config.h +++ b/src/drivers/boards/px4fmu-v4pro/board_config.h @@ -60,6 +60,8 @@ #define PX4IO_SERIAL_VECTOR STM32_IRQ_USART6 #define PX4IO_SERIAL_TX_DMAMAP DMAMAP_USART6_TX_2 #define PX4IO_SERIAL_RX_DMAMAP DMAMAP_USART6_RX_2 +#define PX4IO_SERIAL_RCC_REG STM32_RCC_APB2ENR +#define PX4IO_SERIAL_RCC_EN RCC_APB2ENR_USART6EN #define PX4IO_SERIAL_CLOCK STM32_PCLK2_FREQUENCY #define PX4IO_SERIAL_BITRATE 1500000 /* 1.5Mbps -> max rate for IO */ diff --git a/src/drivers/px4io/CMakeLists.txt b/src/drivers/px4io/CMakeLists.txt index 3f91db3a6d..88ae47a5c3 100644 --- a/src/drivers/px4io/CMakeLists.txt +++ b/src/drivers/px4io/CMakeLists.txt @@ -39,6 +39,7 @@ px4_add_module( px4io.cpp px4io_uploader.cpp px4io_serial.cpp + px4io_serial_f4.cpp DEPENDS platforms__common ) diff --git a/src/drivers/px4io/px4io_driver.h b/src/drivers/px4io/px4io_driver.h index e1786c7fa3..2da2d0e05c 100644 --- a/src/drivers/px4io/px4io_driver.h +++ b/src/drivers/px4io/px4io_driver.h @@ -42,5 +42,7 @@ #include #ifdef PX4IO_SERIAL_BASE +#include + device::Device *PX4IO_serial_interface(); #endif diff --git a/src/drivers/px4io/px4io_serial.cpp b/src/drivers/px4io/px4io_serial.cpp index 25c5575fb0..6c60f3ff97 100644 --- a/src/drivers/px4io/px4io_serial.cpp +++ b/src/drivers/px4io/px4io_serial.cpp @@ -37,234 +37,53 @@ * Serial interface for PX4IO */ -/* XXX trim includes */ -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -/* XXX might be able to prune these */ -#include -#include -#include -#include - - -#if defined(CONFIG_ARCH_CHIP_STM32F7) -# include -# include -# define USART_BRR_MANT_SHIFT 0 -# define USART_BRR_FRAC_SHIFT 0 -# define USART_SR_TXE 0 -# define STM32_USART_DR_OFFSET 0 -# define USART_SR_ORE 0 -# define USART_SR_RXNE 0 -# define USART_SR_NE 0 -# define USART_SR_FE 0 -# define USART_SR_IDLE 0 -# define rSR REG(STM32_USART_ISR_OFFSET) -# define rDR REG(STM32_USART_RDR_OFFSET) -#endif - -#include - -#include -#include -#include - -#include - -#include - #include "px4io_driver.h" -#ifdef PX4IO_SERIAL_BASE +#include "px4io_serial.h" -/* serial register accessors */ -#define REG(_x) (*(volatile uint32_t *)(PX4IO_SERIAL_BASE + _x)) -# if !defined(rSR) -# define rSR REG(STM32_USART_SR_OFFSET) -#endif -# if !defined(rDR) -# define rDR REG(STM32_USART_DR_OFFSET) -#endif -#define rBRR REG(STM32_USART_BRR_OFFSET) -#define rCR1 REG(STM32_USART_CR1_OFFSET) -#define rCR2 REG(STM32_USART_CR2_OFFSET) -#define rCR3 REG(STM32_USART_CR3_OFFSET) -#define rGTPR REG(STM32_USART_GTPR_OFFSET) - -class PX4IO_serial : public device::Device -{ -public: - PX4IO_serial(); - virtual ~PX4IO_serial(); - - virtual int init(); - virtual int read(unsigned offset, void *data, unsigned count = 1); - virtual int write(unsigned address, void *data, unsigned count = 1); - virtual int ioctl(unsigned operation, unsigned &arg); - -private: - /* - * XXX tune this value - * - * At 1.5Mbps each register takes 13.3µs, and we always transfer a full packet. - * Packet overhead is 26µs for the four-byte header. - * - * 32 registers = 451µs - * - * Maybe we can just send smaller packets (e.g. 8 regs) and loop for larger (less common) - * transfers? Could cause issues with any regs expecting to be written atomically... - */ - static IOPacket _dma_buffer; // XXX static to ensure DMA-able memory - - DMA_HANDLE _tx_dma; - DMA_HANDLE _rx_dma; - - /** saved DMA status */ - static const unsigned _dma_status_inactive = 0x80000000; // low bits overlap DMA_STATUS_* values - static const unsigned _dma_status_waiting = 0x00000000; - volatile unsigned _rx_dma_status; - - /** bus-ownership lock */ - px4_sem_t _bus_semaphore; - - /** client-waiting lock/signal */ - px4_sem_t _completion_semaphore; - - /** - * Start the transaction with IO and wait for it to complete. - */ - int _wait_complete(); - - /** - * DMA completion handler. - */ - static void _dma_callback(DMA_HANDLE handle, uint8_t status, void *arg); - void _do_rx_dma_callback(unsigned status); - - /** - * Serial interrupt handler. - */ - static int _interrupt(int vector, void *context, void *arg); - void _do_interrupt(); - - /** - * Cancel any DMA in progress with an error. - */ - void _abort_dma(); - - /** - * Performance counters. - */ - perf_counter_t _pc_txns; - perf_counter_t _pc_dmasetup; - perf_counter_t _pc_retries; - perf_counter_t _pc_timeouts; - perf_counter_t _pc_crcerrs; - perf_counter_t _pc_dmaerrs; - perf_counter_t _pc_protoerrs; - perf_counter_t _pc_uerrs; - perf_counter_t _pc_idle; - perf_counter_t _pc_badidle; - - /* do not allow top copying this class */ - PX4IO_serial(PX4IO_serial &); - PX4IO_serial &operator = (const PX4IO_serial &); - -}; - -IOPacket PX4IO_serial::_dma_buffer; +IOPacket PX4IO_serial::_io_buffer; static PX4IO_serial *g_interface; device::Device *PX4IO_serial_interface() { - return new PX4IO_serial(); + return new PX4IO_INTERFACE_CLASS(); } PX4IO_serial::PX4IO_serial() : Device("PX4IO_serial"), - _tx_dma(nullptr), - _rx_dma(nullptr), - _rx_dma_status(_dma_status_inactive), - _bus_semaphore(SEM_INITIALIZER(0)), - _completion_semaphore(SEM_INITIALIZER(0)), _pc_txns(perf_alloc(PC_ELAPSED, "io_txns")), #if 0 - _pc_dmasetup(perf_alloc(PC_ELAPSED, "io_dmasetup ")), _pc_retries(perf_alloc(PC_COUNT, "io_retries ")), _pc_timeouts(perf_alloc(PC_COUNT, "io_timeouts ")), _pc_crcerrs(perf_alloc(PC_COUNT, "io_crcerrs ")), - _pc_dmaerrs(perf_alloc(PC_COUNT, "io_dmaerrs ")), _pc_protoerrs(perf_alloc(PC_COUNT, "io_protoerrs")), _pc_uerrs(perf_alloc(PC_COUNT, "io_uarterrs ")), _pc_idle(perf_alloc(PC_COUNT, "io_idle ")), - _pc_badidle(perf_alloc(PC_COUNT, "io_badidle ")) + _pc_badidle(perf_alloc(PC_COUNT, "io_badidle ")), #else - _pc_dmasetup(nullptr), _pc_retries(nullptr), _pc_timeouts(nullptr), _pc_crcerrs(nullptr), - _pc_dmaerrs(nullptr), _pc_protoerrs(nullptr), _pc_uerrs(nullptr), _pc_idle(nullptr), - _pc_badidle(nullptr) + _pc_badidle(nullptr), #endif + _bus_semaphore(SEM_INITIALIZER(0)) { g_interface = this; } PX4IO_serial::~PX4IO_serial() { - if (_tx_dma != nullptr) { - stm32_dmastop(_tx_dma); - stm32_dmafree(_tx_dma); - } - - if (_rx_dma != nullptr) { - stm32_dmastop(_rx_dma); - stm32_dmafree(_rx_dma); - } - - /* reset the UART */ - rCR1 = 0; - rCR2 = 0; - rCR3 = 0; - - /* detach our interrupt handler */ - up_disable_irq(PX4IO_SERIAL_VECTOR); - irq_detach(PX4IO_SERIAL_VECTOR); - - /* restore the GPIOs */ - px4_arch_unconfiggpio(PX4IO_SERIAL_TX_GPIO); - px4_arch_unconfiggpio(PX4IO_SERIAL_RX_GPIO); - - /* Disable APB clock for the USART peripheral */ - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_USART6EN, 0); - - /* and kill our semaphores */ - px4_sem_destroy(&_completion_semaphore); + /* kill our semaphores */ px4_sem_destroy(&_bus_semaphore); perf_free(_pc_txns); - perf_free(_pc_dmasetup); perf_free(_pc_retries); perf_free(_pc_timeouts); perf_free(_pc_crcerrs); - perf_free(_pc_dmaerrs); perf_free(_pc_protoerrs); perf_free(_pc_uerrs); perf_free(_pc_idle); @@ -278,129 +97,13 @@ PX4IO_serial::~PX4IO_serial() int PX4IO_serial::init() { - - /* allocate DMA */ - _tx_dma = stm32_dmachannel(PX4IO_SERIAL_TX_DMAMAP); - _rx_dma = stm32_dmachannel(PX4IO_SERIAL_RX_DMAMAP); - - if ((_tx_dma == nullptr) || (_rx_dma == nullptr)) { - return -1; - } - - - /* Enable the APB clock for the USART peripheral */ - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_USART6EN); - - /* configure pins for serial use */ - px4_arch_configgpio(PX4IO_SERIAL_TX_GPIO); - px4_arch_configgpio(PX4IO_SERIAL_RX_GPIO); - - /* reset & configure the UART */ - rCR1 = 0; - rCR2 = 0; - rCR3 = 0; - - /* eat any existing interrupt status */ - (void)rSR; - (void)rDR; - - - /* configure line speed */ - uint32_t usartdiv32 = PX4IO_SERIAL_CLOCK / (PX4IO_SERIAL_BITRATE / 2); - uint32_t mantissa = usartdiv32 >> 5; - uint32_t fraction = (usartdiv32 - (mantissa << 5) + 1) >> 1; - rBRR = (mantissa << USART_BRR_MANT_SHIFT) | (fraction << USART_BRR_FRAC_SHIFT); - - /* attach serial interrupt handler */ - irq_attach(PX4IO_SERIAL_VECTOR, _interrupt, NULL); - up_enable_irq(PX4IO_SERIAL_VECTOR); - - /* enable UART in DMA mode, enable error and line idle interrupts */ - rCR3 = USART_CR3_EIE; - - rCR1 = USART_CR1_RE | USART_CR1_TE | USART_CR1_UE | USART_CR1_IDLEIE; - /* create semaphores */ - px4_sem_init(&_completion_semaphore, 0, 0); - - /* _completion_semaphore use case is a signal */ - - px4_sem_setprotocol(&_completion_semaphore, SEM_PRIO_NONE); - + // in case the sub-class impl fails, the semaphore is cleaned up by destructor. px4_sem_init(&_bus_semaphore, 0, 1); - - /* XXX this could try talking to IO */ - return 0; } -int -PX4IO_serial::ioctl(unsigned operation, unsigned &arg) -{ - - switch (operation) { - - case 1: /* XXX magic number - test operation */ - switch (arg) { - case 0: - syslog(LOG_INFO, "test 0\n"); - - /* kill DMA, this is a PIO test */ - stm32_dmastop(_tx_dma); - stm32_dmastop(_rx_dma); - rCR3 &= ~(USART_CR3_DMAR | USART_CR3_DMAT); - - for (;;) { - while (!(rSR & USART_SR_TXE)) - ; - - rDR = 0x55; - } - - return 0; - - case 1: { - unsigned fails = 0; - - for (unsigned count = 0;; count++) { - uint16_t value = count & 0xffff; - - if (write((PX4IO_PAGE_TEST << 8) | PX4IO_P_TEST_LED, &value, 1) != 0) { - fails++; - } - - if (count >= 5000) { - syslog(LOG_INFO, "==== test 1 : %u failures ====\n", fails); - perf_print_counter(_pc_txns); - perf_print_counter(_pc_dmasetup); - perf_print_counter(_pc_retries); - perf_print_counter(_pc_timeouts); - perf_print_counter(_pc_crcerrs); - perf_print_counter(_pc_dmaerrs); - perf_print_counter(_pc_protoerrs); - perf_print_counter(_pc_uerrs); - perf_print_counter(_pc_idle); - perf_print_counter(_pc_badidle); - count = 0; - } - } - - return 0; - } - - case 2: - syslog(LOG_INFO, "test 2\n"); - return 0; - } - - default: - break; - } - - return -1; -} - int PX4IO_serial::write(unsigned address, void *data, unsigned count) { @@ -417,26 +120,26 @@ PX4IO_serial::write(unsigned address, void *data, unsigned count) int result; for (unsigned retries = 0; retries < 3; retries++) { - - _dma_buffer.count_code = count | PKT_CODE_WRITE; - _dma_buffer.page = page; - _dma_buffer.offset = offset; - memcpy((void *)&_dma_buffer.regs[0], (void *)values, (2 * count)); + _io_buffer.count_code = count | PKT_CODE_WRITE; + _io_buffer.page = page; + _io_buffer.offset = offset; + memcpy((void *)&_io_buffer.regs[0], (void *)values, (2 * count)); for (unsigned i = count; i < PKT_MAX_REGS; i++) { - _dma_buffer.regs[i] = 0x55aa; + _io_buffer.regs[i] = 0x55aa; } - /* XXX implement check byte */ + _io_buffer.crc = 0; + _io_buffer.crc = crc_packet(&_io_buffer); /* start the transaction and wait for it to complete */ - result = _wait_complete(); + result = _bus_exchange(&_io_buffer); /* successful transaction? */ if (result == OK) { /* check result in packet */ - if (PKT_CODE(_dma_buffer) == PKT_CODE_ERROR) { + if (PKT_CODE(_io_buffer) == PKT_CODE_ERROR) { /* IO didn't like it - no point retrying */ result = -EINVAL; @@ -475,18 +178,21 @@ PX4IO_serial::read(unsigned address, void *data, unsigned count) for (unsigned retries = 0; retries < 3; retries++) { - _dma_buffer.count_code = count | PKT_CODE_READ; - _dma_buffer.page = page; - _dma_buffer.offset = offset; + _io_buffer.count_code = count | PKT_CODE_READ; + _io_buffer.page = page; + _io_buffer.offset = offset; + + _io_buffer.crc = 0; + _io_buffer.crc = crc_packet(&_io_buffer); /* start the transaction and wait for it to complete */ - result = _wait_complete(); + result = _bus_exchange(&_io_buffer); /* successful transaction? */ if (result == OK) { /* check result in packet */ - if (PKT_CODE(_dma_buffer) == PKT_CODE_ERROR) { + if (PKT_CODE(_io_buffer) == PKT_CODE_ERROR) { /* IO didn't like it - no point retrying */ result = -EINVAL; @@ -494,7 +200,7 @@ PX4IO_serial::read(unsigned address, void *data, unsigned count) /* compare the received count with the expected count */ - } else if (PKT_COUNT(_dma_buffer) != count) { + } else if (PKT_COUNT(_io_buffer) != count) { /* IO returned the wrong number of registers - no point retrying */ result = -EIO; @@ -505,7 +211,7 @@ PX4IO_serial::read(unsigned address, void *data, unsigned count) } else { /* copy back the result */ - memcpy(values, &_dma_buffer.regs[0], (2 * count)); + memcpy(values, &_io_buffer.regs[0], (2 * count)); } break; @@ -522,243 +228,3 @@ PX4IO_serial::read(unsigned address, void *data, unsigned count) return result; } - -int -PX4IO_serial::_wait_complete() -{ - /* clear any lingering error status */ - (void)rSR; - (void)rDR; - - /* start RX DMA */ - perf_begin(_pc_txns); - perf_begin(_pc_dmasetup); - - /* DMA setup time ~3µs */ - _rx_dma_status = _dma_status_waiting; - - /* - * Note that we enable circular buffer mode as a workaround for - * there being no API to disable the DMA FIFO. We need direct mode - * because otherwise when the line idle interrupt fires there - * will be packet bytes still in the DMA FIFO, and we will assume - * that the idle was spurious. - * - * XXX this should be fixed with a NuttX change. - */ - stm32_dmasetup( - _rx_dma, - PX4IO_SERIAL_BASE + STM32_USART_DR_OFFSET, - reinterpret_cast(&_dma_buffer), - sizeof(_dma_buffer), - DMA_SCR_CIRC | /* XXX see note above */ - DMA_SCR_DIR_P2M | - DMA_SCR_MINC | - DMA_SCR_PSIZE_8BITS | - DMA_SCR_MSIZE_8BITS | - DMA_SCR_PBURST_SINGLE | - DMA_SCR_MBURST_SINGLE); - stm32_dmastart(_rx_dma, _dma_callback, this, false); - rCR3 |= USART_CR3_DMAR; - - /* start TX DMA - no callback if we also expect a reply */ - /* DMA setup time ~3µs */ - _dma_buffer.crc = 0; - _dma_buffer.crc = crc_packet(&_dma_buffer); - stm32_dmasetup( - _tx_dma, - PX4IO_SERIAL_BASE + STM32_USART_DR_OFFSET, - reinterpret_cast(&_dma_buffer), - PKT_SIZE(_dma_buffer), - DMA_SCR_DIR_M2P | - DMA_SCR_MINC | - DMA_SCR_PSIZE_8BITS | - DMA_SCR_MSIZE_8BITS | - DMA_SCR_PBURST_SINGLE | - DMA_SCR_MBURST_SINGLE); - stm32_dmastart(_tx_dma, nullptr, nullptr, false); - //rCR1 &= ~USART_CR1_TE; - //rCR1 |= USART_CR1_TE; - rCR3 |= USART_CR3_DMAT; - - perf_end(_pc_dmasetup); - - /* compute the deadline for a 10ms timeout */ - struct timespec abstime; - clock_gettime(CLOCK_REALTIME, &abstime); - abstime.tv_nsec += 10 * 1000 * 1000; - - if (abstime.tv_nsec >= 1000 * 1000 * 1000) { - abstime.tv_sec++; - abstime.tv_nsec -= 1000 * 1000 * 1000; - } - - /* wait for the transaction to complete - 64 bytes @ 1.5Mbps ~426µs */ - int ret; - - for (;;) { - ret = sem_timedwait(&_completion_semaphore, &abstime); - - if (ret == OK) { - /* check for DMA errors */ - if (_rx_dma_status & DMA_STATUS_TEIF) { - perf_count(_pc_dmaerrs); - ret = -EIO; - break; - } - - /* check packet CRC - corrupt packet errors mean IO receive CRC error */ - uint8_t crc = _dma_buffer.crc; - _dma_buffer.crc = 0; - - if ((crc != crc_packet(&_dma_buffer)) | (PKT_CODE(_dma_buffer) == PKT_CODE_CORRUPT)) { - perf_count(_pc_crcerrs); - ret = -EIO; - break; - } - - /* successful txn (may still be reporting an error) */ - break; - } - - if (errno == ETIMEDOUT) { - /* something has broken - clear out any partial DMA state and reconfigure */ - _abort_dma(); - perf_count(_pc_timeouts); - perf_cancel(_pc_txns); /* don't count this as a transaction */ - break; - } - - /* we might? see this for EINTR */ - syslog(LOG_ERR, "unexpected ret %d/%d\n", ret, errno); - } - - /* reset DMA status */ - _rx_dma_status = _dma_status_inactive; - - /* update counters */ - perf_end(_pc_txns); - - return ret; -} - -void -PX4IO_serial::_dma_callback(DMA_HANDLE handle, uint8_t status, void *arg) -{ - if (arg != nullptr) { - PX4IO_serial *ps = reinterpret_cast(arg); - - ps->_do_rx_dma_callback(status); - } -} - -void -PX4IO_serial::_do_rx_dma_callback(unsigned status) -{ - /* on completion of a reply, wake the waiter */ - if (_rx_dma_status == _dma_status_waiting) { - - /* check for packet overrun - this will occur after DMA completes */ - uint32_t sr = rSR; - - if (sr & (USART_SR_ORE | USART_SR_RXNE)) { - (void)rDR; - status = DMA_STATUS_TEIF; - } - - /* save RX status */ - _rx_dma_status = status; - - /* disable UART DMA */ - rCR3 &= ~(USART_CR3_DMAT | USART_CR3_DMAR); - - /* complete now */ - px4_sem_post(&_completion_semaphore); - } -} - -int -PX4IO_serial::_interrupt(int irq, void *context, void *arg) -{ - if (g_interface != nullptr) { - g_interface->_do_interrupt(); - } - - return 0; -} - -void -PX4IO_serial::_do_interrupt() -{ - uint32_t sr = rSR; /* get UART status register */ - (void)rDR; /* read DR to clear status */ - - if (sr & (USART_SR_ORE | /* overrun error - packet was too big for DMA or DMA was too slow */ - USART_SR_NE | /* noise error - we have lost a byte due to noise */ - USART_SR_FE)) { /* framing error - start/stop bit lost or line break */ - - /* - * If we are in the process of listening for something, these are all fatal; - * abort the DMA with an error. - */ - if (_rx_dma_status == _dma_status_waiting) { - _abort_dma(); - - perf_count(_pc_uerrs); - /* complete DMA as though in error */ - _do_rx_dma_callback(DMA_STATUS_TEIF); - - return; - } - - /* XXX we might want to use FE / line break as an out-of-band handshake ... handle it here */ - - /* don't attempt to handle IDLE if it's set - things went bad */ - return; - } - - if (sr & USART_SR_IDLE) { - - /* if there is DMA reception going on, this is a short packet */ - if (_rx_dma_status == _dma_status_waiting) { - - /* verify that the received packet is complete */ - size_t length = sizeof(_dma_buffer) - stm32_dmaresidual(_rx_dma); - - if ((length < 1) || (length < PKT_SIZE(_dma_buffer))) { - perf_count(_pc_badidle); - - /* stop the receive DMA */ - stm32_dmastop(_rx_dma); - - /* complete the short reception */ - _do_rx_dma_callback(DMA_STATUS_TEIF); - return; - } - - perf_count(_pc_idle); - - /* stop the receive DMA */ - stm32_dmastop(_rx_dma); - - /* complete the short reception */ - _do_rx_dma_callback(DMA_STATUS_TCIF); - } - } -} - -void -PX4IO_serial::_abort_dma() -{ - /* disable UART DMA */ - rCR3 &= ~(USART_CR3_DMAT | USART_CR3_DMAR); - (void)rSR; - (void)rDR; - (void)rDR; - - /* stop DMA */ - stm32_dmastop(_tx_dma); - stm32_dmastop(_rx_dma); -} - -#endif /* PX4IO_SERIAL_BASE */ diff --git a/src/drivers/px4io/px4io_serial.h b/src/drivers/px4io/px4io_serial.h new file mode 100644 index 0000000000..35edf54d76 --- /dev/null +++ b/src/drivers/px4io/px4io_serial.h @@ -0,0 +1,197 @@ +/**************************************************************************** + * + * Copyright (c) 2015 PX4 Development Team. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name PX4 nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/** + * @file px4io_driver.h + * + * Interface for PX4IO + */ + +#pragma once + +/* XXX trim includes */ +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* XXX might be able to prune these */ +#include +#include +#include +#include + +#include + +#include + +#include + +#include +#include +#include + +#include + +class PX4IO_serial : public device::Device +{ +public: + PX4IO_serial(); + virtual ~PX4IO_serial(); + + virtual int init(); + virtual int read(unsigned offset, void *data, unsigned count = 1); + virtual int write(unsigned address, void *data, unsigned count = 1); + +protected: + /** + * Start the transaction with IO and wait for it to complete. + */ + virtual int _bus_exchange(IOPacket *_packet) = 0; + + /** + * Performance counters. + */ + perf_counter_t _pc_txns; + perf_counter_t _pc_retries; + perf_counter_t _pc_timeouts; + perf_counter_t _pc_crcerrs; + perf_counter_t _pc_protoerrs; + perf_counter_t _pc_uerrs; + perf_counter_t _pc_idle; + perf_counter_t _pc_badidle; +private: + /* + * XXX tune this value + * + * At 1.5Mbps each register takes 13.3µs, and we always transfer a full packet. + * Packet overhead is 26µs for the four-byte header. + * + * 32 registers = 451µs + * + * Maybe we can just send smaller packets (e.g. 8 regs) and loop for larger (less common) + * transfers? Could cause issues with any regs expecting to be written atomically... + */ + static IOPacket _io_buffer; // XXX static to ensure DMA-able memory + + /** bus-ownership lock */ + px4_sem_t _bus_semaphore; + + /* do not allow top copying this class */ + PX4IO_serial(PX4IO_serial &); + PX4IO_serial &operator = (const PX4IO_serial &); +}; + +#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F4XXX) +/** XXX use F4 implementation for F1 as well. **/ + +#define PX4IO_INTERFACE_CLASS PX4IO_serial_f4 +#define PX4IO_INTERFACE_F4 + +class PX4IO_serial_f4 : public PX4IO_serial +{ +public: + PX4IO_serial_f4(); + ~PX4IO_serial_f4(); + + virtual int init(); + virtual int ioctl(unsigned operation, unsigned &arg); + +protected: + /** + * Start the transaction with IO and wait for it to complete. + */ + int _bus_exchange(IOPacket *_packet); + +private: + DMA_HANDLE _tx_dma; + DMA_HANDLE _rx_dma; + + IOPacket *_current_packet; + + /** saved DMA status */ + static const unsigned _dma_status_inactive = 0x80000000; // low bits overlap DMA_STATUS_* values + static const unsigned _dma_status_waiting = 0x00000000; + volatile unsigned _rx_dma_status; + + /** client-waiting lock/signal */ + px4_sem_t _completion_semaphore; + + /** + * DMA completion handler. + */ + static void _dma_callback(DMA_HANDLE handle, uint8_t status, void *arg); + void _do_rx_dma_callback(unsigned status); + + /** + * Serial interrupt handler. + */ + static int _interrupt(int vector, void *context, void *arg); + void _do_interrupt(); + + /** + * Cancel any DMA in progress with an error. + */ + void _abort_dma(); + + /** + * Performance counters. + */ + perf_counter_t _pc_dmasetup; + perf_counter_t _pc_dmaerrs; + + /* do not allow top copying this class */ + PX4IO_serial_f4(PX4IO_serial_f4 &); + PX4IO_serial_f4 &operator = (const PX4IO_serial_f4 &); +}; + +#elif defined(CONFIG_ARCH_CHIP_STM32F7) + +#define PX4IO_INTERFACE_CLASS PX4IO_serial_f7 +#define PX4IO_INTERFACE_F7 + + + +#else +#error "Interface not implemented for this chip" +#endif diff --git a/src/drivers/px4io/px4io_serial_f4.cpp b/src/drivers/px4io/px4io_serial_f4.cpp new file mode 100644 index 0000000000..4d01510c56 --- /dev/null +++ b/src/drivers/px4io/px4io_serial_f4.cpp @@ -0,0 +1,472 @@ +/**************************************************************************** + * + * Copyright (c) 2013-2015 PX4 Development Team. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name PX4 nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/** + * @file px4io_serial_f4.cpp + * + * Serial interface for PX4IO on STM32F4 + */ + +#include "px4io_serial.h" + +#ifdef PX4IO_INTERFACE_F4 + +/* serial register accessors */ +#define REG(_x) (*(volatile uint32_t *)(PX4IO_SERIAL_BASE + _x)) +#define rSR REG(STM32_USART_SR_OFFSET) +#define rDR REG(STM32_USART_DR_OFFSET) +#define rBRR REG(STM32_USART_BRR_OFFSET) +#define rCR1 REG(STM32_USART_CR1_OFFSET) +#define rCR2 REG(STM32_USART_CR2_OFFSET) +#define rCR3 REG(STM32_USART_CR3_OFFSET) +#define rGTPR REG(STM32_USART_GTPR_OFFSET) + +PX4IO_serial_f4::PX4IO_serial_f4() : + _tx_dma(nullptr), + _rx_dma(nullptr), + _current_packet(nullptr), + _rx_dma_status(_dma_status_inactive), + _completion_semaphore(SEM_INITIALIZER(0)), +#if 0 + _pc_dmasetup(perf_alloc(PC_ELAPSED, "io_dmasetup ")), + _pc_dmaerrs(perf_alloc(PC_COUNT, "io_dmaerrs ")) +#else + _pc_dmasetup(nullptr), + _pc_dmaerrs(nullptr) +#endif +{ +} + +PX4IO_serial_f4::~PX4IO_serial_f4() +{ + if (_tx_dma != nullptr) { + stm32_dmastop(_tx_dma); + stm32_dmafree(_tx_dma); + } + + if (_rx_dma != nullptr) { + stm32_dmastop(_rx_dma); + stm32_dmafree(_rx_dma); + } + + /* reset the UART */ + rCR1 = 0; + rCR2 = 0; + rCR3 = 0; + + /* detach our interrupt handler */ + up_disable_irq(PX4IO_SERIAL_VECTOR); + irq_detach(PX4IO_SERIAL_VECTOR); + + /* restore the GPIOs */ + px4_arch_unconfiggpio(PX4IO_SERIAL_TX_GPIO); + px4_arch_unconfiggpio(PX4IO_SERIAL_RX_GPIO); + + /* Disable APB clock for the USART peripheral */ + modifyreg32(PX4IO_SERIAL_RCC_REG, PX4IO_SERIAL_RCC_EN, 0); + + /* and kill our semaphores */ + px4_sem_destroy(&_completion_semaphore); + + perf_free(_pc_dmasetup); + perf_free(_pc_dmaerrs); +} + +int +PX4IO_serial_f4::init() +{ + /* initialize base implementation */ + int r; + + if ((r = PX4IO_serial::init()) != 0) { + return r; + } + + /* allocate DMA */ + _tx_dma = stm32_dmachannel(PX4IO_SERIAL_TX_DMAMAP); + _rx_dma = stm32_dmachannel(PX4IO_SERIAL_RX_DMAMAP); + + if ((_tx_dma == nullptr) || (_rx_dma == nullptr)) { + return -1; + } + + /* Enable the APB clock for the USART peripheral */ + modifyreg32(PX4IO_SERIAL_RCC_REG, 0, PX4IO_SERIAL_RCC_EN); + + /* configure pins for serial use */ + px4_arch_configgpio(PX4IO_SERIAL_TX_GPIO); + px4_arch_configgpio(PX4IO_SERIAL_RX_GPIO); + + /* reset & configure the UART */ + rCR1 = 0; + rCR2 = 0; + rCR3 = 0; + + /* eat any existing interrupt status */ + (void)rSR; + (void)rDR; + + + /* configure line speed */ + uint32_t usartdiv32 = PX4IO_SERIAL_CLOCK / (PX4IO_SERIAL_BITRATE / 2); + uint32_t mantissa = usartdiv32 >> 5; + uint32_t fraction = (usartdiv32 - (mantissa << 5) + 1) >> 1; + rBRR = (mantissa << USART_BRR_MANT_SHIFT) | (fraction << USART_BRR_FRAC_SHIFT); + + /* attach serial interrupt handler */ + irq_attach(PX4IO_SERIAL_VECTOR, _interrupt, this); + up_enable_irq(PX4IO_SERIAL_VECTOR); + + /* enable UART in DMA mode, enable error and line idle interrupts */ + rCR3 = USART_CR3_EIE; + + rCR1 = USART_CR1_RE | USART_CR1_TE | USART_CR1_UE | USART_CR1_IDLEIE; + + /* create semaphores */ + px4_sem_init(&_completion_semaphore, 0, 0); + + /* _completion_semaphore use case is a signal */ + + px4_sem_setprotocol(&_completion_semaphore, SEM_PRIO_NONE); + + /* XXX this could try talking to IO */ + + return 0; +} + +int +PX4IO_serial_f4::ioctl(unsigned operation, unsigned &arg) +{ + switch (operation) { + + case 1: /* XXX magic number - test operation */ + switch (arg) { + case 0: + syslog(LOG_INFO, "test 0\n"); + + /* kill DMA, this is a PIO test */ + stm32_dmastop(_tx_dma); + stm32_dmastop(_rx_dma); + rCR3 &= ~(USART_CR3_DMAR | USART_CR3_DMAT); + + for (;;) { + while (!(rSR & USART_SR_TXE)) + ; + + rDR = 0x55; + } + + return 0; + + case 1: { + unsigned fails = 0; + + for (unsigned count = 0;; count++) { + uint16_t value = count & 0xffff; + + if (write((PX4IO_PAGE_TEST << 8) | PX4IO_P_TEST_LED, &value, 1) != 0) { + fails++; + } + + if (count >= 5000) { + syslog(LOG_INFO, "==== test 1 : %u failures ====\n", fails); + perf_print_counter(_pc_txns); + perf_print_counter(_pc_dmasetup); + perf_print_counter(_pc_retries); + perf_print_counter(_pc_timeouts); + perf_print_counter(_pc_crcerrs); + perf_print_counter(_pc_dmaerrs); + perf_print_counter(_pc_protoerrs); + perf_print_counter(_pc_uerrs); + perf_print_counter(_pc_idle); + perf_print_counter(_pc_badidle); + count = 0; + } + } + + return 0; + } + + case 2: + syslog(LOG_INFO, "test 2\n"); + return 0; + } + + default: + break; + } + + return -1; +} + +int +PX4IO_serial_f4::_bus_exchange(IOPacket *_packet) +{ + _current_packet = _packet; + + /* clear any lingering error status */ + (void)rSR; + (void)rDR; + + /* start RX DMA */ + perf_begin(_pc_txns); + perf_begin(_pc_dmasetup); + + /* DMA setup time ~3µs */ + _rx_dma_status = _dma_status_waiting; + + /* + * Note that we enable circular buffer mode as a workaround for + * there being no API to disable the DMA FIFO. We need direct mode + * because otherwise when the line idle interrupt fires there + * will be packet bytes still in the DMA FIFO, and we will assume + * that the idle was spurious. + * + * XXX this should be fixed with a NuttX change. + */ + stm32_dmasetup( + _rx_dma, + PX4IO_SERIAL_BASE + STM32_USART_DR_OFFSET, + reinterpret_cast(_current_packet), + sizeof(*_current_packet), + DMA_SCR_CIRC | /* XXX see note above */ + DMA_SCR_DIR_P2M | + DMA_SCR_MINC | + DMA_SCR_PSIZE_8BITS | + DMA_SCR_MSIZE_8BITS | + DMA_SCR_PBURST_SINGLE | + DMA_SCR_MBURST_SINGLE); + stm32_dmastart(_rx_dma, _dma_callback, this, false); + rCR3 |= USART_CR3_DMAR; + + /* start TX DMA - no callback if we also expect a reply */ + /* DMA setup time ~3µs */ + stm32_dmasetup( + _tx_dma, + PX4IO_SERIAL_BASE + STM32_USART_DR_OFFSET, + reinterpret_cast(_current_packet), + PKT_SIZE(*_current_packet), + DMA_SCR_DIR_M2P | + DMA_SCR_MINC | + DMA_SCR_PSIZE_8BITS | + DMA_SCR_MSIZE_8BITS | + DMA_SCR_PBURST_SINGLE | + DMA_SCR_MBURST_SINGLE); + stm32_dmastart(_tx_dma, nullptr, nullptr, false); + //rCR1 &= ~USART_CR1_TE; + //rCR1 |= USART_CR1_TE; + rCR3 |= USART_CR3_DMAT; + + perf_end(_pc_dmasetup); + + /* compute the deadline for a 10ms timeout */ + struct timespec abstime; + clock_gettime(CLOCK_REALTIME, &abstime); + abstime.tv_nsec += 10 * 1000 * 1000; + + if (abstime.tv_nsec >= 1000 * 1000 * 1000) { + abstime.tv_sec++; + abstime.tv_nsec -= 1000 * 1000 * 1000; + } + + /* wait for the transaction to complete - 64 bytes @ 1.5Mbps ~426µs */ + int ret; + + for (;;) { + ret = sem_timedwait(&_completion_semaphore, &abstime); + + if (ret == OK) { + /* check for DMA errors */ + if (_rx_dma_status & DMA_STATUS_TEIF) { + perf_count(_pc_dmaerrs); + ret = -EIO; + break; + } + + /* check packet CRC - corrupt packet errors mean IO receive CRC error */ + uint8_t crc = _current_packet->crc; + _current_packet->crc = 0; + + if ((crc != crc_packet(_current_packet)) || (PKT_CODE(*_current_packet) == PKT_CODE_CORRUPT)) { + perf_count(_pc_crcerrs); + ret = -EIO; + break; + } + + /* successful txn (may still be reporting an error) */ + break; + } + + if (errno == ETIMEDOUT) { + /* something has broken - clear out any partial DMA state and reconfigure */ + _abort_dma(); + perf_count(_pc_timeouts); + perf_cancel(_pc_txns); /* don't count this as a transaction */ + break; + } + + /* we might? see this for EINTR */ + syslog(LOG_ERR, "unexpected ret %d/%d\n", ret, errno); + } + + /* reset DMA status */ + _rx_dma_status = _dma_status_inactive; + + /* update counters */ + perf_end(_pc_txns); + + return ret; +} + +void +PX4IO_serial_f4::_dma_callback(DMA_HANDLE handle, uint8_t status, void *arg) +{ + if (arg != nullptr) { + PX4IO_serial_f4 *ps = reinterpret_cast(arg); + + ps->_do_rx_dma_callback(status); + } +} + +void +PX4IO_serial_f4::_do_rx_dma_callback(unsigned status) +{ + /* on completion of a reply, wake the waiter */ + if (_rx_dma_status == _dma_status_waiting) { + + /* check for packet overrun - this will occur after DMA completes */ + uint32_t sr = rSR; + + if (sr & (USART_SR_ORE | USART_SR_RXNE)) { + (void)rDR; + status = DMA_STATUS_TEIF; + } + + /* save RX status */ + _rx_dma_status = status; + + /* disable UART DMA */ + rCR3 &= ~(USART_CR3_DMAT | USART_CR3_DMAR); + + /* complete now */ + px4_sem_post(&_completion_semaphore); + } +} + +int +PX4IO_serial_f4::_interrupt(int irq, void *context, void *arg) +{ + if (arg != nullptr) { + PX4IO_serial_f4 *instance = reinterpret_cast(arg); + + instance->_do_interrupt(); + } + + return 0; +} + +void +PX4IO_serial_f4::_do_interrupt() +{ + uint32_t sr = rSR; /* get UART status register */ + (void)rDR; /* read DR to clear status */ + + if (sr & (USART_SR_ORE | /* overrun error - packet was too big for DMA or DMA was too slow */ + USART_SR_NE | /* noise error - we have lost a byte due to noise */ + USART_SR_FE)) { /* framing error - start/stop bit lost or line break */ + + /* + * If we are in the process of listening for something, these are all fatal; + * abort the DMA with an error. + */ + if (_rx_dma_status == _dma_status_waiting) { + _abort_dma(); + + perf_count(_pc_uerrs); + /* complete DMA as though in error */ + _do_rx_dma_callback(DMA_STATUS_TEIF); + + return; + } + + /* XXX we might want to use FE / line break as an out-of-band handshake ... handle it here */ + + /* don't attempt to handle IDLE if it's set - things went bad */ + return; + } + + if (sr & USART_SR_IDLE) { + + /* if there is DMA reception going on, this is a short packet */ + if (_rx_dma_status == _dma_status_waiting) { + + /* verify that the received packet is complete */ + size_t length = sizeof(*_current_packet) - stm32_dmaresidual(_rx_dma); + + if ((length < 1) || (length < PKT_SIZE(*_current_packet))) { + perf_count(_pc_badidle); + + /* stop the receive DMA */ + stm32_dmastop(_rx_dma); + + /* complete the short reception */ + _do_rx_dma_callback(DMA_STATUS_TEIF); + return; + } + + perf_count(_pc_idle); + + /* stop the receive DMA */ + stm32_dmastop(_rx_dma); + + /* complete the short reception */ + _do_rx_dma_callback(DMA_STATUS_TCIF); + } + } +} + +void +PX4IO_serial_f4::_abort_dma() +{ + /* disable UART DMA */ + rCR3 &= ~(USART_CR3_DMAT | USART_CR3_DMAR); + (void)rSR; + (void)rDR; + (void)rDR; + + /* stop DMA */ + stm32_dmastop(_tx_dma); + stm32_dmastop(_rx_dma); +} + +#endif /* PX4IO_INTERFACE_F4 */