fly316/PX4-Autopilot
7
0
Fork 0
mirror of https://gitee.com/mirrors_PX4/PX4-Autopilot.git synced 2026-11-03 05:21:35 +08:00
Code Issues Packages Projects Releases Wiki Activity

mpu6000: add gyro/accel self test bits to checked registers

Browse Source
This commit is contained in:
Daniel Agar
2021-11-04 21:22:14 -04:00
parent bffcdd6fad
commit 8fbb241c2e
2 changed files with 10 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/drivers/imu/invensense/mpu6000/InvenSense_MPU6000_registers.hpp
+8
View File
@@ -94,6 +94,10 @@ enum CONFIG_BIT : uint8_t {
// GYRO_CONFIG // GYRO_CONFIG
enum GYRO_CONFIG_BIT : uint8_t { enum GYRO_CONFIG_BIT : uint8_t {
XG_ST = Bit7,
YG_ST = Bit6,
ZG_ST = Bit5,
// FS_SEL [4:3] // FS_SEL [4:3]
FS_SEL_250_DPS = 0, // 0b00000 FS_SEL_250_DPS = 0, // 0b00000
FS_SEL_500_DPS = Bit3, // 0b01000 FS_SEL_500_DPS = Bit3, // 0b01000
@@ -103,6 +107,10 @@ enum GYRO_CONFIG_BIT : uint8_t {
// ACCEL_CONFIG // ACCEL_CONFIG
enum ACCEL_CONFIG_BIT : uint8_t { enum ACCEL_CONFIG_BIT : uint8_t {
XA_ST = Bit7,
YA_ST = Bit6,
ZA_ST = Bit5,
// AFS_SEL [4:3] // AFS_SEL [4:3]
AFS_SEL_2G = 0, // 0b00000 AFS_SEL_2G = 0, // 0b00000
AFS_SEL_4G = Bit3, // 0b01000 AFS_SEL_4G = Bit3, // 0b01000
src/drivers/imu/invensense/mpu6000/MPU6000.hpp
+2 -2
View File
@@ -158,8 +158,8 @@ private:
static constexpr uint8_t size_register_cfg{7}; static constexpr uint8_t size_register_cfg{7};
register_config_t _register_cfg[size_register_cfg] { register_config_t _register_cfg[size_register_cfg] {
// Register | Set bits, Clear bits // Register | Set bits, Clear bits
{ Register::GYRO_CONFIG, GYRO_CONFIG_BIT::FS_SEL_2000_DPS, 0 }, { Register::GYRO_CONFIG, GYRO_CONFIG_BIT::FS_SEL_2000_DPS, GYRO_CONFIG_BIT::XG_ST | GYRO_CONFIG_BIT::YG_ST | GYRO_CONFIG_BIT::ZG_ST },
{ Register::ACCEL_CONFIG, ACCEL_CONFIG_BIT::AFS_SEL_16G, 0 }, { Register::ACCEL_CONFIG, ACCEL_CONFIG_BIT::AFS_SEL_16G, ACCEL_CONFIG_BIT::XA_ST | ACCEL_CONFIG_BIT::YA_ST | ACCEL_CONFIG_BIT::ZA_ST },
{ Register::FIFO_EN, FIFO_EN_BIT::XG_FIFO_EN | FIFO_EN_BIT::YG_FIFO_EN | FIFO_EN_BIT::ZG_FIFO_EN | FIFO_EN_BIT::ACCEL_FIFO_EN, FIFO_EN_BIT::TEMP_FIFO_EN }, { Register::FIFO_EN, FIFO_EN_BIT::XG_FIFO_EN | FIFO_EN_BIT::YG_FIFO_EN | FIFO_EN_BIT::ZG_FIFO_EN | FIFO_EN_BIT::ACCEL_FIFO_EN, FIFO_EN_BIT::TEMP_FIFO_EN },
{ Register::INT_PIN_CFG, INT_PIN_CFG_BIT::INT_LEVEL, 0 }, { Register::INT_PIN_CFG, INT_PIN_CFG_BIT::INT_LEVEL, 0 },
{ Register::INT_ENABLE, INT_ENABLE_BIT::DATA_RDY_INT_EN, 0 }, { Register::INT_ENABLE, INT_ENABLE_BIT::DATA_RDY_INT_EN, 0 },