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v6x-rt: move romapi to platform

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This commit is contained in:
Peter van der Perk
2024-01-04 05:12:34 -05:00
committed by David Sidrane
parent 6be8cbe439
commit 8ba18a78af
11 changed files with 134 additions and 21 deletions
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platforms/nuttx/src/bootloader/nxp/imxrt_common/main.c
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@@ -7,8 +7,8 @@
#include <px4_defines.h>
#include "hw_config.h"
#include "imxrt_flexspi_nor_flash.h"
#include "imxrt_romapi.h"
#include <px4_arch/imxrt_flexspi_nor_flash.h>
#include <px4_arch/imxrt_romapi.h>
#include <hardware/rt117x/imxrt117x_ocotp.h>
#include <hardware/rt117x/imxrt117x_anadig.h>
#include <hardware/rt117x/imxrt117x_snvs.h>
platforms/nuttx/src/px4/nxp/imxrt/include/px4_arch/imxrt_flexspi_nor_flash.h
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@@ -0,0 +1,352 @@
/****************************************************************************
* platforms/nuttx/src/px4/nxp/imrt/include/px4_arch/imxrt_flexspi_nor_flash.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __PX4_ARCH_IMXRT_FLEXSPI_NOR_FLASH_H
#define __PX4_ARCH_IMXRT_FLEXSPI_NOR_FLASH_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
#include <stdbool.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief XIP_BOARD driver version 2.0.0. */
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/* FLEXSPI memory config block related defintions */
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
#define FLEXSPI_CFG_BLK_SIZE (512)
/* FLEXSPI Feature related definitions */
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
/* Lookup table related defintions */
#define CMD_INDEX_READ 0
#define CMD_INDEX_READSTATUS 1
#define CMD_INDEX_WRITEENABLE 2
#define CMD_INDEX_WRITE 4
#define CMD_LUT_SEQ_IDX_READ 0
#define CMD_LUT_SEQ_IDX_READSTATUS 1
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
#define CMD_LUT_SEQ_IDX_WRITE 9
#define CMD_SDR 0x01
#define CMD_DDR 0x21
#define RADDR_SDR 0x02
#define RADDR_DDR 0x22
#define CADDR_SDR 0x03
#define CADDR_DDR 0x23
#define MODE1_SDR 0x04
#define MODE1_DDR 0x24
#define MODE2_SDR 0x05
#define MODE2_DDR 0x25
#define MODE4_SDR 0x06
#define MODE4_DDR 0x26
#define MODE8_SDR 0x07
#define MODE8_DDR 0x27
#define WRITE_SDR 0x08
#define WRITE_DDR 0x28
#define READ_SDR 0x09
#define READ_DDR 0x29
#define LEARN_SDR 0x0A
#define LEARN_DDR 0x2A
#define DATSZ_SDR 0x0B
#define DATSZ_DDR 0x2B
#define DUMMY_SDR 0x0C
#define DUMMY_DDR 0x2C
#define DUMMY_RWDS_SDR 0x0D
#define DUMMY_RWDS_DDR 0x2D
#define JMP_ON_CS 0x1F
#define STOP_EXE 0
#define FLEXSPI_1PAD 0
#define FLEXSPI_2PAD 1
#define FLEXSPI_4PAD 2
#define FLEXSPI_8PAD 3
/*! @name LUT - LUT 0..LUT 63 */
/*! @{ */
#define FLEXSPI_LUT_OPERAND0_MASK (0xFFU)
#define FLEXSPI_LUT_OPERAND0_SHIFT (0U)
/*! OPERAND0 - OPERAND0
*/
#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U)
#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U)
/*! NUM_PADS0 - NUM_PADS0
*/
#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
#define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U)
#define FLEXSPI_LUT_OPCODE0_SHIFT (10U)
/*! OPCODE0 - OPCODE
*/
#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
#define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U)
#define FLEXSPI_LUT_OPERAND1_SHIFT (16U)
/*! OPERAND1 - OPERAND1
*/
#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U)
#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U)
/*! NUM_PADS1 - NUM_PADS1
*/
#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
#define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U)
#define FLEXSPI_LUT_OPCODE1_SHIFT (26U)
/*! OPCODE1 - OPCODE1
*/
#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
/*! @} */
/* The count of FLEXSPI_LUT */
#define FLEXSPI_LUT_COUNT (64U)
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
//!@brief Definitions for FlexSPI Serial Clock Frequency
typedef enum _FlexSpiSerialClockFreq {
kFlexSpiSerialClk_30MHz = 1,
kFlexSpiSerialClk_50MHz = 2,
kFlexSpiSerialClk_60MHz = 3,
kFlexSpiSerialClk_80MHz = 4,
kFlexSpiSerialClk_100MHz = 5,
kFlexSpiSerialClk_120MHz = 6,
kFlexSpiSerialClk_133MHz = 7,
kFlexSpiSerialClk_166MHz = 8,
kFlexSpiSerialClk_200MHz = 9,
} flexspi_serial_clk_freq_t;
//!@brief FlexSPI clock configuration type
enum {
kFlexSpiClk_SDR, //!< Clock configure for SDR mode
kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
};
//!@brief FlexSPI Read Sample Clock Source definition
typedef enum _FlashReadSampleClkSource {
kFlexSPIReadSampleClk_LoopbackInternally = 0,
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
} flexspi_read_sample_clk_t;
//!@brief Misc feature bit definitions
enum {
kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
};
//!@brief Flash Type Definition
enum {
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
};
//!@brief Flash Pad Definitions
enum {
kSerialFlash_1Pad = 1,
kSerialFlash_2Pads = 2,
kSerialFlash_4Pads = 4,
kSerialFlash_8Pads = 8,
};
//!@brief FlexSPI LUT Sequence structure
typedef struct _lut_sequence {
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
uint8_t seqId; //!< Sequence Index, valid number: 0-15
uint16_t reserved;
} flexspi_lut_seq_t;
//!@brief Flash Configuration Command Type
enum {
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
kDeviceConfigCmdType_Reset, //!< Reset device command
};
typedef struct {
uint8_t time_100ps; /* Data valid time, in terms of 100ps */
uint8_t delay_cells; /* Data valid time, in terms of delay cells */
} flexspi_dll_time_t;
/*!
* @name Configuration Option
* @{
*/
/*! @brief Serial NOR Configuration Option. */
typedef struct _serial_nor_config_option {
union {
struct {
uint32_t max_freq : 4; /*!< Maximum supported Frequency */
uint32_t misc_mode : 4; /*!< miscellaneous mode */
uint32_t quad_mode_setting : 4; /*!< Quad mode setting */
uint32_t cmd_pads : 4; /*!< Command pads */
uint32_t query_pads : 4; /*!< SFDP read pads */
uint32_t device_type : 4; /*!< Device type */
uint32_t option_size : 4; /*!< Option size, in terms of uint32_t, size = (option_size + 1) * 4 */
uint32_t tag : 4; /*!< Tag, must be 0x0E */
} B;
uint32_t U;
} option0;
union {
struct {
uint32_t dummy_cycles : 8; /*!< Dummy cycles before read */
uint32_t status_override : 8; /*!< Override status register value during device mode configuration */
uint32_t pinmux_group : 4; /*!< The pinmux group selection */
uint32_t dqs_pinmux_group : 4; /*!< The DQS Pinmux Group Selection */
uint32_t drive_strength : 4; /*!< The Drive Strength of FlexSPI Pads */
uint32_t flash_connection : 4; /*!< Flash connection option: 0 - Single Flash connected to port A, 1 -
Parallel mode, 2 - Single Flash connected to Port B */
} B;
uint32_t U;
} option1;
} serial_nor_config_option_t;
//!@brief FlexSPI Memory Configuration Block
struct mem_config_s {
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For Serial NAND, need to refer to datasheet
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, Generic configuration, etc.
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for DPI/QPI/OPI switch or reset command
flexspi_lut_seq_t
deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt sequence number, [31:16] Reserved
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
flexspi_lut_seq_t
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more details
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot Chapter for more details
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot be done using 1 LUT sequence, currently, only applicable to HyperFLASH
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
flexspi_dll_time_t
dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 busy flag is 0 when flash device is busy
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
};
/* */
#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
#define NOR_CMD_INDEX_DUMMY 6 //!< 6
#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
/*
* Serial NOR configuration block
*/
struct flexspi_nor_config_s {
struct mem_config_s memConfig; //!< Common memory configuration info via FlexSPI
uint32_t pageSize; //!< Page size of Serial NOR
uint32_t sectorSize; //!< Sector size of Serial NOR
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
uint8_t reserved0[2]; //!< Reserved for future use
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution
uint32_t blockSize; //!< Block size
uint32_t reserve2[11]; //!< Reserved for future use
};
extern const struct flexspi_nor_config_s g_flash_config;
extern const struct flexspi_nor_config_s g_flash_fast_config;
#endif /* __PX4_ARCH_IMXRT_FLEXSPI_NOR_FLASH_H */
platforms/nuttx/src/px4/nxp/imxrt/include/px4_arch/imxrt_romapi.h
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/****************************************************************************
* platforms/nuttx/src/px4/nxp/imrt/include/px4_arch/imxrt_romapi.h
*
* Copyright 2017-2024 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
****************************************************************************/
#ifndef __PX4_ARCH_IMXRT_ROMAPI_H
#define __PX4_ARCH_IMXRT_ROMAPI_H
/****************************************************************************
*
* Included Files
****************************************************************************/
#include "board_config.h"
typedef int32_t status_t;
typedef struct flexspi_nor_config_s flexspi_nor_config_t;
typedef status_t (*clearCacheCommand_t)(uint32_t instance);
/*! @brief FLEXSPI Operation Context */
typedef enum _flexspi_operation {
kFLEXSPIOperation_Command, /*!< FLEXSPI operation: Only command, both TX and RX buffer are ignored. */
kFLEXSPIOperation_Config, /*!< FLEXSPI operation: Configure device mode, the TX FIFO size is fixed in LUT. */
kFLEXSPIOperation_Write, /*!< FLEXSPI operation: Write, only TX buffer is effective */
kFLEXSPIOperation_Read, /*!< FLEXSPI operation: Read, only Rx Buffer is effective. */
} flexspi_operation_t;
#define kFLEXSPIOperation_End kFLEXSPIOperation_Read
/*! @brief FLEXSPI Transfer Context */
typedef struct _flexspi_xfer {
flexspi_operation_t operation; /*!< FLEXSPI operation */
uint32_t baseAddress; /*!< FLEXSPI operation base address */
uint32_t seqId; /*!< Sequence Id */
uint32_t seqNum; /*!< Sequence Number */
bool isParallelModeEnable; /*!< Is a parallel transfer */
uint32_t *txBuffer; /*!< Tx buffer */
uint32_t txSize; /*!< Tx size in bytes */
uint32_t *rxBuffer; /*!< Rx buffer */
uint32_t rxSize; /*!< Rx size in bytes */
} flexspi_xfer_t;
/*! @brief convert the type for MISRA */
#define MISRA_CAST(to_type, to_var, from_type, from_var) \
do \
{ \
union \
{ \
to_type to_var_tmp; \
from_type from_var_tmp; \
} type_converter_var = {.from_var_tmp = (from_var)}; \
(to_var) = type_converter_var.to_var_tmp; \
} while (false)
#ifdef __cplusplus
extern "C" {
#endif
extern struct flexspi_nor_config_s g_bootConfig;
/*!
* @brief ROM API init
*
* Get the bootloader api entry address.
*/
void ROM_API_Init(void);
/*!
* @name Enter Bootloader
* @{
*/
/*!
* @brief Enter Bootloader.
*
* @param arg A pointer to the storage for the bootloader param.
* refer to System Boot Chapter in device reference manual for details.
*/
void ROM_RunBootloader(void *arg);
/*@}*/
/*!
* @name GetConfig
* @{
*/
/*!
* @brief Get FLEXSPI NOR Configuration Block based on specified option.
*
* @param instance storage the instance of FLEXSPI.
* @param config A pointer to the storage for the driver runtime state.
* @param option A pointer to the storage Serial NOR Configuration Option Context.
*
* @retval kStatus_Success Api was executed successfully.
* @retval kStatus_InvalidArgument A invalid argument is provided.
* @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
* @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
* @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
*/
status_t ROM_FLEXSPI_NorFlash_GetConfig(uint32_t instance,
flexspi_nor_config_t *config,
serial_nor_config_option_t *option);
/*!
* @name Initialization
* @{
*/
/*!
* @brief Initialize Serial NOR devices via FLEXSPI
*
* This function checks and initializes the FLEXSPI module for the other FLEXSPI APIs.
*
* @param instance storage the instance of FLEXSPI.
* @param config A pointer to the storage for the driver runtime state.
*
* @retval kStatus_Success Api was executed successfully.
* @retval kStatus_InvalidArgument A invalid argument is provided.
* @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
* @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
* @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
*/
status_t ROM_FLEXSPI_NorFlash_Init(uint32_t instance, flexspi_nor_config_t *config);
/*@}*/
/*!
* @name Programming
* @{
*/
/*!
* @brief Program data to Serial NOR via FLEXSPI.
*
* This function programs the NOR flash memory with the dest address for a given
* flash area as determined by the dst address and the length.
*
* @param instance storage the instance of FLEXSPI.
* @param config A pointer to the storage for the driver runtime state.
* @param dst_addr A pointer to the desired flash memory to be programmed.
* @note It is recommended that use page aligned access;
* If the dst_addr is not aligned to page, the driver automatically
* aligns address down with the page address.
* @param src A pointer to the source buffer of data that is to be programmed
* into the NOR flash.
*
* @retval kStatus_Success Api was executed successfully.
* @retval kStatus_InvalidArgument A invalid argument is provided.
* @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
* @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
* @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
*/
status_t ROM_FLEXSPI_NorFlash_ProgramPage(uint32_t instance,
flexspi_nor_config_t *config,
uint32_t dst_addr,
const uint32_t *src);
/*@}*/
/*!
* @name Reading
* @{
*/
/*!
* @brief Read data from Serial NOR via FLEXSPI.
*
* This function read the NOR flash memory with the start address for a given
* flash area as determined by the dst address and the length.
*
* @param instance storage the instance of FLEXSPI.
* @param config A pointer to the storage for the driver runtime state.
* @param dst A pointer to the dest buffer of data that is to be read from the NOR flash.
* @note It is recommended that use page aligned access;
* If the dstAddr is not aligned to page, the driver automatically
* aligns address down with the page address.
* @param start The start address of the desired NOR flash memory to be read.
* @param lengthInBytes The length, given in bytes to be read.
*
* @retval kStatus_Success Api was executed successfully.
* @retval kStatus_InvalidArgument A invalid argument is provided.
* @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
* @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
* @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
*/
status_t ROM_FLEXSPI_NorFlash_Read(
uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t lengthInBytes);
/*@}*/
/*!
* @name Erasing
* @{
*/
/*!
* @brief Erase Flash Region specified by address and length
*
* This function erases the appropriate number of flash sectors based on the
* desired start address and length.
*
* @param instance storage the index of FLEXSPI.
* @param config A pointer to the storage for the driver runtime state.
* @param start The start address of the desired NOR flash memory to be erased.
* @note It is recommended that use sector-aligned access nor device;
* If dstAddr is not aligned with the sector,the driver automatically
* aligns address down with the sector address.
* @param length The length, given in bytes to be erased.
* @note It is recommended that use sector-aligned access nor device;
* If length is not aligned with the sector,the driver automatically
* aligns up with the sector.
* @retval kStatus_Success Api was executed successfully.
* @retval kStatus_InvalidArgument A invalid argument is provided.
* @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
* @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
* @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
*/
status_t ROM_FLEXSPI_NorFlash_Erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length);
/*!
* @brief Erase one sector specified by address
*
* This function erases one of NOR flash sectors based on the desired address.
*
* @param instance storage the index of FLEXSPI.
* @param config A pointer to the storage for the driver runtime state.
* @param start The start address of the desired NOR flash memory to be erased.
* @note It is recommended that use sector-aligned access nor device;
* If dstAddr is not aligned with the sector, the driver automatically
* aligns address down with the sector address.
*
* @retval kStatus_Success Api was executed successfully.
* @retval kStatus_InvalidArgument A invalid argument is provided.
* @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
* @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
* @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
*/
status_t ROM_FLEXSPI_NorFlash_EraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t start);
/*!
* @brief Erase one block specified by address
*
* This function erases one block of NOR flash based on the desired address.
*
* @param instance storage the index of FLEXSPI.
* @param config A pointer to the storage for the driver runtime state.
* @param start The start address of the desired NOR flash memory to be erased.
* @note It is recommended that use block-aligned access nor device;
* If dstAddr is not aligned with the block, the driver automatically
* aligns address down with the block address.
*
* @retval kStatus_Success Api was executed successfully.
* @retval kStatus_InvalidArgument A invalid argument is provided.
* @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
* @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
* @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
*/
status_t ROM_FLEXSPI_NorFlash_EraseBlock(uint32_t instance, flexspi_nor_config_t *config, uint32_t start);
/*!
* @brief Erase all the Serial NOR devices connected on FLEXSPI.
*
* @param instance storage the instance of FLEXSPI.
* @param config A pointer to the storage for the driver runtime state.
*
* @retval kStatus_Success Api was executed successfully.
* @retval kStatus_InvalidArgument A invalid argument is provided.
* @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
* @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
* @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
*/
status_t ROM_FLEXSPI_NorFlash_EraseAll(uint32_t instance, flexspi_nor_config_t *config);
/*@}*/
/*!
* @name Command
* @{
*/
/*!
* @brief FLEXSPI command
*
* This function is used to perform the command write sequence to the NOR device.
*
* @param instance storage the index of FLEXSPI.
* @param xfer A pointer to the storage FLEXSPI Transfer Context.
*
* @retval kStatus_Success Api was executed successfully.
* @retval kStatus_InvalidArgument A invalid argument is provided.
* @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
* @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
*/
status_t ROM_FLEXSPI_NorFlash_CommandXfer(uint32_t instance, flexspi_xfer_t *xfer);
/*@}*/
/*!
* @name UpdateLut
* @{
*/
/*!
* @brief Configure FLEXSPI Lookup table
*
* @param instance storage the index of FLEXSPI.
* @param seqIndex storage the sequence Id.
* @param lutBase A pointer to the look-up-table for command sequences.
* @param seqNumber storage sequence number.
*
* @retval kStatus_Success Api was executed successfully.
* @retval kStatus_InvalidArgument A invalid argument is provided.
* @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
* @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
*/
status_t ROM_FLEXSPI_NorFlash_UpdateLut(uint32_t instance,
uint32_t seqIndex,
const uint32_t *lutBase,
uint32_t seqNumber);
/*@}*/
/*!
* @name Device status
* @{
*/
/*!
* @brief Wait until device is idle.
*
* @param instance Indicates the index of FLEXSPI.
* @param config A pointer to the storage for the driver runtime state
* @param isParallelMode Indicates whether NOR flash is in parallel mode.
* @param address Indicates the operation(erase/program/read) address for serial NOR flash.
*
* @retval kStatus_Success Api was executed successfully.
* @retval kStatus_InvalidArgument A invalid argument is provided.
* @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
* @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
* @retval kStatus_ROM_FLEXSPI_DeviceTimeout Device timeout.
*/
status_t ROM_FLEXSPI_NorFlash_WaitBusy(uint32_t instance,
flexspi_nor_config_t *config,
bool isParallelMode,
uint32_t address);
/*@}*/
/*!
* @name ClearCache
* @{
*/
/*!
* @name ClearCache
* @{
*/
/*!
* @brief Software reset for the FLEXSPI logic.
*
* This function sets the software reset flags for both AHB and buffer domain and
* resets both AHB buffer and also IP FIFOs.
*
* @param instance storage the index of FLEXSPI.
*/
void ROM_FLEXSPI_NorFlash_ClearCache(uint32_t instance);
/*@}*/
#ifdef __cplusplus
}
#endif
#endif /* __PX4_ARCH_IMXRT_ROMAPI_H */
platforms/nuttx/src/px4/nxp/imxrt/romapi/CMakeLists.txt
+36
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@@ -0,0 +1,36 @@
############################################################################
#
# Copyright (c) 2019 PX4 Development Team. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name PX4 nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
############################################################################
px4_add_library(arch_board_romapi
imxrt_romapi.c
)
platforms/nuttx/src/px4/nxp/imxrt/romapi/imxrt_romapi.c
+271
View File
@@ -0,0 +1,271 @@
/****************************************************************************
* platforms/nuttx/src/px4/nxp/imrt/romapi/imxrt_romapi.c
*
* Copyright 2017-2024 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
****************************************************************************/
/****************************************************************************
*
* Included Files
****************************************************************************/
#include "board_config.h"
#include <stdbool.h>
#include <debug.h>
#include <stdint.h>
#include <stdbool.h>
#include "arm_internal.h"
#include <px4_arch/imxrt_flexspi_nor_flash.h>
#include <px4_arch/imxrt_romapi.h>
#include <hardware/rt117x/imxrt117x_anadig.h>
/*******************************************************************************
* Definitions
******************************************************************************/
/*!
* @brief Structure of version property.
*
* @ingroup bl_core
*/
typedef union _standard_version {
struct {
uint8_t bugfix; /*!< bugfix version [7:0] */
uint8_t minor; /*!< minor version [15:8] */
uint8_t major; /*!< major version [23:16] */
char name; /*!< name [31:24] */
};
uint32_t version; /*!< combined version numbers */
#if defined(__cplusplus)
StandardVersion() : version(0) {
}
StandardVersion(uint32_t version) : version(version) {
}
#endif
} standard_version_t;
/*!
* @brief Interface for the ROM FLEXSPI NOR flash driver.
*/
typedef struct {
uint32_t version;
status_t (*init)(uint32_t instance, flexspi_nor_config_t *config);
status_t (*page_program)(uint32_t instance, flexspi_nor_config_t *config, uint32_t dst_addr, const uint32_t *src);
status_t (*erase_all)(uint32_t instance, flexspi_nor_config_t *config);
status_t (*erase)(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length);
status_t (*read)(uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t bytes);
void (*clear_cache)(uint32_t instance);
status_t (*xfer)(uint32_t instance, flexspi_xfer_t *xfer);
status_t (*update_lut)(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t numberOfSeq);
status_t (*get_config)(uint32_t instance, flexspi_nor_config_t *config, serial_nor_config_option_t *option);
status_t (*erase_sector)(uint32_t instance, flexspi_nor_config_t *config, uint32_t address);
status_t (*erase_block)(uint32_t instance, flexspi_nor_config_t *config, uint32_t address);
const uint32_t reserved0; /*!< Reserved */
status_t (*wait_busy)(uint32_t instance, flexspi_nor_config_t *config, bool isParallelMode, uint32_t address);
const uint32_t reserved1[2]; /*!< Reserved */
} flexspi_nor_driver_interface_t;
/*!
* @brief Root of the bootloader api tree.
*
* An instance of this struct resides in read-only memory in the bootloader. It
* provides a user application access to APIs exported by the bootloader.
*
* @note The order of existing fields must not be changed.
*/
typedef struct {
void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing.*/
standard_version_t version; /*!< Bootloader version number.*/
const char *copyright; /*!< Copyright string.*/
const flexspi_nor_driver_interface_t *flexSpiNorDriver; /*!< FlexSPI NOR FLASH Driver API.*/
const uint32_t reserved[8]; /*!< Reserved */
} bootloader_api_entry_t;
/*******************************************************************************
* Variables
******************************************************************************/
static bootloader_api_entry_t *g_bootloaderTree = NULL;
/*******************************************************************************
* ROM FLEXSPI NOR driver
******************************************************************************/
/*!
* @brief ROM API init.
*/
locate_code(".ramfunc")
void ROM_API_Init(void)
{
if ((getreg32(IMXRT_ANADIG_MISC_MISC_DIFPROG) & ANADIG_MISC_MISC_DIFPROG_CHIPID(0x10U)) != 0U) {
g_bootloaderTree = ((bootloader_api_entry_t *) * (uint32_t *)0x0021001cU);
} else {
g_bootloaderTree = ((bootloader_api_entry_t *) * (uint32_t *)0x0020001cU);
}
}
/*!
* @brief Enter Bootloader.
*
* @param arg A pointer to the storage for the bootloader param.
* refer to System Boot Chapter in device reference manual for details.
*/
locate_code(".ramfunc")
void ROM_RunBootloader(void *arg)
{
g_bootloaderTree->runBootloader(arg);
}
/*! @brief Get FLEXSPI NOR Configuration Block based on specified option. */
locate_code(".ramfunc")
status_t ROM_FLEXSPI_NorFlash_GetConfig(uint32_t instance,
flexspi_nor_config_t *config,
serial_nor_config_option_t *option)
{
return g_bootloaderTree->flexSpiNorDriver->get_config(instance, config, option);
}
/*!
* @brief Initialize Serial NOR devices via FLEXSPI.
*
* @param instance storage the instance of FLEXSPI.
* @param config A pointer to the storage for the driver runtime state.
*/
locate_code(".ramfunc")
status_t ROM_FLEXSPI_NorFlash_Init(uint32_t instance, flexspi_nor_config_t *config)
{
return g_bootloaderTree->flexSpiNorDriver->init(instance, config);
}
/*!
* @brief Program data to Serial NOR via FLEXSPI.
*
* @param instance storage the instance of FLEXSPI.
* @param config A pointer to the storage for the driver runtime state.
* @param dst_addr A pointer to the desired flash memory to be programmed.
* @param src A pointer to the source buffer of data that is to be programmed
* into the NOR flash.
*/
locate_code(".ramfunc")
status_t ROM_FLEXSPI_NorFlash_ProgramPage(uint32_t instance,
flexspi_nor_config_t *config,
uint32_t dst_addr,
const uint32_t *src)
{
return g_bootloaderTree->flexSpiNorDriver->page_program(instance, config, dst_addr, src);
}
/*!
* @brief Read data from Serial NOR
*
* @param instance storage the instance of FLEXSPI.
* @param config A pointer to the storage for the driver runtime state.
* @param dst A pointer to the dest buffer of data that is to be read from the NOR flash.
* @param lengthInBytes The length, given in bytes to be read.
*/
locate_code(".ramfunc")
status_t ROM_FLEXSPI_NorFlash_Read(
uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t lengthInBytes)
{
return g_bootloaderTree->flexSpiNorDriver->read(instance, config, dst, start, lengthInBytes);
}
/*!
* @brief Erase Flash Region specified by address and length.
*
* @param instance storage the index of FLEXSPI.
* @param config A pointer to the storage for the driver runtime state.
* @param start The start address of the desired NOR flash memory to be erased.
* @param length The length, given in bytes to be erased.
*/
locate_code(".ramfunc")
status_t ROM_FLEXSPI_NorFlash_Erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length)
{
return g_bootloaderTree->flexSpiNorDriver->erase(instance, config, start, length);
}
/*!
* @brief Erase one sector specified by address.
*
* @param instance storage the index of FLEXSPI.
* @param config A pointer to the storage for the driver runtime state.
* @param start The start address of the desired NOR flash memory to be erased.
*/
locate_code(".ramfunc")
status_t ROM_FLEXSPI_NorFlash_EraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t start)
{
return g_bootloaderTree->flexSpiNorDriver->erase_sector(instance, config, start);
}
/*!
* @brief Erase one block specified by address.
*
* @param instance storage the index of FLEXSPI.
* @param config A pointer to the storage for the driver runtime state.
* @param start The start address of the desired NOR flash memory to be erased.
*/
locate_code(".ramfunc")
status_t ROM_FLEXSPI_NorFlash_EraseBlock(uint32_t instance, flexspi_nor_config_t *config, uint32_t start)
{
return g_bootloaderTree->flexSpiNorDriver->erase_block(instance, config, start);
}
/*! @brief Erase all the Serial NOR devices connected on FLEXSPI. */
locate_code(".ramfunc")
status_t ROM_FLEXSPI_NorFlash_EraseAll(uint32_t instance, flexspi_nor_config_t *config)
{
return g_bootloaderTree->flexSpiNorDriver->erase_all(instance, config);
}
/*! @brief FLEXSPI command */
locate_code(".ramfunc")
status_t ROM_FLEXSPI_NorFlash_CommandXfer(uint32_t instance, flexspi_xfer_t *xfer)
{
return g_bootloaderTree->flexSpiNorDriver->xfer(instance, xfer);
}
/*! @brief Configure FLEXSPI Lookup table. */
locate_code(".ramfunc")
status_t ROM_FLEXSPI_NorFlash_UpdateLut(uint32_t instance,
uint32_t seqIndex,
const uint32_t *lutBase,
uint32_t seqNumber)
{
return g_bootloaderTree->flexSpiNorDriver->update_lut(instance, seqIndex, lutBase, seqNumber);
}
/*! @brief Software reset for the FLEXSPI logic. */
locate_code(".ramfunc")
void ROM_FLEXSPI_NorFlash_ClearCache(uint32_t instance)
{
uint32_t clearCacheFunctionAddress;
if ((getreg32(IMXRT_ANADIG_MISC_MISC_DIFPROG) & ANADIG_MISC_MISC_DIFPROG_CHIPID(0x10U)) != 0U) {
clearCacheFunctionAddress = 0x0021a3b7U;
} else {
clearCacheFunctionAddress = 0x0020426bU;
}
clearCacheCommand_t clearCacheCommand;
MISRA_CAST(clearCacheCommand_t, clearCacheCommand, uint32_t, clearCacheFunctionAddress);
(void)clearCacheCommand(instance);
}
/*! @brief Wait until device is idle*/
locate_code(".ramfunc")
status_t ROM_FLEXSPI_NorFlash_WaitBusy(uint32_t instance,
flexspi_nor_config_t *config,
bool isParallelMode,
uint32_t address)
{
return g_bootloaderTree->flexSpiNorDriver->wait_busy(instance, config, isParallelMode, address);
}
platforms/nuttx/src/px4/nxp/rt117x/CMakeLists.txt
+1 -1
View File
@@ -36,7 +36,7 @@ add_subdirectory(adc)
add_subdirectory(../imxrt/board_critmon board_critmon)
add_subdirectory(../imxrt/board_hw_info board_hw_info)
add_subdirectory(../imxrt/board_reset board_reset)
#add_subdirectory(../imxrt/dshot dshot)
add_subdirectory(../imxrt/romapi romapi)
add_subdirectory(../imxrt/hrt hrt)
add_subdirectory(../imxrt/led_pwm led_pwm)
add_subdirectory(../imxrt/io_pins io_pins)
platforms/nuttx/src/px4/nxp/rt117x/include/px4_arch/imxrt_flexspi_nor_flash.h
+36
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@@ -0,0 +1,36 @@
/****************************************************************************
*
* Copyright (c) 2024 PX4 Development Team. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name PX4 nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#pragma once
#include "../../../imxrt/include/px4_arch/imxrt_flexspi_nor_flash.h"
platforms/nuttx/src/px4/nxp/rt117x/include/px4_arch/imxrt_romapi.h
+36
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@@ -0,0 +1,36 @@
/****************************************************************************
*
* Copyright (c) 2024 PX4 Development Team. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name PX4 nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#pragma once
#include "../../../imxrt/include/px4_arch/imxrt_romapi.h"