From 8a8bb78d38b0b5d9f774cb33a372ca4ef4c87d23 Mon Sep 17 00:00:00 2001 From: Pavel Kirienko Date: Thu, 28 Aug 2014 17:28:44 +0400 Subject: [PATCH] More warning fixes in the STM32 drvier, STM32 test project and the library core --- libuavcan/include/uavcan/marshal/array.hpp | 4 +- libuavcan/include/uavcan/transport/crc.hpp | 6 +- libuavcan/src/transport/uc_frame.cpp | 2 +- .../driver/include/uavcan_stm32/bxcan.hpp | 296 +++++++++--------- .../driver/include/uavcan_stm32/clock.hpp | 10 +- .../stm32/driver/src/uc_stm32_can.cpp | 36 +-- .../stm32/driver/src/uc_stm32_clock.cpp | 16 +- 7 files changed, 186 insertions(+), 184 deletions(-) diff --git a/libuavcan/include/uavcan/marshal/array.hpp b/libuavcan/include/uavcan/marshal/array.hpp index fd2bb3f106..3eae8653cd 100644 --- a/libuavcan/include/uavcan/marshal/array.hpp +++ b/libuavcan/include/uavcan/marshal/array.hpp @@ -56,7 +56,7 @@ protected: throw std::out_of_range("uavcan::Array"); #else UAVCAN_ASSERT(0); - return Size - 1; // Ha ha + return SizeType(Size - 1U); // Ha ha #endif } }; @@ -87,7 +87,7 @@ protected: throw std::out_of_range("uavcan::Array"); #else UAVCAN_ASSERT(0); - return (size_ == 0) ? 0 : (size_ - 1); + return SizeType((size_ == 0U) ? 0U : (size_ - 1U)); #endif } diff --git a/libuavcan/include/uavcan/transport/crc.hpp b/libuavcan/include/uavcan/transport/crc.hpp index 86eb24083c..15b19e4e97 100644 --- a/libuavcan/include/uavcan/transport/crc.hpp +++ b/libuavcan/include/uavcan/transport/crc.hpp @@ -42,16 +42,16 @@ public: #if UAVCAN_TINY void add(uint8_t byte) { - value_ ^= static_cast(byte) << 8; + value_ ^= uint16_t(uint16_t(byte) << 8); for (uint8_t bit = 8; bit > 0; --bit) { if (value_ & 0x8000U) { - value_ = (value_ << 1) ^ 0x1021U; + value_ = uint16_t(uint16_t(value_ << 1) ^ 0x1021U); } else { - value_ = (value_ << 1); + value_ = uint16_t(value_ << 1); } } } diff --git a/libuavcan/src/transport/uc_frame.cpp b/libuavcan/src/transport/uc_frame.cpp index 4314fb73a8..8340c21ed6 100644 --- a/libuavcan/src/transport/uc_frame.cpp +++ b/libuavcan/src/transport/uc_frame.cpp @@ -141,7 +141,7 @@ bool Frame::compile(CanFrame& out_can_frame) const { case TransferTypeMessageBroadcast: { - out_can_frame.dlc = payload_len_; + out_can_frame.dlc = uint8_t(payload_len_); (void)copy(payload_, payload_ + payload_len_, out_can_frame.data); break; } diff --git a/libuavcan_drivers/stm32/driver/include/uavcan_stm32/bxcan.hpp b/libuavcan_drivers/stm32/driver/include/uavcan_stm32/bxcan.hpp index eeeadbee48..2bf1e375f2 100644 --- a/libuavcan_drivers/stm32/driver/include/uavcan_stm32/bxcan.hpp +++ b/libuavcan_drivers/stm32/driver/include/uavcan_stm32/bxcan.hpp @@ -88,200 +88,200 @@ CanType* const Can[UAVCAN_STM32_NUM_IFACES] = /* CAN master control register */ -constexpr unsigned long MCR_INRQ = (1 << 0); /* Bit 0: Initialization Request */ -constexpr unsigned long MCR_SLEEP = (1 << 1); /* Bit 1: Sleep Mode Request */ -constexpr unsigned long MCR_TXFP = (1 << 2); /* Bit 2: Transmit FIFO Priority */ -constexpr unsigned long MCR_RFLM = (1 << 3); /* Bit 3: Receive FIFO Locked Mode */ -constexpr unsigned long MCR_NART = (1 << 4); /* Bit 4: No Automatic Retransmission */ -constexpr unsigned long MCR_AWUM = (1 << 5); /* Bit 5: Automatic Wakeup Mode */ -constexpr unsigned long MCR_ABOM = (1 << 6); /* Bit 6: Automatic Bus-Off Management */ -constexpr unsigned long MCR_TTCM = (1 << 7); /* Bit 7: Time Triggered Communication Mode Enable */ -constexpr unsigned long MCR_RESET = (1 << 15);/* Bit 15: bxCAN software master reset */ -constexpr unsigned long MCR_DBF = (1 << 16);/* Bit 16: Debug freeze */ +constexpr unsigned long MCR_INRQ = (1U << 0); /* Bit 0: Initialization Request */ +constexpr unsigned long MCR_SLEEP = (1U << 1); /* Bit 1: Sleep Mode Request */ +constexpr unsigned long MCR_TXFP = (1U << 2); /* Bit 2: Transmit FIFO Priority */ +constexpr unsigned long MCR_RFLM = (1U << 3); /* Bit 3: Receive FIFO Locked Mode */ +constexpr unsigned long MCR_NART = (1U << 4); /* Bit 4: No Automatic Retransmission */ +constexpr unsigned long MCR_AWUM = (1U << 5); /* Bit 5: Automatic Wakeup Mode */ +constexpr unsigned long MCR_ABOM = (1U << 6); /* Bit 6: Automatic Bus-Off Management */ +constexpr unsigned long MCR_TTCM = (1U << 7); /* Bit 7: Time Triggered Communication Mode Enable */ +constexpr unsigned long MCR_RESET = (1U << 15);/* Bit 15: bxCAN software master reset */ +constexpr unsigned long MCR_DBF = (1U << 16);/* Bit 16: Debug freeze */ /* CAN master status register */ -constexpr unsigned long MSR_INAK = (1 << 0); /* Bit 0: Initialization Acknowledge */ -constexpr unsigned long MSR_SLAK = (1 << 1); /* Bit 1: Sleep Acknowledge */ -constexpr unsigned long MSR_ERRI = (1 << 2); /* Bit 2: Error Interrupt */ -constexpr unsigned long MSR_WKUI = (1 << 3); /* Bit 3: Wakeup Interrupt */ -constexpr unsigned long MSR_SLAKI = (1 << 4); /* Bit 4: Sleep acknowledge interrupt */ -constexpr unsigned long MSR_TXM = (1 << 8); /* Bit 8: Transmit Mode */ -constexpr unsigned long MSR_RXM = (1 << 9); /* Bit 9: Receive Mode */ -constexpr unsigned long MSR_SAMP = (1 << 10);/* Bit 10: Last Sample Point */ -constexpr unsigned long MSR_RX = (1 << 11);/* Bit 11: CAN Rx Signal */ +constexpr unsigned long MSR_INAK = (1U << 0); /* Bit 0: Initialization Acknowledge */ +constexpr unsigned long MSR_SLAK = (1U << 1); /* Bit 1: Sleep Acknowledge */ +constexpr unsigned long MSR_ERRI = (1U << 2); /* Bit 2: Error Interrupt */ +constexpr unsigned long MSR_WKUI = (1U << 3); /* Bit 3: Wakeup Interrupt */ +constexpr unsigned long MSR_SLAKI = (1U << 4); /* Bit 4: Sleep acknowledge interrupt */ +constexpr unsigned long MSR_TXM = (1U << 8); /* Bit 8: Transmit Mode */ +constexpr unsigned long MSR_RXM = (1U << 9); /* Bit 9: Receive Mode */ +constexpr unsigned long MSR_SAMP = (1U << 10);/* Bit 10: Last Sample Point */ +constexpr unsigned long MSR_RX = (1U << 11);/* Bit 11: CAN Rx Signal */ /* CAN transmit status register */ -constexpr unsigned long TSR_RQCP0 = (1 << 0); /* Bit 0: Request Completed Mailbox 0 */ -constexpr unsigned long TSR_TXOK0 = (1 << 1); /* Bit 1 : Transmission OK of Mailbox 0 */ -constexpr unsigned long TSR_ALST0 = (1 << 2); /* Bit 2 : Arbitration Lost for Mailbox 0 */ -constexpr unsigned long TSR_TERR0 = (1 << 3); /* Bit 3 : Transmission Error of Mailbox 0 */ -constexpr unsigned long TSR_ABRQ0 = (1 << 7); /* Bit 7 : Abort Request for Mailbox 0 */ -constexpr unsigned long TSR_RQCP1 = (1 << 8); /* Bit 8 : Request Completed Mailbox 1 */ -constexpr unsigned long TSR_TXOK1 = (1 << 9); /* Bit 9 : Transmission OK of Mailbox 1 */ -constexpr unsigned long TSR_ALST1 = (1 << 10);/* Bit 10 : Arbitration Lost for Mailbox 1 */ -constexpr unsigned long TSR_TERR1 = (1 << 11);/* Bit 11 : Transmission Error of Mailbox 1 */ -constexpr unsigned long TSR_ABRQ1 = (1 << 15);/* Bit 15 : Abort Request for Mailbox 1 */ -constexpr unsigned long TSR_RQCP2 = (1 << 16);/* Bit 16 : Request Completed Mailbox 2 */ -constexpr unsigned long TSR_TXOK2 = (1 << 17);/* Bit 17 : Transmission OK of Mailbox 2 */ -constexpr unsigned long TSR_ALST2 = (1 << 18);/* Bit 18: Arbitration Lost for Mailbox 2 */ -constexpr unsigned long TSR_TERR2 = (1 << 19);/* Bit 19: Transmission Error of Mailbox 2 */ -constexpr unsigned long TSR_ABRQ2 = (1 << 23);/* Bit 23: Abort Request for Mailbox 2 */ -constexpr unsigned long TSR_CODE_SHIFT = (24); /* Bits 25-24: Mailbox Code */ -constexpr unsigned long TSR_CODE_MASK = (3 << TSR_CODE_SHIFT); -constexpr unsigned long TSR_TME0 = (1 << 26);/* Bit 26: Transmit Mailbox 0 Empty */ -constexpr unsigned long TSR_TME1 = (1 << 27);/* Bit 27: Transmit Mailbox 1 Empty */ -constexpr unsigned long TSR_TME2 = (1 << 28);/* Bit 28: Transmit Mailbox 2 Empty */ -constexpr unsigned long TSR_LOW0 = (1 << 29);/* Bit 29: Lowest Priority Flag for Mailbox 0 */ -constexpr unsigned long TSR_LOW1 = (1 << 30);/* Bit 30: Lowest Priority Flag for Mailbox 1 */ -constexpr unsigned long TSR_LOW2 = (1 << 31);/* Bit 31: Lowest Priority Flag for Mailbox 2 */ +constexpr unsigned long TSR_RQCP0 = (1U << 0); /* Bit 0: Request Completed Mailbox 0 */ +constexpr unsigned long TSR_TXOK0 = (1U << 1); /* Bit 1 : Transmission OK of Mailbox 0 */ +constexpr unsigned long TSR_ALST0 = (1U << 2); /* Bit 2 : Arbitration Lost for Mailbox 0 */ +constexpr unsigned long TSR_TERR0 = (1U << 3); /* Bit 3 : Transmission Error of Mailbox 0 */ +constexpr unsigned long TSR_ABRQ0 = (1U << 7); /* Bit 7 : Abort Request for Mailbox 0 */ +constexpr unsigned long TSR_RQCP1 = (1U << 8); /* Bit 8 : Request Completed Mailbox 1 */ +constexpr unsigned long TSR_TXOK1 = (1U << 9); /* Bit 9 : Transmission OK of Mailbox 1 */ +constexpr unsigned long TSR_ALST1 = (1U << 10);/* Bit 10 : Arbitration Lost for Mailbox 1 */ +constexpr unsigned long TSR_TERR1 = (1U << 11);/* Bit 11 : Transmission Error of Mailbox 1 */ +constexpr unsigned long TSR_ABRQ1 = (1U << 15);/* Bit 15 : Abort Request for Mailbox 1 */ +constexpr unsigned long TSR_RQCP2 = (1U << 16);/* Bit 16 : Request Completed Mailbox 2 */ +constexpr unsigned long TSR_TXOK2 = (1U << 17);/* Bit 17 : Transmission OK of Mailbox 2 */ +constexpr unsigned long TSR_ALST2 = (1U << 18);/* Bit 18: Arbitration Lost for Mailbox 2 */ +constexpr unsigned long TSR_TERR2 = (1U << 19);/* Bit 19: Transmission Error of Mailbox 2 */ +constexpr unsigned long TSR_ABRQ2 = (1U << 23);/* Bit 23: Abort Request for Mailbox 2 */ +constexpr unsigned long TSR_CODE_SHIFT = (24U); /* Bits 25-24: Mailbox Code */ +constexpr unsigned long TSR_CODE_MASK = (3U << TSR_CODE_SHIFT); +constexpr unsigned long TSR_TME0 = (1U << 26);/* Bit 26: Transmit Mailbox 0 Empty */ +constexpr unsigned long TSR_TME1 = (1U << 27);/* Bit 27: Transmit Mailbox 1 Empty */ +constexpr unsigned long TSR_TME2 = (1U << 28);/* Bit 28: Transmit Mailbox 2 Empty */ +constexpr unsigned long TSR_LOW0 = (1U << 29);/* Bit 29: Lowest Priority Flag for Mailbox 0 */ +constexpr unsigned long TSR_LOW1 = (1U << 30);/* Bit 30: Lowest Priority Flag for Mailbox 1 */ +constexpr unsigned long TSR_LOW2 = (1U << 31);/* Bit 31: Lowest Priority Flag for Mailbox 2 */ /* CAN receive FIFO 0/1 registers */ -constexpr unsigned long RFR_FMP_SHIFT = (0); /* Bits 1-0: FIFO Message Pending */ -constexpr unsigned long RFR_FMP_MASK = (3 << RFR_FMP_SHIFT); -constexpr unsigned long RFR_FULL = (1 << 3); /* Bit 3: FIFO 0 Full */ -constexpr unsigned long RFR_FOVR = (1 << 4); /* Bit 4: FIFO 0 Overrun */ -constexpr unsigned long RFR_RFOM = (1 << 5); /* Bit 5: Release FIFO 0 Output Mailbox */ +constexpr unsigned long RFR_FMP_SHIFT = (0U); /* Bits 1-0: FIFO Message Pending */ +constexpr unsigned long RFR_FMP_MASK = (3U << RFR_FMP_SHIFT); +constexpr unsigned long RFR_FULL = (1U << 3); /* Bit 3: FIFO 0 Full */ +constexpr unsigned long RFR_FOVR = (1U << 4); /* Bit 4: FIFO 0 Overrun */ +constexpr unsigned long RFR_RFOM = (1U << 5); /* Bit 5: Release FIFO 0 Output Mailbox */ /* CAN interrupt enable register */ -constexpr unsigned long IER_TMEIE = (1 << 0); /* Bit 0: Transmit Mailbox Empty Interrupt Enable */ -constexpr unsigned long IER_FMPIE0 = (1 << 1); /* Bit 1: FIFO Message Pending Interrupt Enable */ -constexpr unsigned long IER_FFIE0 = (1 << 2); /* Bit 2: FIFO Full Interrupt Enable */ -constexpr unsigned long IER_FOVIE0 = (1 << 3); /* Bit 3: FIFO Overrun Interrupt Enable */ -constexpr unsigned long IER_FMPIE1 = (1 << 4); /* Bit 4: FIFO Message Pending Interrupt Enable */ -constexpr unsigned long IER_FFIE1 = (1 << 5); /* Bit 5: FIFO Full Interrupt Enable */ -constexpr unsigned long IER_FOVIE1 = (1 << 6); /* Bit 6: FIFO Overrun Interrupt Enable */ -constexpr unsigned long IER_EWGIE = (1 << 8); /* Bit 8: Error Warning Interrupt Enable */ -constexpr unsigned long IER_EPVIE = (1 << 9); /* Bit 9: Error Passive Interrupt Enable */ -constexpr unsigned long IER_BOFIE = (1 << 10);/* Bit 10: Bus-Off Interrupt Enable */ -constexpr unsigned long IER_LECIE = (1 << 11);/* Bit 11: Last Error Code Interrupt Enable */ -constexpr unsigned long IER_ERRIE = (1 << 15);/* Bit 15: Error Interrupt Enable */ -constexpr unsigned long IER_WKUIE = (1 << 16);/* Bit 16: Wakeup Interrupt Enable */ -constexpr unsigned long IER_SLKIE = (1 << 17);/* Bit 17: Sleep Interrupt Enable */ +constexpr unsigned long IER_TMEIE = (1U << 0); /* Bit 0: Transmit Mailbox Empty Interrupt Enable */ +constexpr unsigned long IER_FMPIE0 = (1U << 1); /* Bit 1: FIFO Message Pending Interrupt Enable */ +constexpr unsigned long IER_FFIE0 = (1U << 2); /* Bit 2: FIFO Full Interrupt Enable */ +constexpr unsigned long IER_FOVIE0 = (1U << 3); /* Bit 3: FIFO Overrun Interrupt Enable */ +constexpr unsigned long IER_FMPIE1 = (1U << 4); /* Bit 4: FIFO Message Pending Interrupt Enable */ +constexpr unsigned long IER_FFIE1 = (1U << 5); /* Bit 5: FIFO Full Interrupt Enable */ +constexpr unsigned long IER_FOVIE1 = (1U << 6); /* Bit 6: FIFO Overrun Interrupt Enable */ +constexpr unsigned long IER_EWGIE = (1U << 8); /* Bit 8: Error Warning Interrupt Enable */ +constexpr unsigned long IER_EPVIE = (1U << 9); /* Bit 9: Error Passive Interrupt Enable */ +constexpr unsigned long IER_BOFIE = (1U << 10);/* Bit 10: Bus-Off Interrupt Enable */ +constexpr unsigned long IER_LECIE = (1U << 11);/* Bit 11: Last Error Code Interrupt Enable */ +constexpr unsigned long IER_ERRIE = (1U << 15);/* Bit 15: Error Interrupt Enable */ +constexpr unsigned long IER_WKUIE = (1U << 16);/* Bit 16: Wakeup Interrupt Enable */ +constexpr unsigned long IER_SLKIE = (1U << 17);/* Bit 17: Sleep Interrupt Enable */ /* CAN error status register */ -constexpr unsigned long ESR_EWGF = (1 << 0); /* Bit 0: Error Warning Flag */ -constexpr unsigned long ESR_EPVF = (1 << 1); /* Bit 1: Error Passive Flag */ -constexpr unsigned long ESR_BOFF = (1 << 2); /* Bit 2: Bus-Off Flag */ -constexpr unsigned long ESR_LEC_SHIFT = (4); /* Bits 6-4: Last Error Code */ -constexpr unsigned long ESR_LEC_MASK = (7 << ESR_LEC_SHIFT); -constexpr unsigned long ESR_NOERROR = (0 << ESR_LEC_SHIFT);/* 000: No Error */ -constexpr unsigned long ESR_STUFFERROR = (1 << ESR_LEC_SHIFT);/* 001: Stuff Error */ -constexpr unsigned long ESR_FORMERROR = (2 << ESR_LEC_SHIFT);/* 010: Form Error */ -constexpr unsigned long ESR_ACKERROR = (3 << ESR_LEC_SHIFT);/* 011: Acknowledgment Error */ -constexpr unsigned long ESR_BRECERROR = (4 << ESR_LEC_SHIFT);/* 100: Bit recessive Error */ -constexpr unsigned long ESR_BDOMERROR = (5 << ESR_LEC_SHIFT);/* 101: Bit dominant Error */ -constexpr unsigned long ESR_CRCERRPR = (6 << ESR_LEC_SHIFT);/* 110: CRC Error */ -constexpr unsigned long ESR_SWERROR = (7 << ESR_LEC_SHIFT);/* 111: Set by software */ -constexpr unsigned long ESR_TEC_SHIFT = (16); /* Bits 23-16: LS byte of the 9-bit Transmit Error Counter */ -constexpr unsigned long ESR_TEC_MASK = (0xff << ESR_TEC_SHIFT); -constexpr unsigned long ESR_REC_SHIFT = (24); /* Bits 31-24: Receive Error Counter */ -constexpr unsigned long ESR_REC_MASK = (0xff << ESR_REC_SHIFT); +constexpr unsigned long ESR_EWGF = (1U << 0); /* Bit 0: Error Warning Flag */ +constexpr unsigned long ESR_EPVF = (1U << 1); /* Bit 1: Error Passive Flag */ +constexpr unsigned long ESR_BOFF = (1U << 2); /* Bit 2: Bus-Off Flag */ +constexpr unsigned long ESR_LEC_SHIFT = (4U); /* Bits 6-4: Last Error Code */ +constexpr unsigned long ESR_LEC_MASK = (7U << ESR_LEC_SHIFT); +constexpr unsigned long ESR_NOERROR = (0U << ESR_LEC_SHIFT);/* 000: No Error */ +constexpr unsigned long ESR_STUFFERROR = (1U << ESR_LEC_SHIFT);/* 001: Stuff Error */ +constexpr unsigned long ESR_FORMERROR = (2U << ESR_LEC_SHIFT);/* 010: Form Error */ +constexpr unsigned long ESR_ACKERROR = (3U << ESR_LEC_SHIFT);/* 011: Acknowledgment Error */ +constexpr unsigned long ESR_BRECERROR = (4U << ESR_LEC_SHIFT);/* 100: Bit recessive Error */ +constexpr unsigned long ESR_BDOMERROR = (5U << ESR_LEC_SHIFT);/* 101: Bit dominant Error */ +constexpr unsigned long ESR_CRCERRPR = (6U << ESR_LEC_SHIFT);/* 110: CRC Error */ +constexpr unsigned long ESR_SWERROR = (7U << ESR_LEC_SHIFT);/* 111: Set by software */ +constexpr unsigned long ESR_TEC_SHIFT = (16U); /* Bits 23-16: LS byte of the 9-bit Transmit Error Counter */ +constexpr unsigned long ESR_TEC_MASK = (0xFFU << ESR_TEC_SHIFT); +constexpr unsigned long ESR_REC_SHIFT = (24U); /* Bits 31-24: Receive Error Counter */ +constexpr unsigned long ESR_REC_MASK = (0xFFU << ESR_REC_SHIFT); /* CAN bit timing register */ -constexpr unsigned long BTR_BRP_SHIFT = (0); /* Bits 9-0: Baud Rate Prescaler */ -constexpr unsigned long BTR_BRP_MASK = (0x03ff << BTR_BRP_SHIFT); -constexpr unsigned long BTR_TS1_SHIFT = (16); /* Bits 19-16: Time Segment 1 */ -constexpr unsigned long BTR_TS1_MASK = (0x0f << BTR_TS1_SHIFT); -constexpr unsigned long BTR_TS2_SHIFT = (20); /* Bits 22-20: Time Segment 2 */ -constexpr unsigned long BTR_TS2_MASK = (7 << BTR_TS2_SHIFT); -constexpr unsigned long BTR_SJW_SHIFT = (24); /* Bits 25-24: Resynchronization Jump Width */ -constexpr unsigned long BTR_SJW_MASK = (3 << BTR_SJW_SHIFT); -constexpr unsigned long BTR_LBKM = (1 << 30);/* Bit 30: Loop Back Mode (Debug);*/ -constexpr unsigned long BTR_SILM = (1 << 31);/* Bit 31: Silent Mode (Debug);*/ +constexpr unsigned long BTR_BRP_SHIFT = (0U); /* Bits 9-0: Baud Rate Prescaler */ +constexpr unsigned long BTR_BRP_MASK = (0x03FFU << BTR_BRP_SHIFT); +constexpr unsigned long BTR_TS1_SHIFT = (16U); /* Bits 19-16: Time Segment 1 */ +constexpr unsigned long BTR_TS1_MASK = (0x0FU << BTR_TS1_SHIFT); +constexpr unsigned long BTR_TS2_SHIFT = (20U); /* Bits 22-20: Time Segment 2 */ +constexpr unsigned long BTR_TS2_MASK = (7U << BTR_TS2_SHIFT); +constexpr unsigned long BTR_SJW_SHIFT = (24U); /* Bits 25-24: Resynchronization Jump Width */ +constexpr unsigned long BTR_SJW_MASK = (3U << BTR_SJW_SHIFT); +constexpr unsigned long BTR_LBKM = (1U << 30);/* Bit 30: Loop Back Mode (Debug);*/ +constexpr unsigned long BTR_SILM = (1U << 31);/* Bit 31: Silent Mode (Debug);*/ -constexpr unsigned long BTR_BRP_MAX = (1024); /* Maximum BTR value (without decrement);*/ -constexpr unsigned long BTR_TSEG1_MAX = (16); /* Maximum TSEG1 value (without decrement);*/ -constexpr unsigned long BTR_TSEG2_MAX = (8); /* Maximum TSEG2 value (without decrement);*/ +constexpr unsigned long BTR_BRP_MAX = (1024U); /* Maximum BTR value (without decrement);*/ +constexpr unsigned long BTR_TSEG1_MAX = (16U); /* Maximum TSEG1 value (without decrement);*/ +constexpr unsigned long BTR_TSEG2_MAX = (8U); /* Maximum TSEG2 value (without decrement);*/ /* TX mailbox identifier register */ -constexpr unsigned long TIR_TXRQ = (1 << 0); /* Bit 0: Transmit Mailbox Request */ -constexpr unsigned long TIR_RTR = (1 << 1); /* Bit 1: Remote Transmission Request */ -constexpr unsigned long TIR_IDE = (1 << 2); /* Bit 2: Identifier Extension */ -constexpr unsigned long TIR_EXID_SHIFT = (3); /* Bit 3-31: Extended Identifier */ -constexpr unsigned long TIR_EXID_MASK = (0x1fffffff << TIR_EXID_SHIFT); -constexpr unsigned long TIR_STID_SHIFT = (21); /* Bits 21-31: Standard Identifier */ -constexpr unsigned long TIR_STID_MASK = (0x07ff << TIR_STID_SHIFT); +constexpr unsigned long TIR_TXRQ = (1U << 0); /* Bit 0: Transmit Mailbox Request */ +constexpr unsigned long TIR_RTR = (1U << 1); /* Bit 1: Remote Transmission Request */ +constexpr unsigned long TIR_IDE = (1U << 2); /* Bit 2: Identifier Extension */ +constexpr unsigned long TIR_EXID_SHIFT = (3U); /* Bit 3-31: Extended Identifier */ +constexpr unsigned long TIR_EXID_MASK = (0x1FFFFFFFU << TIR_EXID_SHIFT); +constexpr unsigned long TIR_STID_SHIFT = (21U); /* Bits 21-31: Standard Identifier */ +constexpr unsigned long TIR_STID_MASK = (0x07FFU << TIR_STID_SHIFT); /* Mailbox data length control and time stamp register */ -constexpr unsigned long TDTR_DLC_SHIFT = (0); /* Bits 3:0: Data Length Code */ -constexpr unsigned long TDTR_DLC_MASK = (0x0f << TDTR_DLC_SHIFT); -constexpr unsigned long TDTR_TGT = (1 << 8); /* Bit 8: Transmit Global Time */ -constexpr unsigned long TDTR_TIME_SHIFT = (16); /* Bits 31:16: Message Time Stamp */ -constexpr unsigned long TDTR_TIME_MASK = (0xffff << TDTR_TIME_SHIFT); +constexpr unsigned long TDTR_DLC_SHIFT = (0U); /* Bits 3:0: Data Length Code */ +constexpr unsigned long TDTR_DLC_MASK = (0x0FU << TDTR_DLC_SHIFT); +constexpr unsigned long TDTR_TGT = (1U << 8); /* Bit 8: Transmit Global Time */ +constexpr unsigned long TDTR_TIME_SHIFT = (16U); /* Bits 31:16: Message Time Stamp */ +constexpr unsigned long TDTR_TIME_MASK = (0xFFFFU << TDTR_TIME_SHIFT); /* Mailbox data low register */ -constexpr unsigned long TDLR_DATA0_SHIFT = (0); /* Bits 7-0: Data Byte 0 */ -constexpr unsigned long TDLR_DATA0_MASK = (0xff << TDLR_DATA0_SHIFT); -constexpr unsigned long TDLR_DATA1_SHIFT = (8); /* Bits 15-8: Data Byte 1 */ -constexpr unsigned long TDLR_DATA1_MASK = (0xff << TDLR_DATA1_SHIFT); -constexpr unsigned long TDLR_DATA2_SHIFT = (16); /* Bits 23-16: Data Byte 2 */ -constexpr unsigned long TDLR_DATA2_MASK = (0xff << TDLR_DATA2_SHIFT); -constexpr unsigned long TDLR_DATA3_SHIFT = (24); /* Bits 31-24: Data Byte 3 */ -constexpr unsigned long TDLR_DATA3_MASK = (0xff << TDLR_DATA3_SHIFT); +constexpr unsigned long TDLR_DATA0_SHIFT = (0U); /* Bits 7-0: Data Byte 0 */ +constexpr unsigned long TDLR_DATA0_MASK = (0xFFU << TDLR_DATA0_SHIFT); +constexpr unsigned long TDLR_DATA1_SHIFT = (8U); /* Bits 15-8: Data Byte 1 */ +constexpr unsigned long TDLR_DATA1_MASK = (0xFFU << TDLR_DATA1_SHIFT); +constexpr unsigned long TDLR_DATA2_SHIFT = (16U); /* Bits 23-16: Data Byte 2 */ +constexpr unsigned long TDLR_DATA2_MASK = (0xFFU << TDLR_DATA2_SHIFT); +constexpr unsigned long TDLR_DATA3_SHIFT = (24U); /* Bits 31-24: Data Byte 3 */ +constexpr unsigned long TDLR_DATA3_MASK = (0xFFU << TDLR_DATA3_SHIFT); /* Mailbox data high register */ -constexpr unsigned long TDHR_DATA4_SHIFT = (0); /* Bits 7-0: Data Byte 4 */ -constexpr unsigned long TDHR_DATA4_MASK = (0xff << TDHR_DATA4_SHIFT); -constexpr unsigned long TDHR_DATA5_SHIFT = (8); /* Bits 15-8: Data Byte 5 */ -constexpr unsigned long TDHR_DATA5_MASK = (0xff << TDHR_DATA5_SHIFT); -constexpr unsigned long TDHR_DATA6_SHIFT = (16); /* Bits 23-16: Data Byte 6 */ -constexpr unsigned long TDHR_DATA6_MASK = (0xff << TDHR_DATA6_SHIFT); -constexpr unsigned long TDHR_DATA7_SHIFT = (24); /* Bits 31-24: Data Byte 7 */ -constexpr unsigned long TDHR_DATA7_MASK = (0xff << TDHR_DATA7_SHIFT); +constexpr unsigned long TDHR_DATA4_SHIFT = (0U); /* Bits 7-0: Data Byte 4 */ +constexpr unsigned long TDHR_DATA4_MASK = (0xFFU << TDHR_DATA4_SHIFT); +constexpr unsigned long TDHR_DATA5_SHIFT = (8U); /* Bits 15-8: Data Byte 5 */ +constexpr unsigned long TDHR_DATA5_MASK = (0xFFU << TDHR_DATA5_SHIFT); +constexpr unsigned long TDHR_DATA6_SHIFT = (16U); /* Bits 23-16: Data Byte 6 */ +constexpr unsigned long TDHR_DATA6_MASK = (0xFFU << TDHR_DATA6_SHIFT); +constexpr unsigned long TDHR_DATA7_SHIFT = (24U); /* Bits 31-24: Data Byte 7 */ +constexpr unsigned long TDHR_DATA7_MASK = (0xFFU << TDHR_DATA7_SHIFT); /* Rx FIFO mailbox identifier register */ -constexpr unsigned long RIR_RTR = (1 << 1); /* Bit 1: Remote Transmission Request */ -constexpr unsigned long RIR_IDE = (1 << 2); /* Bit 2: Identifier Extension */ -constexpr unsigned long RIR_EXID_SHIFT = (3); /* Bit 3-31: Extended Identifier */ -constexpr unsigned long RIR_EXID_MASK = (0x1fffffff << RIR_EXID_SHIFT); -constexpr unsigned long RIR_STID_SHIFT = (21); /* Bits 21-31: Standard Identifier */ -constexpr unsigned long RIR_STID_MASK = (0x07ff << RIR_STID_SHIFT); +constexpr unsigned long RIR_RTR = (1U << 1); /* Bit 1: Remote Transmission Request */ +constexpr unsigned long RIR_IDE = (1U << 2); /* Bit 2: Identifier Extension */ +constexpr unsigned long RIR_EXID_SHIFT = (3U); /* Bit 3-31: Extended Identifier */ +constexpr unsigned long RIR_EXID_MASK = (0x1FFFFFFFU << RIR_EXID_SHIFT); +constexpr unsigned long RIR_STID_SHIFT = (21U); /* Bits 21-31: Standard Identifier */ +constexpr unsigned long RIR_STID_MASK = (0x07FFU << RIR_STID_SHIFT); /* Receive FIFO mailbox data length control and time stamp register */ -constexpr unsigned long RDTR_DLC_SHIFT = (0); /* Bits 3:0: Data Length Code */ -constexpr unsigned long RDTR_DLC_MASK = (0x0f << RDTR_DLC_SHIFT); -constexpr unsigned long RDTR_FM_SHIFT = (8); /* Bits 15-8: Filter Match Index */ -constexpr unsigned long RDTR_FM_MASK = (0xff << RDTR_FM_SHIFT); -constexpr unsigned long RDTR_TIME_SHIFT = (16); /* Bits 31:16: Message Time Stamp */ -constexpr unsigned long RDTR_TIME_MASK = (0xffff << RDTR_TIME_SHIFT); +constexpr unsigned long RDTR_DLC_SHIFT = (0U); /* Bits 3:0: Data Length Code */ +constexpr unsigned long RDTR_DLC_MASK = (0x0FU << RDTR_DLC_SHIFT); +constexpr unsigned long RDTR_FM_SHIFT = (8U); /* Bits 15-8: Filter Match Index */ +constexpr unsigned long RDTR_FM_MASK = (0xFFU << RDTR_FM_SHIFT); +constexpr unsigned long RDTR_TIME_SHIFT = (16U); /* Bits 31:16: Message Time Stamp */ +constexpr unsigned long RDTR_TIME_MASK = (0xFFFFU << RDTR_TIME_SHIFT); /* Receive FIFO mailbox data low register */ -constexpr unsigned long RDLR_DATA0_SHIFT = (0); /* Bits 7-0: Data Byte 0 */ -constexpr unsigned long RDLR_DATA0_MASK = (0xff << RDLR_DATA0_SHIFT); -constexpr unsigned long RDLR_DATA1_SHIFT = (8); /* Bits 15-8: Data Byte 1 */ -constexpr unsigned long RDLR_DATA1_MASK = (0xff << RDLR_DATA1_SHIFT); -constexpr unsigned long RDLR_DATA2_SHIFT = (16); /* Bits 23-16: Data Byte 2 */ -constexpr unsigned long RDLR_DATA2_MASK = (0xff << RDLR_DATA2_SHIFT); -constexpr unsigned long RDLR_DATA3_SHIFT = (24); /* Bits 31-24: Data Byte 3 */ -constexpr unsigned long RDLR_DATA3_MASK = (0xff << RDLR_DATA3_SHIFT); +constexpr unsigned long RDLR_DATA0_SHIFT = (0U); /* Bits 7-0: Data Byte 0 */ +constexpr unsigned long RDLR_DATA0_MASK = (0xFFU << RDLR_DATA0_SHIFT); +constexpr unsigned long RDLR_DATA1_SHIFT = (8U); /* Bits 15-8: Data Byte 1 */ +constexpr unsigned long RDLR_DATA1_MASK = (0xFFU << RDLR_DATA1_SHIFT); +constexpr unsigned long RDLR_DATA2_SHIFT = (16U); /* Bits 23-16: Data Byte 2 */ +constexpr unsigned long RDLR_DATA2_MASK = (0xFFU << RDLR_DATA2_SHIFT); +constexpr unsigned long RDLR_DATA3_SHIFT = (24U); /* Bits 31-24: Data Byte 3 */ +constexpr unsigned long RDLR_DATA3_MASK = (0xFFU << RDLR_DATA3_SHIFT); /* Receive FIFO mailbox data high register */ -constexpr unsigned long RDHR_DATA4_SHIFT = (0); /* Bits 7-0: Data Byte 4 */ -constexpr unsigned long RDHR_DATA4_MASK = (0xff << RDHR_DATA4_SHIFT); -constexpr unsigned long RDHR_DATA5_SHIFT = (8); /* Bits 15-8: Data Byte 5 */ -constexpr unsigned long RDHR_DATA5_MASK = (0xff << RDHR_DATA5_SHIFT); -constexpr unsigned long RDHR_DATA6_SHIFT = (16); /* Bits 23-16: Data Byte 6 */ -constexpr unsigned long RDHR_DATA6_MASK = (0xff << RDHR_DATA6_SHIFT); -constexpr unsigned long RDHR_DATA7_SHIFT = (24); /* Bits 31-24: Data Byte 7 */ -constexpr unsigned long RDHR_DATA7_MASK = (0xff << RDHR_DATA7_SHIFT); +constexpr unsigned long RDHR_DATA4_SHIFT = (0U); /* Bits 7-0: Data Byte 4 */ +constexpr unsigned long RDHR_DATA4_MASK = (0xFFU << RDHR_DATA4_SHIFT); +constexpr unsigned long RDHR_DATA5_SHIFT = (8U); /* Bits 15-8: Data Byte 5 */ +constexpr unsigned long RDHR_DATA5_MASK = (0xFFU << RDHR_DATA5_SHIFT); +constexpr unsigned long RDHR_DATA6_SHIFT = (16U); /* Bits 23-16: Data Byte 6 */ +constexpr unsigned long RDHR_DATA6_MASK = (0xFFU << RDHR_DATA6_SHIFT); +constexpr unsigned long RDHR_DATA7_SHIFT = (24U); /* Bits 31-24: Data Byte 7 */ +constexpr unsigned long RDHR_DATA7_MASK = (0xFFU << RDHR_DATA7_SHIFT); /* CAN filter master register */ -constexpr unsigned long FMR_FINIT = (1 << 0); /* Bit 0: Filter Init Mode */ +constexpr unsigned long FMR_FINIT = (1U << 0); /* Bit 0: Filter Init Mode */ } } diff --git a/libuavcan_drivers/stm32/driver/include/uavcan_stm32/clock.hpp b/libuavcan_drivers/stm32/driver/include/uavcan_stm32/clock.hpp index d4afa07e5f..1af0daefd3 100644 --- a/libuavcan_drivers/stm32/driver/include/uavcan_stm32/clock.hpp +++ b/libuavcan_drivers/stm32/driver/include/uavcan_stm32/clock.hpp @@ -41,11 +41,11 @@ void adjustUtc(uavcan::UtcDuration adjustment); */ struct UtcSyncParams { - float offset_p = 0.01; ///< PPM per one usec error - float rate_i = 0.02; ///< PPM per one PPM error for second - float rate_error_corner_freq = 0.01; - float max_rate_correction_ppm = 300; - float lock_thres_rate_ppm = 2.0; + float offset_p = 0.01F; ///< PPM per one usec error + float rate_i = 0.02F; ///< PPM per one PPM error for second + float rate_error_corner_freq = 0.01F; + float max_rate_correction_ppm = 300.0F; + float lock_thres_rate_ppm = 2.0F; uavcan::UtcDuration lock_thres_offset = uavcan::UtcDuration::fromMSec(4); uavcan::UtcDuration min_jump = uavcan::UtcDuration::fromMSec(10); ///< Min error to jump rather than change rate }; diff --git a/libuavcan_drivers/stm32/driver/src/uc_stm32_can.cpp b/libuavcan_drivers/stm32/driver/src/uc_stm32_can.cpp index 3b2b5ce7da..63a29c4cc9 100644 --- a/libuavcan_drivers/stm32/driver/src/uc_stm32_can.cpp +++ b/libuavcan_drivers/stm32/driver/src/uc_stm32_can.cpp @@ -182,11 +182,11 @@ int CanIface::computeTimings(const uavcan::uint32_t target_bitrate, Timings& out while (1) { - prescaler = prescaler_bs / (1 + bs1 + bs2); + prescaler = uavcan::uint16_t(prescaler_bs / unsigned(1 + bs1 + bs2)); // Check result: if ((prescaler >= 1) && (prescaler <= 1024)) { - const uavcan::uint32_t current_bitrate = pclk / (prescaler * (1 + bs1 + bs2)); + const uavcan::uint32_t current_bitrate = pclk / (prescaler * unsigned(1 + bs1 + bs2)); if (current_bitrate == target_bitrate) { break; @@ -209,10 +209,10 @@ int CanIface::computeTimings(const uavcan::uint32_t target_bitrate, Timings& out { return -1; } - out_timings.prescaler = prescaler - 1; + out_timings.prescaler = uavcan::uint16_t(prescaler - 1U); out_timings.sjw = 1; - out_timings.bs1 = bs1 - 1; - out_timings.bs2 = bs2 - 1; + out_timings.bs1 = uavcan::uint8_t(bs1 - 1); + out_timings.bs2 = uavcan::uint8_t(bs2 - 1); return 0; } @@ -365,10 +365,10 @@ int CanIface::init(uavcan::uint32_t bitrate) can_->MCR = bxcan::MCR_ABOM | bxcan::MCR_AWUM | bxcan::MCR_INRQ; // RM page 648 - can_->BTR = ((timings.sjw & 3) << 24) | - ((timings.bs1 & 15) << 16) | - ((timings.bs2 & 7) << 20) | - (timings.prescaler & 1023); + can_->BTR = ((timings.sjw & 3U) << 24) | + ((timings.bs1 & 15U) << 16) | + ((timings.bs2 & 7U) << 20) | + (timings.prescaler & 1023U); can_->IER = bxcan::IER_TMEIE | // TX mailbox empty bxcan::IER_FMPIE0 | // RX FIFO 0 is not empty @@ -419,7 +419,7 @@ leave: void CanIface::pollErrorState() { - const uavcan::uint8_t lec = (can_->ESR & bxcan::ESR_LEC_MASK) >> bxcan::ESR_LEC_SHIFT; + const uavcan::uint8_t lec = uavcan::uint8_t((can_->ESR & bxcan::ESR_LEC_MASK) >> bxcan::ESR_LEC_SHIFT); if (lec != 0) { last_hw_error_code_ = lec; @@ -513,14 +513,14 @@ void CanIface::handleRxInterrupt(uavcan::uint8_t fifo_index, uavcan::uint64_t ut frame.dlc = rf.RDTR & 15; - frame.data[0] = 0xFF & (rf.RDLR >> 0); - frame.data[1] = 0xFF & (rf.RDLR >> 8); - frame.data[2] = 0xFF & (rf.RDLR >> 16); - frame.data[3] = 0xFF & (rf.RDLR >> 24); - frame.data[4] = 0xFF & (rf.RDHR >> 0); - frame.data[5] = 0xFF & (rf.RDHR >> 8); - frame.data[6] = 0xFF & (rf.RDHR >> 16); - frame.data[7] = 0xFF & (rf.RDHR >> 24); + frame.data[0] = uavcan::uint8_t(0xFF & (rf.RDLR >> 0)); + frame.data[1] = uavcan::uint8_t(0xFF & (rf.RDLR >> 8)); + frame.data[2] = uavcan::uint8_t(0xFF & (rf.RDLR >> 16)); + frame.data[3] = uavcan::uint8_t(0xFF & (rf.RDLR >> 24)); + frame.data[4] = uavcan::uint8_t(0xFF & (rf.RDHR >> 0)); + frame.data[5] = uavcan::uint8_t(0xFF & (rf.RDHR >> 8)); + frame.data[6] = uavcan::uint8_t(0xFF & (rf.RDHR >> 16)); + frame.data[7] = uavcan::uint8_t(0xFF & (rf.RDHR >> 24)); *rfr_reg = bxcan::RFR_RFOM | bxcan::RFR_FOVR | bxcan::RFR_FULL; // Release FIFO entry we just read diff --git a/libuavcan_drivers/stm32/driver/src/uc_stm32_clock.cpp b/libuavcan_drivers/stm32/driver/src/uc_stm32_clock.cpp index b12b86852e..b5ce28cd7c 100644 --- a/libuavcan_drivers/stm32/driver/src/uc_stm32_clock.cpp +++ b/libuavcan_drivers/stm32/driver/src/uc_stm32_clock.cpp @@ -99,7 +99,9 @@ static uavcan::uint64_t sampleUtcFromCriticalSection() if (TIMX->SR & TIM_SR_UIF) { cnt = TIMX->CNT; - time += USecPerOverflow + (utc_accumulated_correction_nsec + utc_correction_nsec_per_overflow) / 1000; + const uavcan::int32_t add = uavcan::int32_t(USecPerOverflow) + + (utc_accumulated_correction_nsec + utc_correction_nsec_per_overflow) / 1000; + time = uavcan::uint64_t(uavcan::int64_t(time) + add); } return time + cnt; } @@ -156,9 +158,9 @@ static float lowpass(float xold, float xnew, float corner, float dt) static void updateRatePID(uavcan::UtcDuration adjustment) { const uavcan::MonotonicTime ts = getMonotonic(); - const float dt = (ts - prev_utc_adj_at).toUSec() / 1e6F; + const float dt = float((ts - prev_utc_adj_at).toUSec()) / 1e6F; prev_utc_adj_at = ts; - const float adj_usec = adjustment.toUSec(); + const float adj_usec = float(adjustment.toUSec()); /* * Target relative rate in PPM @@ -196,7 +198,7 @@ static void updateRatePID(uavcan::UtcDuration adjustment) total_rate_correction_ppm = uavcan::max(total_rate_correction_ppm, -utc_sync_params.max_rate_correction_ppm); total_rate_correction_ppm = uavcan::min(total_rate_correction_ppm, utc_sync_params.max_rate_correction_ppm); - utc_correction_nsec_per_overflow = (USecPerOverflow * 1000) * (total_rate_correction_ppm / 1e6F); + utc_correction_nsec_per_overflow = uavcan::int32_t((USecPerOverflow * 1000) * (total_rate_correction_ppm / 1e6F)); // lowsyslog("$ adj=%f rel_rate=%f rel_rate_eint=%f tgt_rel_rate=%f ppm=%f\n", // adj_usec, utc_rel_rate_ppm, utc_rel_rate_error_integral, target_rel_rate_ppm, total_rate_correction_ppm); @@ -219,7 +221,7 @@ void adjustUtc(uavcan::UtcDuration adjustment) } else { - time_utc += adj_usec; + time_utc = uavcan::uint64_t(uavcan::int64_t(time_utc) + adj_usec); } } @@ -245,7 +247,7 @@ void adjustUtc(uavcan::UtcDuration adjustment) float getUtcRateCorrectionPPM() { MutexLocker mlocker(mutex); - const float rate_correction_mult = utc_correction_nsec_per_overflow / float(USecPerOverflow * 1000); + const float rate_correction_mult = float(utc_correction_nsec_per_overflow) / float(USecPerOverflow * 1000); return 1e6F * rate_correction_mult; } @@ -320,7 +322,7 @@ UAVCAN_STM32_IRQ_HANDLER(TIMX_IRQHandler) utc_accumulated_correction_nsec += utc_correction_nsec_per_overflow; if (std::abs(utc_accumulated_correction_nsec) >= 1000) { - time_utc += utc_accumulated_correction_nsec / 1000; + time_utc = uavcan::uint64_t(uavcan::int64_t(time_utc) + utc_accumulated_correction_nsec / 1000); utc_accumulated_correction_nsec %= 1000; }