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git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@5145 7fd9a85b-ad96-42d3-883c-3090e2eb8679
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patacongo
2012-09-13 18:32:24 +00:00
parent 2cb5c82c18
commit 84cfa6fceb
1820 changed files with 27052 additions and 27051 deletions
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nuttx/arch/arm/src/arm/arm.h
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* arch/arm/src/arm/arm.h
*
* Copyright (C) 2007-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/arm/pg_macros.h
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@@ -2,7 +2,7 @@
* arch/arm/src/arm/pg_macros.h
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/arm/up_allocpage.c
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@@ -3,7 +3,7 @@
* Allocate a new page and map it to the fault address of a task.
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/arm/up_assert.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/arm/up_assert.c
*
* Copyright (C) 2007-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/arm/up_blocktask.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/arm/up_blocktask.c
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/arm/up_cache.S
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/arm/up_cache.S
*
* Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/arm/up_checkmapping.c
+1 -1
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@@ -4,7 +4,7 @@
* address space.
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/arm/up_copystate.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/arm/up_copystate.c
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/arm/up_dataabort.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/arm/up_dataabort.c
*
* Copyright (C) 2007-2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/arm/up_doirq.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/arm/up_doirq.c
*
* Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/arm/up_fullcontextrestore.S
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/arm/up_fullcontextrestore.S
*
* Copyright (C) 2007, 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/arm/up_head.S
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/arm/up_head.S
*
* Copyright (C) 2007, 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/arm/up_initialstate.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/arm/up_initialstate.c
*
* Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/arm/up_pginitialize.c
+1 -1
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@@ -3,7 +3,7 @@
* Initialize the MMU for on-demand paging support.
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/arm/up_prefetchabort.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/src/up_prefetchabort.c
*
* Copyright (C) 2007-2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/arm/up_releasepending.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/arm/up_releasepending.c
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/arm/up_reprioritizertr.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/arm/up_reprioritizertr.c
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/arm/up_saveusercontext.S
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/arm/up_saveusercontext.S
*
* Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/arm/up_schedulesigaction.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/arm/up_schedulesigaction.c
*
* Copyright (C) 2007-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/arm/up_sigdeliver.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/arm/up_sigdeliver.c
*
* Copyright (C) 2007-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/arm/up_syscall.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/arm/up_syscall.c
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/arm/up_unblocktask.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/arm/up_unblocktask.c
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/arm/up_undefinedinsn.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/arm/up_undefinedinsn.c
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/arm/up_va2pte.c
+1 -1
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@@ -3,7 +3,7 @@
* Utility to map a virtual address to a L2 page table entry.
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/arm/up_vectoraddrexcptn.S
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/src/up_vectoraddrexceptn.S
*
* Copyright (C) 2008-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/arm/up_vectors.S
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/arm/up_vectors.S
*
* Copyright (C) 2007-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/arm/up_vectortab.S
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/arm/up_vectortab.S
*
* Copyright (C) 2007, 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/armv7-m/psr.h
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/armv7-m/psr.h
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/armv7-m/svcall.h
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/armv7-m/svcall.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/armv7-m/up_assert.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/armv7-m/up_assert.c
*
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/armv7-m/up_copystate.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/armv7-m/up_copystate.c
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/armv7-m/up_doirq.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/armv7-m/up_doirq.c
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/armv7-m/up_hardfault.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/armv7-m/up_hardfault.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/armv7-m/up_memfault.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/armv7-m/up_memfault.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/armv7-m/up_mpu.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/armv7-m/up_mpu.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/armv7-m/up_saveusercontext.S
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/armv7-m/up_saveusercontext.S
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/armv7-m/up_sigdeliver.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/armv7-m/up_sigdeliver.c
*
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/armv7-m/up_switchcontext.S
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/armv7-m/up_switchcontext.S
*
* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/c5471/Make.defs
+1 -1
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@@ -2,7 +2,7 @@
# c5471/Make.defs
#
# Copyright (C) 2007 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <spudmonkey@racsa.co.cr>
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
nuttx/arch/arm/src/c5471/c5471_ethernet.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/c5471/c5471_ethernet.c
*
* Copyright (C) 2007, 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Based one a C5471 Linux driver and released under this BSD license with
* special permisson from the copyright holder of the Linux driver:
nuttx/arch/arm/src/c5471/c5471_lowputc.S
+1 -1
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@@ -2,7 +2,7 @@
* c5471/c5471_lowputc.S
*
* Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/c5471/c5471_timerisr.c
+1 -1
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@@ -2,7 +2,7 @@
* c5471/c5471_timerisr.c
*
* Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/c5471/c5471_vectors.S
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/c5471/c5471_vectors.S
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/c5471/chip.h
+1 -1
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@@ -2,7 +2,7 @@
* c5471/chip.h
*
* Copyright (C) 2007 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/calypso/Make.defs
+1 -1
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@@ -2,7 +2,7 @@
# calypso/Make.defs
#
# Copyright (C) 2007 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <spudmonkey@racsa.co.cr>
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Copyright (C) 2011 Stefan Richter. All rights reserved.
# Author: Stefan Richter <ichgeh@l--putt.de>
nuttx/arch/arm/src/calypso/calypso_lowputc.S
+1 -1
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@@ -6,7 +6,7 @@
*
* based on: c5471/c5471_lowputc.S
* Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/calypso/calypso_serial.c
+1 -1
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@@ -6,7 +6,7 @@
*
* based on c5471/c5471_serial.c
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/calypso/chip.h
+1 -1
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@@ -6,7 +6,7 @@
*
* based on: c5471/chip.h
* Copyright (C) 2007 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/common/up_allocateheap.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/common/up_allocateheap.c
*
* Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/common/up_arch.h
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/common/up_arch.h
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/common/up_checkstack.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/common/up_checkstack.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/common/up_etherstub.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/common/up_etherstub.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/common/up_idle.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/common/up_idle.c
*
* Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/common/up_interruptcontext.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/common/up_interruptcontext.c
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/common/up_lowputs.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/common/up_lowputs.c
*
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/common/up_mdelay.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/common/up_mdelay.c
*
* Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/common/up_modifyreg16.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/common/up_modifyreg16.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/common/up_modifyreg32.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/common/up_modifyreg32.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/common/up_modifyreg8.c
+1 -1
View File
@@ -2,7 +2,7 @@
* arch/arm/src/common/up_modifyreg8.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/common/up_puts.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/common/up_puts.c
*
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/common/up_releasestack.c
+1 -1
View File
@@ -2,7 +2,7 @@
* arch/arm/src/common/up_releasestack.c
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/common/up_udelay.c
+1 -1
View File
@@ -2,7 +2,7 @@
* arch/arm/src/common/up_udelay.c
*
* Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/common/up_usestack.c
+1 -1
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@@ -2,7 +2,7 @@
* arch/arm/src/common/up_usestack.c
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/dm320/Make.defs
+1 -1
View File
@@ -2,7 +2,7 @@
# dm320/Make.defs
#
# Copyright (C) 2007, 2010 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <spudmonkey@racsa.co.cr>
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
nuttx/arch/arm/src/dm320/chip.h
+1 -1
View File
@@ -2,7 +2,7 @@
* arch/arm/src/dm320/chip.h
*
* Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/dm320/dm320_ahb.h
+1 -1
View File
@@ -2,7 +2,7 @@
* dm320/dm320_uart.h
*
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/dm320/dm320_allocateheap.c
+1 -1
View File
@@ -2,7 +2,7 @@
* dm320/dm320_allocateheap.c
*
* Copyright (C) 2007 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/dm320/dm320_busc.h
+1 -1
View File
@@ -2,7 +2,7 @@
* dm320/dm320_busc.h
*
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/dm320/dm320_clkc.h
+1 -1
View File
@@ -2,7 +2,7 @@
* dm320/dm320_clkc.h
*
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/dm320/dm320_decodeirq.c
+1 -1
View File
@@ -3,7 +3,7 @@
* arch/arm/src/chip/dm320_decodeirq.c
*
* Copyright (C) 2007, 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/dm320/dm320_emif.h
+1 -1
View File
@@ -2,7 +2,7 @@
* dm320/dm320_emif.h
*
* Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/dm320/dm320_framebuffer.c
+1 -1
View File
@@ -2,7 +2,7 @@
* arch/arm/src/dm320/dm320_framebuffer.c
*
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/dm320/dm320_gio.h
+1 -1
View File
@@ -2,7 +2,7 @@
* dm320/dm320_gio.h
*
* Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/dm320/dm320_intc.h
+1 -1
View File
@@ -2,7 +2,7 @@
* dm320/dm320_intc.h
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/dm320/dm320_lowputc.S
+1 -1
View File
@@ -3,7 +3,7 @@
* arch/arm/src/chip/dm320_lowputc.S
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/dm320/dm320_memorymap.h
+1 -1
View File
@@ -2,7 +2,7 @@
* dm320/dm320_memorymap.h
*
* Copyright (C) 2007, 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/dm320/dm320_osd.h
+1 -1
View File
@@ -2,7 +2,7 @@
* dm320/dm320_osd.h
*
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/dm320/dm320_restart.S
+1 -1
View File
@@ -2,7 +2,7 @@
* arch/arm/src/dm320/dm320_restart.S
*
* Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/dm320/dm320_timer.h
+1 -1
View File
@@ -2,7 +2,7 @@
* dm320/dm320_timer.h
*
* Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/dm320/dm320_timerisr.c
+1 -1
View File
@@ -3,7 +3,7 @@
* arch/arm/src/chip/dm320_timerisr.c
*
* Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/dm320/dm320_uart.h
+1 -1
View File
@@ -2,7 +2,7 @@
* dm320/dm320_uart.h
*
* Copyright (C) 2007, 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/dm320/dm320_usb.h
+1 -1
View File
@@ -2,7 +2,7 @@
* dm320/dm320_uart.h
*
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/imx/Make.defs
+1 -1
View File
@@ -2,7 +2,7 @@
# arch/arm/src/imx/Make.defs
#
# Copyright (C) 2009 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <spudmonkey@racsa.co.cr>
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
nuttx/arch/arm/src/imx/chip.h
+1 -1
View File
@@ -2,7 +2,7 @@
* arch/arm/src/imx/chip.h
*
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/imx/imx_aitc.h
+1 -1
View File
@@ -2,7 +2,7 @@
* arch/arm/src/imx/imx_aitc.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/imx/imx_allocateheap.c
+1 -1
View File
@@ -3,7 +3,7 @@
* arch/arm/src/chip/imx_allocateheap.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/imx/imx_cspi.h
+1 -1
View File
@@ -2,7 +2,7 @@
* arch/arm/src/imx/imx_cspi.h
*
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/imx/imx_decodeirq.c
+1 -1
View File
@@ -3,7 +3,7 @@
* arch/arm/src/chip/imx_decodeirq.c
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/imx/imx_dma.h
+250 -250
View File
@@ -1,250 +1,250 @@
/************************************************************************************
* arch/arm/src/imx/imx_dma.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_IMX_DMA_H
#define __ARCH_ARM_IMX_DMA_H
/************************************************************************************
* Included Files
************************************************************************************/
/************************************************************************************
* Definitions
************************************************************************************/
/* DMA Register Offsets *************************************************************/
#define DMA_SYS_OFFSET 0x0000
#define DMA_M2D_OFFSET 0x0040
#define DMA_CH0_OFFSET 0x0080
#define DMA_CH1_OFFSET 0x00c0
#define DMA_CH2_OFFSET 0x0100
#define DMA_CH3_OFFSET 0x0140
#define DMA_CH4_OFFSET 0x0180
#define DMA_CH5_OFFSET 0x01C0
#define DMA_CH6_OFFSET 0x0200
#define DMA_CH7_OFFSET 0x0240
#define DMA_CH8_OFFSET 0x0280
#define DMA_CH9_OFFSET 0x02c0
#define DMA_CH10_OFFSET 0x0300
#define DMA_CH_OFFSET(n) (DMA_CH0_OFFSET + (n)*0x0040)
#define DMA_TST_OFFSET 0x0340
#define DMA_DCR_OFFSET 0x0000
#define DMA_ISR_OFFSET 0x0004
#define DMA_IMR_OFFSET 0x0008
#define DMA_BTOSR_OFFSET 0x000c
#define DMA_RTOSR_OFFSET 0x0010
#define DMA_TESR_OFFSET 0x0014
#define DMA_BOSR_OFFSET 0x0018
#define DMA_BTOCR_OFFSET 0x001c
#define DMA_WSRA_OFFSET 0x0000
#define DMA_XSRA_OFFSET 0x0004
#define DMA_YSRA_OFFSET 0x0008
#define DMA_WSRB_OFFSET 0x000c
#define DMA_XSRB_OFFSET 0x0010
#define DMA_YSRB_OFFSET 0x0014
#define DMA_SAR_OFFSET 0x0000
#define DMA_DAR_OFFSET 0x0004
#define DMA_CNTR_OFFSET 0x0008
#define DMA_CCR_OFFSET 0x000c
#define DMA_RSSR_OFFSET 0x0010
#define DMA_BLR_OFFSET 0x0014
#define DMA_RTOR_OFFSET 0x0018
#define DMA_BUCR_OFFSET 0x0018
#define DMA_TCR_OFFSET 0x0000
#define DMA_TFIFOA_OFFSET 0x0004
#define DMA_TDRR_OFFSET 0x0008
#define DMA_TDIPR_OFFSET 0x000c
#define DMA_TFIFOB_OFFSET 0x0010
/* DMA Register Addresses ***********************************************************/
#define IMX_DMA_SYS_BASE (IMX_DMA_VBASE + DMA_SYS_OFFSET)
#define IMX_DMA_M2D_BASE (IMX_DMA_VBASE + DMA_M2D_OFFSET)
#define IMX_DMA_CH0_BASE (IMX_DMA_VBASE + DMA_CH0_OFFSET)
#define IMX_DMA_CH1_BASE (IMX_DMA_VBASE + DMA_CH1_OFFSET)
#define IMX_DMA_CH2_BASE (IMX_DMA_VBASE + DMA_CH2_OFFSET)
#define IMX_DMA_CH3_BASE (IMX_DMA_VBASE + DMA_CH3_OFFSET)
#define IMX_DMA_CH4_BASE (IMX_DMA_VBASE + DMA_CH4_OFFSET)
#define IMX_DMA_CH5_BASE (IMX_DMA_VBASE + DMA_CH5_OFFSET)
#define IMX_DMA_CH6_BASE (IMX_DMA_VBASE + DMA_CH6_OFFSET)
#define IMX_DMA_CH7_BASE (IMX_DMA_VBASE + DMA_CH7_OFFSET)
#define IMX_DMA_CH8_BASE (IMX_DMA_VBASE + DMA_CH8_OFFSET)
#define IMX_DMA_CH9_BASE (IMX_DMA_VBASE + DMA_CH9_OFFSET)
#define IMX_DMA_CH10_BASE (IMX_DMA_VBASE + DMA_CH10_OFFSET)
#define IMX_DMA_CH_BASE(n) (IMX_DMA_VBASE + DMA_CH_OFFSET(n))
#define IMX_DMA_TST_BASE (IMX_DMA_VBASE + DMA_TST_OFFSET)
#define IMX_DMA_DCR (DMA_SYS_BASE + DMA_DCR_OFFSET)
#define IMX_DMA_ISR (DMA_SYS_BASE + DMA_ISR_OFFSET)
#define IMX_DMA_IMR (DMA_SYS_BASE + DMA_IMR_OFFSET)
#define IMX_DMA_BTOSR (DMA_SYS_BASE + DMA_BTOSR_OFFSET)
#define IMX_DMA_RTOSR (DMA_SYS_BASE + DMA_RTOSR_OFFSET)
#define IMX_DMA_TESR (DMA_SYS_BASE + DMA_TESR_OFFSET)
#define IMX_DMA_BOSR (DMA_SYS_BASE + DMA_BOSR_OFFSET)
#define IMX_DMA_BTOCR (DMA_SYS_BASE + DMA_BTOCR_OFFSET)
#define IMX_DMA_WSRA (DMA_M2D_BASE + DMA_WSRA_OFFSET)
#define IMX_DMA_XSRA (DMA_M2D_BASE + DMA_XSRA_OFFSET)
#define IMX_DMA_YSRA (DMA_M2D_BASE + DMA_YSRA_OFFSET)
#define IMX_DMA_WSRB (DMA_M2D_BASE + DMA_WSRB_OFFSET)
#define IMX_DMA_XSRB (DMA_M2D_BASE + DMA_XSRB_OFFSET)
#define IMX_DMA_YSRB (DMA_M2D_BASE + DMA_YSRB_OFFSET)
#define IMX_DMA_SAR0 (DMA_CH0_BASE + DMA_SAR_OFFSET)
#define IMX_DMA_DAR0 (DMA_CH0_BASE + DMA_DAR_OFFSET)
#define IMX_DMA_CNTR0 (DMA_CH0_BASE + DMA_CNTR_OFFSET)
#define IMX_DMA_CCR0 (DMA_CH0_BASE + DMA_CCR_OFFSET)
#define IMX_DMA_RSSR0 (DMA_CH0_BASE + DMA_RSSR_OFFSET)
#define IMX_DMA_BLR0 (DMA_CH0_BASE + DMA_BLR_OFFSET)
#define IMX_DMA_RTOR0 (DMA_CH0_BASE + DMA_RTOR_OFFSET)
#define IMX_DMA_BUCR0 (DMA_CH0_BASE + DMA_BUCR_OFFSET)
#define IMX_DMA_SAR1 (DMA_CH1_BASE + DMA_SAR_OFFSET)
#define IMX_DMA_DAR1 (DMA_CH1_BASE + DMA_DAR_OFFSET)
#define IMX_DMA_CNTR1 (DMA_CH1_BASE + DMA_CNTR_OFFSET)
#define IMX_DMA_CCR1 (DMA_CH1_BASE + DMA_CCR_OFFSET)
#define IMX_DMA_RSSR1 (DMA_CH1_BASE + DMA_RSSR_OFFSET)
#define IMX_DMA_BLR1 (DMA_CH1_BASE + DMA_BLR_OFFSET)
#define IMX_DMA_RTOR1 (DMA_CH1_BASE + DMA_RTOR_OFFSET)
#define IMX_DMA_BUCR1 (DMA_CH1_BASE + DMA_BUCR_OFFSET)
#define IMX_DMA_SAR2 (DMA_CH2_BASE + DMA_SAR_OFFSET)
#define IMX_DMA_DAR2 (DMA_CH2_BASE + DMA_DAR_OFFSET)
#define IMX_DMA_CNTR2 (DMA_CH2_BASE + DMA_CNTR_OFFSET)
#define IMX_DMA_CCR2 (DMA_CH2_BASE + DMA_CCR_OFFSET)
#define IMX_DMA_RSSR2 (DMA_CH2_BASE + DMA_RSSR_OFFSET)
#define IMX_DMA_BLR2 (DMA_CH2_BASE + DMA_BLR_OFFSET)
#define IMX_DMA_RTOR2 (DMA_CH2_BASE + DMA_RTOR_OFFSET)
#define IMX_DMA_BUCR2 (DMA_CH2_BASE + DMA_BUCR_OFFSET)
#define IMX_DMA_SAR3 (DMA_CH3_BASE + DMA_SAR_OFFSET)
#define IMX_DMA_DAR3 (DMA_CH3_BASE + DMA_DAR_OFFSET)
#define IMX_DMA_CNTR3 (DMA_CH3_BASE + DMA_CNTR_OFFSET)
#define IMX_DMA_CCR3 (DMA_CH3_BASE + DMA_CCR_OFFSET)
#define IMX_DMA_RSSR3 (DMA_CH3_BASE + DMA_RSSR_OFFSET)
#define IMX_DMA_BLR3 (DMA_CH3_BASE + DMA_BLR_OFFSET)
#define IMX_DMA_RTOR3 (DMA_CH3_BASE + DMA_RTOR_OFFSET)
#define IMX_DMA_BUCR3 (DMA_CH3_BASE + DMA_BUCR_OFFSET)
#define IMX_DMA_SAR4 (DMA_CH4_BASE + DMA_SAR_OFFSET)
#define IMX_DMA_DAR4 (DMA_CH4_BASE + DMA_DAR_OFFSET)
#define IMX_DMA_CNTR4 (DMA_CH4_BASE + DMA_CNTR_OFFSET)
#define IMX_DMA_CCR4 (DMA_CH4_BASE + DMA_CCR_OFFSET)
#define IMX_DMA_RSSR4 (DMA_CH4_BASE + DMA_RSSR_OFFSET)
#define IMX_DMA_BLR4 (DMA_CH4_BASE + DMA_BLR_OFFSET)
#define IMX_DMA_RTOR4 (DMA_CH4_BASE + DMA_RTOR_OFFSET)
#define IMX_DMA_BUCR4 (DMA_CH4_BASE + DMA_BUCR_OFFSET)
#define IMX_DMA_SAR5 (DMA_CH5_BASE + DMA_SAR_OFFSET)
#define IMX_DMA_DAR5 (DMA_CH5_BASE + DMA_DAR_OFFSET)
#define IMX_DMA_CNTR5 (DMA_CH5_BASE + DMA_CNTR_OFFSET)
#define IMX_DMA_CCR5 (DMA_CH5_BASE + DMA_CCR_OFFSET)
#define IMX_DMA_RSSR5 (DMA_CH5_BASE + DMA_RSSR_OFFSET)
#define IMX_DMA_BLR5 (DMA_CH5_BASE + DMA_BLR_OFFSET)
#define IMX_DMA_RTOR5 (DMA_CH5_BASE + DMA_RTOR_OFFSET)
#define IMX_DMA_BUCR5 (DMA_CH5_BASE + DMA_BUCR_OFFSET)
#define IMX_DMA_SAR6 (DMA_CH6_BASE + DMA_SAR_OFFSET)
#define IMX_DMA_DAR6 (DMA_CH6_BASE + DMA_DAR_OFFSET)
#define IMX_DMA_CNTR6 (DMA_CH6_BASE + DMA_CNTR_OFFSET)
#define IMX_DMA_CCR6 (DMA_CH6_BASE + DMA_CCR_OFFSET)
#define IMX_DMA_RSSR6 (DMA_CH6_BASE + DMA_RSSR_OFFSET)
#define IMX_DMA_BLR6 (DMA_CH6_BASE + DMA_BLR_OFFSET)
#define IMX_DMA_RTOR6 (DMA_CH6_BASE + DMA_RTOR_OFFSET)
#define IMX_DMA_BUCR6 (DMA_CH6_BASE + DMA_BUCR_OFFSET)
#define IMX_DMA_SAR7 (DMA_CH7_BASE + DMA_SAR_OFFSET)
#define IMX_DMA_DAR7 (DMA_CH7_BASE + DMA_DAR_OFFSET)
#define IMX_DMA_CNTR7 (DMA_CH7_BASE + DMA_CNTR_OFFSET)
#define IMX_DMA_CCR7 (DMA_CH7_BASE + DMA_CCR_OFFSET)
#define IMX_DMA_RSSR7 (DMA_CH7_BASE + DMA_RSSR_OFFSET)
#define IMX_DMA_BLR7 (DMA_CH7_BASE + DMA_BLR_OFFSET)
#define IMX_DMA_RTOR7 (DMA_CH7_BASE + DMA_RTOR_OFFSET)
#define IMX_DMA_BUCR7 (DMA_CH7_BASE + DMA_BUCR_OFFSET)
#define IMX_DMA_SAR8 (DMA_CH8_BASE + DMA_SAR_OFFSET)
#define IMX_DMA_DAR8 (DMA_CH8_BASE + DMA_DAR_OFFSET)
#define IMX_DMA_CNTR8 (DMA_CH8_BASE + DMA_CNTR_OFFSET)
#define IMX_DMA_CCR8 (DMA_CH8_BASE + DMA_CCR_OFFSET)
#define IMX_DMA_RSSR8 (DMA_CH8_BASE + DMA_RSSR_OFFSET)
#define IMX_DMA_BLR8 (DMA_CH8_BASE + DMA_BLR_OFFSET)
#define IMX_DMA_RTOR8 (DMA_CH8_BASE + DMA_RTOR_OFFSET)
#define IMX_DMA_BUCR8 (DMA_CH8_BASE + DMA_BUCR_OFFSET)
#define IMX_DMA_SAR9 (DMA_CH9_BASE + DMA_SAR_OFFSET)
#define IMX_DMA_DAR9 (DMA_CH9_BASE + DMA_DAR_OFFSET)
#define IMX_DMA_CNTR9 (DMA_CH9_BASE + DMA_CNTR_OFFSET)
#define IMX_DMA_CCR9 (DMA_CH9_BASE + DMA_CCR_OFFSET)
#define IMX_DMA_RSSR9 (DMA_CH9_BASE + DMA_RSSR_OFFSET)
#define IMX_DMA_BLR9 (DMA_CH9_BASE + DMA_BLR_OFFSET)
#define IMX_DMA_RTOR9 (DMA_CH9_BASE + DMA_RTOR_OFFSET)
#define IMX_DMA_BUCR9 (DMA_CH9_BASE + DMA_BUCR_OFFSET)
#define IMX_DMA_SAR10 (DMA_CH10_BASE + DMA_SAR_OFFSET)
#define IMX_DMA_DAR10 (DMA_CH10_BASE + DMA_DAR_OFFSET)
#define IMX_DMA_CNTR10 (DMA_CH10_BASE + DMA_CNTR_OFFSET)
#define IMX_DMA_CCR10 (DMA_CH10_BASE + DMA_CCR_OFFSET)
#define IMX_DMA_RSSR10 (DMA_CH10_BASE + DMA_RSSR_OFFSET)
#define IMX_DMA_BLR10 (DMA_CH10_BASE + DMA_BLR_OFFSET)
#define IMX_DMA_RTOR10 (DMA_CH10_BASE + DMA_RTOR_OFFSET)
#define IMX_DMA_BUCR10 (DMA_CH10_BASE + DMA_BUCR_OFFSET)
#define IMX_DMA_SAR(n) (DMA_CH_BASE(n) + DMA_SAR_OFFSET)
#define IMX_DMA_DAR(n) (DMA_CH_BASE(n) + DMA_DAR_OFFSET)
#define IMX_DMA_CNTR(n) (DMA_CH_BASE(n) + DMA_CNTR_OFFSET)
#define IMX_DMA_CCR(n) (DMA_CH_BASE(n) + DMA_CCR_OFFSET)
#define IMX_DMA_RSSR(n) (DMA_CH_BASE(n) + DMA_RSSR_OFFSET)
#define IMX_DMA_BLR(n) (DMA_CH_BASE(n) + DMA_BLR_OFFSET)
#define IMX_DMA_RTOR(n) (DMA_CH_BASE(n) + DMA_RTOR_OFFSET)
#define IMX_DMA_BUCR(n) (DMA_CH_BASE(n) + DMA_BUCR_OFFSET)
#define IMX_DMA_TCR (DMA_TST_BASE + DMA_TCR_OFFSET)
#define IMX_DMA_TFIFOA (DMA_TST_BASE + DMA_TFIFOA_OFFSET)
#define IMX_DMA_TDRR (DMA_TST_BASE + DMA_TDRR_OFFSET)
#define IMX_DMA_TDIPR (DMA_TST_BASE + DMA_TDIPR_OFFSET)
#define IMX_DMA_TFIFOB (DMA_TST_BASE + DMA_TFIFOB_OFFSET)
/* DMA Register Bit Definitions *****************************************************/
/************************************************************************************
* Inline Functions
************************************************************************************/
#endif /* __ARCH_ARM_IMX_DMA_H */
/************************************************************************************
* arch/arm/src/imx/imx_dma.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_IMX_DMA_H
#define __ARCH_ARM_IMX_DMA_H
/************************************************************************************
* Included Files
************************************************************************************/
/************************************************************************************
* Definitions
************************************************************************************/
/* DMA Register Offsets *************************************************************/
#define DMA_SYS_OFFSET 0x0000
#define DMA_M2D_OFFSET 0x0040
#define DMA_CH0_OFFSET 0x0080
#define DMA_CH1_OFFSET 0x00c0
#define DMA_CH2_OFFSET 0x0100
#define DMA_CH3_OFFSET 0x0140
#define DMA_CH4_OFFSET 0x0180
#define DMA_CH5_OFFSET 0x01C0
#define DMA_CH6_OFFSET 0x0200
#define DMA_CH7_OFFSET 0x0240
#define DMA_CH8_OFFSET 0x0280
#define DMA_CH9_OFFSET 0x02c0
#define DMA_CH10_OFFSET 0x0300
#define DMA_CH_OFFSET(n) (DMA_CH0_OFFSET + (n)*0x0040)
#define DMA_TST_OFFSET 0x0340
#define DMA_DCR_OFFSET 0x0000
#define DMA_ISR_OFFSET 0x0004
#define DMA_IMR_OFFSET 0x0008
#define DMA_BTOSR_OFFSET 0x000c
#define DMA_RTOSR_OFFSET 0x0010
#define DMA_TESR_OFFSET 0x0014
#define DMA_BOSR_OFFSET 0x0018
#define DMA_BTOCR_OFFSET 0x001c
#define DMA_WSRA_OFFSET 0x0000
#define DMA_XSRA_OFFSET 0x0004
#define DMA_YSRA_OFFSET 0x0008
#define DMA_WSRB_OFFSET 0x000c
#define DMA_XSRB_OFFSET 0x0010
#define DMA_YSRB_OFFSET 0x0014
#define DMA_SAR_OFFSET 0x0000
#define DMA_DAR_OFFSET 0x0004
#define DMA_CNTR_OFFSET 0x0008
#define DMA_CCR_OFFSET 0x000c
#define DMA_RSSR_OFFSET 0x0010
#define DMA_BLR_OFFSET 0x0014
#define DMA_RTOR_OFFSET 0x0018
#define DMA_BUCR_OFFSET 0x0018
#define DMA_TCR_OFFSET 0x0000
#define DMA_TFIFOA_OFFSET 0x0004
#define DMA_TDRR_OFFSET 0x0008
#define DMA_TDIPR_OFFSET 0x000c
#define DMA_TFIFOB_OFFSET 0x0010
/* DMA Register Addresses ***********************************************************/
#define IMX_DMA_SYS_BASE (IMX_DMA_VBASE + DMA_SYS_OFFSET)
#define IMX_DMA_M2D_BASE (IMX_DMA_VBASE + DMA_M2D_OFFSET)
#define IMX_DMA_CH0_BASE (IMX_DMA_VBASE + DMA_CH0_OFFSET)
#define IMX_DMA_CH1_BASE (IMX_DMA_VBASE + DMA_CH1_OFFSET)
#define IMX_DMA_CH2_BASE (IMX_DMA_VBASE + DMA_CH2_OFFSET)
#define IMX_DMA_CH3_BASE (IMX_DMA_VBASE + DMA_CH3_OFFSET)
#define IMX_DMA_CH4_BASE (IMX_DMA_VBASE + DMA_CH4_OFFSET)
#define IMX_DMA_CH5_BASE (IMX_DMA_VBASE + DMA_CH5_OFFSET)
#define IMX_DMA_CH6_BASE (IMX_DMA_VBASE + DMA_CH6_OFFSET)
#define IMX_DMA_CH7_BASE (IMX_DMA_VBASE + DMA_CH7_OFFSET)
#define IMX_DMA_CH8_BASE (IMX_DMA_VBASE + DMA_CH8_OFFSET)
#define IMX_DMA_CH9_BASE (IMX_DMA_VBASE + DMA_CH9_OFFSET)
#define IMX_DMA_CH10_BASE (IMX_DMA_VBASE + DMA_CH10_OFFSET)
#define IMX_DMA_CH_BASE(n) (IMX_DMA_VBASE + DMA_CH_OFFSET(n))
#define IMX_DMA_TST_BASE (IMX_DMA_VBASE + DMA_TST_OFFSET)
#define IMX_DMA_DCR (DMA_SYS_BASE + DMA_DCR_OFFSET)
#define IMX_DMA_ISR (DMA_SYS_BASE + DMA_ISR_OFFSET)
#define IMX_DMA_IMR (DMA_SYS_BASE + DMA_IMR_OFFSET)
#define IMX_DMA_BTOSR (DMA_SYS_BASE + DMA_BTOSR_OFFSET)
#define IMX_DMA_RTOSR (DMA_SYS_BASE + DMA_RTOSR_OFFSET)
#define IMX_DMA_TESR (DMA_SYS_BASE + DMA_TESR_OFFSET)
#define IMX_DMA_BOSR (DMA_SYS_BASE + DMA_BOSR_OFFSET)
#define IMX_DMA_BTOCR (DMA_SYS_BASE + DMA_BTOCR_OFFSET)
#define IMX_DMA_WSRA (DMA_M2D_BASE + DMA_WSRA_OFFSET)
#define IMX_DMA_XSRA (DMA_M2D_BASE + DMA_XSRA_OFFSET)
#define IMX_DMA_YSRA (DMA_M2D_BASE + DMA_YSRA_OFFSET)
#define IMX_DMA_WSRB (DMA_M2D_BASE + DMA_WSRB_OFFSET)
#define IMX_DMA_XSRB (DMA_M2D_BASE + DMA_XSRB_OFFSET)
#define IMX_DMA_YSRB (DMA_M2D_BASE + DMA_YSRB_OFFSET)
#define IMX_DMA_SAR0 (DMA_CH0_BASE + DMA_SAR_OFFSET)
#define IMX_DMA_DAR0 (DMA_CH0_BASE + DMA_DAR_OFFSET)
#define IMX_DMA_CNTR0 (DMA_CH0_BASE + DMA_CNTR_OFFSET)
#define IMX_DMA_CCR0 (DMA_CH0_BASE + DMA_CCR_OFFSET)
#define IMX_DMA_RSSR0 (DMA_CH0_BASE + DMA_RSSR_OFFSET)
#define IMX_DMA_BLR0 (DMA_CH0_BASE + DMA_BLR_OFFSET)
#define IMX_DMA_RTOR0 (DMA_CH0_BASE + DMA_RTOR_OFFSET)
#define IMX_DMA_BUCR0 (DMA_CH0_BASE + DMA_BUCR_OFFSET)
#define IMX_DMA_SAR1 (DMA_CH1_BASE + DMA_SAR_OFFSET)
#define IMX_DMA_DAR1 (DMA_CH1_BASE + DMA_DAR_OFFSET)
#define IMX_DMA_CNTR1 (DMA_CH1_BASE + DMA_CNTR_OFFSET)
#define IMX_DMA_CCR1 (DMA_CH1_BASE + DMA_CCR_OFFSET)
#define IMX_DMA_RSSR1 (DMA_CH1_BASE + DMA_RSSR_OFFSET)
#define IMX_DMA_BLR1 (DMA_CH1_BASE + DMA_BLR_OFFSET)
#define IMX_DMA_RTOR1 (DMA_CH1_BASE + DMA_RTOR_OFFSET)
#define IMX_DMA_BUCR1 (DMA_CH1_BASE + DMA_BUCR_OFFSET)
#define IMX_DMA_SAR2 (DMA_CH2_BASE + DMA_SAR_OFFSET)
#define IMX_DMA_DAR2 (DMA_CH2_BASE + DMA_DAR_OFFSET)
#define IMX_DMA_CNTR2 (DMA_CH2_BASE + DMA_CNTR_OFFSET)
#define IMX_DMA_CCR2 (DMA_CH2_BASE + DMA_CCR_OFFSET)
#define IMX_DMA_RSSR2 (DMA_CH2_BASE + DMA_RSSR_OFFSET)
#define IMX_DMA_BLR2 (DMA_CH2_BASE + DMA_BLR_OFFSET)
#define IMX_DMA_RTOR2 (DMA_CH2_BASE + DMA_RTOR_OFFSET)
#define IMX_DMA_BUCR2 (DMA_CH2_BASE + DMA_BUCR_OFFSET)
#define IMX_DMA_SAR3 (DMA_CH3_BASE + DMA_SAR_OFFSET)
#define IMX_DMA_DAR3 (DMA_CH3_BASE + DMA_DAR_OFFSET)
#define IMX_DMA_CNTR3 (DMA_CH3_BASE + DMA_CNTR_OFFSET)
#define IMX_DMA_CCR3 (DMA_CH3_BASE + DMA_CCR_OFFSET)
#define IMX_DMA_RSSR3 (DMA_CH3_BASE + DMA_RSSR_OFFSET)
#define IMX_DMA_BLR3 (DMA_CH3_BASE + DMA_BLR_OFFSET)
#define IMX_DMA_RTOR3 (DMA_CH3_BASE + DMA_RTOR_OFFSET)
#define IMX_DMA_BUCR3 (DMA_CH3_BASE + DMA_BUCR_OFFSET)
#define IMX_DMA_SAR4 (DMA_CH4_BASE + DMA_SAR_OFFSET)
#define IMX_DMA_DAR4 (DMA_CH4_BASE + DMA_DAR_OFFSET)
#define IMX_DMA_CNTR4 (DMA_CH4_BASE + DMA_CNTR_OFFSET)
#define IMX_DMA_CCR4 (DMA_CH4_BASE + DMA_CCR_OFFSET)
#define IMX_DMA_RSSR4 (DMA_CH4_BASE + DMA_RSSR_OFFSET)
#define IMX_DMA_BLR4 (DMA_CH4_BASE + DMA_BLR_OFFSET)
#define IMX_DMA_RTOR4 (DMA_CH4_BASE + DMA_RTOR_OFFSET)
#define IMX_DMA_BUCR4 (DMA_CH4_BASE + DMA_BUCR_OFFSET)
#define IMX_DMA_SAR5 (DMA_CH5_BASE + DMA_SAR_OFFSET)
#define IMX_DMA_DAR5 (DMA_CH5_BASE + DMA_DAR_OFFSET)
#define IMX_DMA_CNTR5 (DMA_CH5_BASE + DMA_CNTR_OFFSET)
#define IMX_DMA_CCR5 (DMA_CH5_BASE + DMA_CCR_OFFSET)
#define IMX_DMA_RSSR5 (DMA_CH5_BASE + DMA_RSSR_OFFSET)
#define IMX_DMA_BLR5 (DMA_CH5_BASE + DMA_BLR_OFFSET)
#define IMX_DMA_RTOR5 (DMA_CH5_BASE + DMA_RTOR_OFFSET)
#define IMX_DMA_BUCR5 (DMA_CH5_BASE + DMA_BUCR_OFFSET)
#define IMX_DMA_SAR6 (DMA_CH6_BASE + DMA_SAR_OFFSET)
#define IMX_DMA_DAR6 (DMA_CH6_BASE + DMA_DAR_OFFSET)
#define IMX_DMA_CNTR6 (DMA_CH6_BASE + DMA_CNTR_OFFSET)
#define IMX_DMA_CCR6 (DMA_CH6_BASE + DMA_CCR_OFFSET)
#define IMX_DMA_RSSR6 (DMA_CH6_BASE + DMA_RSSR_OFFSET)
#define IMX_DMA_BLR6 (DMA_CH6_BASE + DMA_BLR_OFFSET)
#define IMX_DMA_RTOR6 (DMA_CH6_BASE + DMA_RTOR_OFFSET)
#define IMX_DMA_BUCR6 (DMA_CH6_BASE + DMA_BUCR_OFFSET)
#define IMX_DMA_SAR7 (DMA_CH7_BASE + DMA_SAR_OFFSET)
#define IMX_DMA_DAR7 (DMA_CH7_BASE + DMA_DAR_OFFSET)
#define IMX_DMA_CNTR7 (DMA_CH7_BASE + DMA_CNTR_OFFSET)
#define IMX_DMA_CCR7 (DMA_CH7_BASE + DMA_CCR_OFFSET)
#define IMX_DMA_RSSR7 (DMA_CH7_BASE + DMA_RSSR_OFFSET)
#define IMX_DMA_BLR7 (DMA_CH7_BASE + DMA_BLR_OFFSET)
#define IMX_DMA_RTOR7 (DMA_CH7_BASE + DMA_RTOR_OFFSET)
#define IMX_DMA_BUCR7 (DMA_CH7_BASE + DMA_BUCR_OFFSET)
#define IMX_DMA_SAR8 (DMA_CH8_BASE + DMA_SAR_OFFSET)
#define IMX_DMA_DAR8 (DMA_CH8_BASE + DMA_DAR_OFFSET)
#define IMX_DMA_CNTR8 (DMA_CH8_BASE + DMA_CNTR_OFFSET)
#define IMX_DMA_CCR8 (DMA_CH8_BASE + DMA_CCR_OFFSET)
#define IMX_DMA_RSSR8 (DMA_CH8_BASE + DMA_RSSR_OFFSET)
#define IMX_DMA_BLR8 (DMA_CH8_BASE + DMA_BLR_OFFSET)
#define IMX_DMA_RTOR8 (DMA_CH8_BASE + DMA_RTOR_OFFSET)
#define IMX_DMA_BUCR8 (DMA_CH8_BASE + DMA_BUCR_OFFSET)
#define IMX_DMA_SAR9 (DMA_CH9_BASE + DMA_SAR_OFFSET)
#define IMX_DMA_DAR9 (DMA_CH9_BASE + DMA_DAR_OFFSET)
#define IMX_DMA_CNTR9 (DMA_CH9_BASE + DMA_CNTR_OFFSET)
#define IMX_DMA_CCR9 (DMA_CH9_BASE + DMA_CCR_OFFSET)
#define IMX_DMA_RSSR9 (DMA_CH9_BASE + DMA_RSSR_OFFSET)
#define IMX_DMA_BLR9 (DMA_CH9_BASE + DMA_BLR_OFFSET)
#define IMX_DMA_RTOR9 (DMA_CH9_BASE + DMA_RTOR_OFFSET)
#define IMX_DMA_BUCR9 (DMA_CH9_BASE + DMA_BUCR_OFFSET)
#define IMX_DMA_SAR10 (DMA_CH10_BASE + DMA_SAR_OFFSET)
#define IMX_DMA_DAR10 (DMA_CH10_BASE + DMA_DAR_OFFSET)
#define IMX_DMA_CNTR10 (DMA_CH10_BASE + DMA_CNTR_OFFSET)
#define IMX_DMA_CCR10 (DMA_CH10_BASE + DMA_CCR_OFFSET)
#define IMX_DMA_RSSR10 (DMA_CH10_BASE + DMA_RSSR_OFFSET)
#define IMX_DMA_BLR10 (DMA_CH10_BASE + DMA_BLR_OFFSET)
#define IMX_DMA_RTOR10 (DMA_CH10_BASE + DMA_RTOR_OFFSET)
#define IMX_DMA_BUCR10 (DMA_CH10_BASE + DMA_BUCR_OFFSET)
#define IMX_DMA_SAR(n) (DMA_CH_BASE(n) + DMA_SAR_OFFSET)
#define IMX_DMA_DAR(n) (DMA_CH_BASE(n) + DMA_DAR_OFFSET)
#define IMX_DMA_CNTR(n) (DMA_CH_BASE(n) + DMA_CNTR_OFFSET)
#define IMX_DMA_CCR(n) (DMA_CH_BASE(n) + DMA_CCR_OFFSET)
#define IMX_DMA_RSSR(n) (DMA_CH_BASE(n) + DMA_RSSR_OFFSET)
#define IMX_DMA_BLR(n) (DMA_CH_BASE(n) + DMA_BLR_OFFSET)
#define IMX_DMA_RTOR(n) (DMA_CH_BASE(n) + DMA_RTOR_OFFSET)
#define IMX_DMA_BUCR(n) (DMA_CH_BASE(n) + DMA_BUCR_OFFSET)
#define IMX_DMA_TCR (DMA_TST_BASE + DMA_TCR_OFFSET)
#define IMX_DMA_TFIFOA (DMA_TST_BASE + DMA_TFIFOA_OFFSET)
#define IMX_DMA_TDRR (DMA_TST_BASE + DMA_TDRR_OFFSET)
#define IMX_DMA_TDIPR (DMA_TST_BASE + DMA_TDIPR_OFFSET)
#define IMX_DMA_TFIFOB (DMA_TST_BASE + DMA_TFIFOB_OFFSET)
/* DMA Register Bit Definitions *****************************************************/
/************************************************************************************
* Inline Functions
************************************************************************************/
#endif /* __ARCH_ARM_IMX_DMA_H */
nuttx/arch/arm/src/imx/imx_eim.h
+85 -85
View File
@@ -1,85 +1,85 @@
/************************************************************************************
* arch/arm/src/imx/imx_eim.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_IMX_WIEM_H
#define __ARCH_ARM_IMX_WIEM_H
/************************************************************************************
* Included Files
************************************************************************************/
/************************************************************************************
* Definitions
************************************************************************************/
/* EIM Register Offsets ************************************************************/
#define EIM_CS0H_OFFSET 0x00
#define EIM_CS0L_OFFSET 0x04
#define EIM_CS1H_OFFSET 0x08
#define EIM_CS1L_OFFSET 0x0c
#define EIM_CS2H_OFFSET 0x10
#define EIM_CS2L_OFFSET 0x14
#define EIM_CS3H_OFFSET 0x18
#define EIM_CS3L_OFFSET 0x1c
#define EIM_CS4H_OFFSET 0x20
#define EIM_CS4L_OFFSET 0x24
#define EIM_CS5H_OFFSET 0x28
#define EIM_CS5L_OFFSET 0x2c
#define EIM_WEIM_OFFSET 0x30
/* EIM Register Addresses ***********************************************************/
#define IMX_EIM_CS0H (EIM_BASE_ADDR + EIM_CS0H_OFFSET)
#define IMX_EIM_CS0L (EIM_BASE_ADDR + EIM_CS0L_OFFSET)
#define IMX_EIM_CS1H (EIM_BASE_ADDR + EIM_CS1H_OFFSET)
#define IMX_EIM_CS1L (EIM_BASE_ADDR + EIM_CS1L_OFFSET)
#define IMX_EIM_CS2H (EIM_BASE_ADDR + EIM_CS2H_OFFSET)
#define IMX_EIM_CS2L (EIM_BASE_ADDR + EIM_CS2L_OFFSET)
#define IMX_EIM_CS3H (EIM_BASE_ADDR + EIM_CS3H_OFFSET)
#define IMX_EIM_CS3L (EIM_BASE_ADDR + EIM_CS3L_OFFSET)
#define IMX_EIM_CS4H (EIM_BASE_ADDR + EIM_CS4H_OFFSET)
#define IMX_EIM_CS4L (EIM_BASE_ADDR + EIM_CS4L_OFFSET)
#define IMX_EIM_CS5H (EIM_BASE_ADDR + EIM_CS5H_OFFSET)
#define IMX_EIM_CS5L (EIM_BASE_ADDR + EIM_CS5L_OFFSET)
#define IMX_EIM_WEIM (EIM_BASE_ADDR + EIM_WEIM_OFFSET)
/* EIM Register Bit Definitions *****************************************************/
/************************************************************************************
* Inline Functions
************************************************************************************/
#endif /* __ARCH_ARM_IMX_EIM_H */
/************************************************************************************
* arch/arm/src/imx/imx_eim.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_IMX_WIEM_H
#define __ARCH_ARM_IMX_WIEM_H
/************************************************************************************
* Included Files
************************************************************************************/
/************************************************************************************
* Definitions
************************************************************************************/
/* EIM Register Offsets ************************************************************/
#define EIM_CS0H_OFFSET 0x00
#define EIM_CS0L_OFFSET 0x04
#define EIM_CS1H_OFFSET 0x08
#define EIM_CS1L_OFFSET 0x0c
#define EIM_CS2H_OFFSET 0x10
#define EIM_CS2L_OFFSET 0x14
#define EIM_CS3H_OFFSET 0x18
#define EIM_CS3L_OFFSET 0x1c
#define EIM_CS4H_OFFSET 0x20
#define EIM_CS4L_OFFSET 0x24
#define EIM_CS5H_OFFSET 0x28
#define EIM_CS5L_OFFSET 0x2c
#define EIM_WEIM_OFFSET 0x30
/* EIM Register Addresses ***********************************************************/
#define IMX_EIM_CS0H (EIM_BASE_ADDR + EIM_CS0H_OFFSET)
#define IMX_EIM_CS0L (EIM_BASE_ADDR + EIM_CS0L_OFFSET)
#define IMX_EIM_CS1H (EIM_BASE_ADDR + EIM_CS1H_OFFSET)
#define IMX_EIM_CS1L (EIM_BASE_ADDR + EIM_CS1L_OFFSET)
#define IMX_EIM_CS2H (EIM_BASE_ADDR + EIM_CS2H_OFFSET)
#define IMX_EIM_CS2L (EIM_BASE_ADDR + EIM_CS2L_OFFSET)
#define IMX_EIM_CS3H (EIM_BASE_ADDR + EIM_CS3H_OFFSET)
#define IMX_EIM_CS3L (EIM_BASE_ADDR + EIM_CS3L_OFFSET)
#define IMX_EIM_CS4H (EIM_BASE_ADDR + EIM_CS4H_OFFSET)
#define IMX_EIM_CS4L (EIM_BASE_ADDR + EIM_CS4L_OFFSET)
#define IMX_EIM_CS5H (EIM_BASE_ADDR + EIM_CS5H_OFFSET)
#define IMX_EIM_CS5L (EIM_BASE_ADDR + EIM_CS5L_OFFSET)
#define IMX_EIM_WEIM (EIM_BASE_ADDR + EIM_WEIM_OFFSET)
/* EIM Register Bit Definitions *****************************************************/
/************************************************************************************
* Inline Functions
************************************************************************************/
#endif /* __ARCH_ARM_IMX_EIM_H */
nuttx/arch/arm/src/imx/imx_gpio.c
+1 -1
View File
@@ -3,7 +3,7 @@
* arch/arm/src/chip/imx_gpio.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/imx/imx_gpio.h
+562 -562
View File
File diff suppressed because it is too large Load Diff
nuttx/arch/arm/src/imx/imx_i2c.h
+69 -69
View File
@@ -1,69 +1,69 @@
/************************************************************************************
* arch/arm/src/imx/imx_i2c.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_IMX_I2C_H
#define __ARCH_ARM_IMX_I2C_H
/************************************************************************************
* Included Files
************************************************************************************/
/************************************************************************************
* Definitions
************************************************************************************/
/* I2C Register Offsets *************************************************************/
#define I2C_IADR_OFFSET 0x0000
#define I2C_IFDR_OFFSET 0x0004
#define I2C_I2CR_OFFSET 0x0008
#define I2C_I2SR_OFFSET 0x000c
#define I2C_I2DR_OFFSET 0x0010
/* I2C Register Addresses ***********************************************************/
#define IMX_I2C_IADR (IMX_I2C_VBASE + I2C_IADR_OFFSET)
#define IMX_I2C_IFDR (IMX_I2C_VBASE + I2C_IFDR_OFFSET)
#define IMX_I2C_I2CR (IMX_I2C_VBASE + I2C_I2CR_OFFSET)
#define IMX_I2C_I2SR (IMX_I2C_VBASE + I2C_I2SR_OFFSET)
#define IMX_I2C_I2DR (IMX_I2C_VBASE + I2C_I2DR_OFFSET)
/* I2C Register Bit Definitions *****************************************************/
/************************************************************************************
* Inline Functions
************************************************************************************/
#endif /* __ARCH_ARM_IMX_I2C_H */
/************************************************************************************
* arch/arm/src/imx/imx_i2c.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_IMX_I2C_H
#define __ARCH_ARM_IMX_I2C_H
/************************************************************************************
* Included Files
************************************************************************************/
/************************************************************************************
* Definitions
************************************************************************************/
/* I2C Register Offsets *************************************************************/
#define I2C_IADR_OFFSET 0x0000
#define I2C_IFDR_OFFSET 0x0004
#define I2C_I2CR_OFFSET 0x0008
#define I2C_I2SR_OFFSET 0x000c
#define I2C_I2DR_OFFSET 0x0010
/* I2C Register Addresses ***********************************************************/
#define IMX_I2C_IADR (IMX_I2C_VBASE + I2C_IADR_OFFSET)
#define IMX_I2C_IFDR (IMX_I2C_VBASE + I2C_IFDR_OFFSET)
#define IMX_I2C_I2CR (IMX_I2C_VBASE + I2C_I2CR_OFFSET)
#define IMX_I2C_I2SR (IMX_I2C_VBASE + I2C_I2SR_OFFSET)
#define IMX_I2C_I2DR (IMX_I2C_VBASE + I2C_I2DR_OFFSET)
/* I2C Register Bit Definitions *****************************************************/
/************************************************************************************
* Inline Functions
************************************************************************************/
#endif /* __ARCH_ARM_IMX_I2C_H */
nuttx/arch/arm/src/imx/imx_irq.c
+1 -1
View File
@@ -3,7 +3,7 @@
* arch/arm/src/chip/imx_irq.c
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/imx/imx_lowputc.S
+1 -1
View File
@@ -3,7 +3,7 @@
* arch/arm/src/chip/imx_lowputc.S
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/imx/imx_memorymap.h
+1 -1
View File
@@ -2,7 +2,7 @@
* arch/arm/src/imx/imx_memorymap.h
*
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/imx/imx_rtc.h
+85 -85
View File
@@ -1,85 +1,85 @@
/************************************************************************************
* arch/arm/src/imx/imx_rtc.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_IMX_RTC_H
#define __ARCH_ARM_IMX_RTC_H
/************************************************************************************
* Included Files
************************************************************************************/
/************************************************************************************
* Definitions
************************************************************************************/
/* RTC Register Offsets *************************************************************/
#define RTC_HOURMIN_OFFSET 0x0000
#define RTC_SECOND_OFFSET 0x0004
#define RTC_ALRM_HM_OFFSET 0x0008
#define RTC_ALRM_SEC_OFFSET 0x000c
#define RTC_RTCCTL_OFFSET 0x0010
#define RTC_RTCISR_OFFSET 0x0014
#define RTC_RTCIENR_OFFSET 0x0018
#define RTC_STPWCH_OFFSET 0x001c
#define RTC_DAYR_OFFSET 0x0020
#define RTC_DAYALARM_OFFSET 0x0024
#define RTC_TEST1_OFFSET 0x0028
#define RTC_TEST2_OFFSET 0x002c
#define RTC_TEST3_OFFSET 0x0030
/* RTC Register Addresses ***********************************************************/
#define IMX_RTC_HOURMIN (IMX_RTC_VBASE + RTC_HOURMIN_OFFSET)
#define IMX_RTC_SECOND (IMX_RTC_VBASE + RTC_SECOND_OFFSET)
#define IMX_RTC_ALRM_HM (IMX_RTC_VBASE + RTC_ALRM_HM_OFFSET)
#define IMX_RTC_ALRM_SEC (IMX_RTC_VBASE + RTC_ALRM_SEC_OFFSET)
#define IMX_RTC_RTCCTL (IMX_RTC_VBASE + RTC_RTCCTL_OFFSET)
#define IMX_RTC_RTCISR (IMX_RTC_VBASE + RTC_RTCISR_OFFSET)
#define IMX_RTC_RTCIENR (IMX_RTC_VBASE + RTC_RTCIENR_OFFSET)
#define IMX_RTC_STPWCH (IMX_RTC_VBASE + RTC_STPWCH_OFFSET)
#define IMX_RTC_DAYR (IMX_RTC_VBASE + RTC_DAYR_OFFSET)
#define IMX_RTC_DAYALARM (IMX_RTC_VBASE + RTC_DAYALARM_OFFSET)
#define IMX_RTC_TEST1 (IMX_RTC_VBASE + RTC_TEST1_OFFSET)
#define IMX_RTC_TEST2 (IMX_RTC_VBASE + RTC_TEST2_OFFSET)
#define IMX_RTC_TEST3 (IMX_RTC_VBASE + RTC_TEST3_OFFSET)
/* RTC Register Bit Definitions *****************************************************/
/************************************************************************************
* Inline Functions
************************************************************************************/
#endif /* __ARCH_ARM_IMX_RTC_H */
/************************************************************************************
* arch/arm/src/imx/imx_rtc.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_IMX_RTC_H
#define __ARCH_ARM_IMX_RTC_H
/************************************************************************************
* Included Files
************************************************************************************/
/************************************************************************************
* Definitions
************************************************************************************/
/* RTC Register Offsets *************************************************************/
#define RTC_HOURMIN_OFFSET 0x0000
#define RTC_SECOND_OFFSET 0x0004
#define RTC_ALRM_HM_OFFSET 0x0008
#define RTC_ALRM_SEC_OFFSET 0x000c
#define RTC_RTCCTL_OFFSET 0x0010
#define RTC_RTCISR_OFFSET 0x0014
#define RTC_RTCIENR_OFFSET 0x0018
#define RTC_STPWCH_OFFSET 0x001c
#define RTC_DAYR_OFFSET 0x0020
#define RTC_DAYALARM_OFFSET 0x0024
#define RTC_TEST1_OFFSET 0x0028
#define RTC_TEST2_OFFSET 0x002c
#define RTC_TEST3_OFFSET 0x0030
/* RTC Register Addresses ***********************************************************/
#define IMX_RTC_HOURMIN (IMX_RTC_VBASE + RTC_HOURMIN_OFFSET)
#define IMX_RTC_SECOND (IMX_RTC_VBASE + RTC_SECOND_OFFSET)
#define IMX_RTC_ALRM_HM (IMX_RTC_VBASE + RTC_ALRM_HM_OFFSET)
#define IMX_RTC_ALRM_SEC (IMX_RTC_VBASE + RTC_ALRM_SEC_OFFSET)
#define IMX_RTC_RTCCTL (IMX_RTC_VBASE + RTC_RTCCTL_OFFSET)
#define IMX_RTC_RTCISR (IMX_RTC_VBASE + RTC_RTCISR_OFFSET)
#define IMX_RTC_RTCIENR (IMX_RTC_VBASE + RTC_RTCIENR_OFFSET)
#define IMX_RTC_STPWCH (IMX_RTC_VBASE + RTC_STPWCH_OFFSET)
#define IMX_RTC_DAYR (IMX_RTC_VBASE + RTC_DAYR_OFFSET)
#define IMX_RTC_DAYALARM (IMX_RTC_VBASE + RTC_DAYALARM_OFFSET)
#define IMX_RTC_TEST1 (IMX_RTC_VBASE + RTC_TEST1_OFFSET)
#define IMX_RTC_TEST2 (IMX_RTC_VBASE + RTC_TEST2_OFFSET)
#define IMX_RTC_TEST3 (IMX_RTC_VBASE + RTC_TEST3_OFFSET)
/* RTC Register Bit Definitions *****************************************************/
/************************************************************************************
* Inline Functions
************************************************************************************/
#endif /* __ARCH_ARM_IMX_RTC_H */
nuttx/arch/arm/src/imx/imx_spi.c
+1 -1
View File
@@ -2,7 +2,7 @@
* arch/arm/src/imx/imx_spi.c
*
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
nuttx/arch/arm/src/imx/imx_system.h
+187 -187
View File
@@ -1,187 +1,187 @@
/************************************************************************************
* arch/arm/src/imx/imx_system.h
*
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_IMX_SYSTEM_H
#define __ARCH_ARM_IMX_SYSTEM_H
/************************************************************************************
* Included Files
************************************************************************************/
/************************************************************************************
* Definitions
************************************************************************************/
/* AIPI Register Offsets ************************************************************/
#define AIPI_PSR0_OFFSET 0x0000 /* Peripheral Size Register 0 */
#define AIPI_PSR1_OFFSET 0x0004 /* Peripheral Size Register 1 */
#define AIPI_PAR_OFFSET 0x0008 /* Peripheral Access Register */
/* AIPI Register Addresses **********************************************************/
#define IMX_AIPI1_PSR0 (IMX_AIPI1_VBASE + AIPI_PSR0_OFFSET)
#define IMX_AIPI1_PSR1 (IMX_AIPI1_VBASE + AIPI_PSR1_OFFSET)
#define IMX_AIPI1_PAR (IMX_AIPI1_VBASE + AIPI_PAR_OFFSET)
#define IMX_AIPI2_PSR0 (IMX_AIP2_VBASE + AIPI_PSR0_OFFSET)
#define IMX_AIPI2_PSR1 (IMX_AIP2_VBASE + AIPI_PSR1_OFFSET)
#define IMX_AIPI2_PAR (IMX_AIP2_VBASE + 0xAIPI_PAR_OFFSET)
/* AIPI Register Bit Definitions ****************************************************/
/* PLL Register Offsets *************************************************************/
#define PLL_CSCR_OFFSET 0x0000 /* Clock Source Control Register */
#define PLL_MPCTL0_OFFSET 0x0004 /* MCU PLL Control Register 0 */
#define PLL_MPCTL1_OFFSET 0x0008 /* MCU PLL & System Clock Control Register 1 */
#define PLL_SPCTL0_OFFSET 0x000c /* System PLL Control Register 0 */
#define PLL_SPCTL1_OFFSET 0x0010 /* System PLL Control Register 1 */
#define PLL_PCDR_OFFSET 0x0020 /* Peripherial Clock Divider Register */
/* PLL Register Addresses ***********************************************************/
#define IMX_PLL_CSCR (IMX_PLL_VBASE + PLL_CSCR_OFFSET)
#define IMX_PLL_MPCTL0 (IMX_PLL_VBASE + PLL_MPCTL0_OFFSET)
#define IMX_PLL_MPCTL1 (IMX_PLL_VBASE + PLL_MPCTL1_OFFSET)
#define IMX_PLL_SPCTL0 (IMX_PLL_VBASE + PLL_SPCTL0_OFFSET)
#define IMX_PLL_SPCTL1 (IMX_PLL_VBASE + PLL_SPCTL1_OFFSET)
#define IMX_PLL_PCDR (IMX_PLL_VBASE + PLL_PCDR_OFFSET)
/* PLL Register Bit Definitions *****************************************************/
#define PLL_CSCR_MPEN (1 << 0) /* Bit 0: 1 = MCU PLL enabled */
#define PLL_CSCR_SPEN (1 << 1) /* Bit 1: System PLL Enable */
#define PLL_CSCR_BCLKDIV_SHIFT 10 /* Bits 13–10: BClock Divider */
#define PLL_CSCR_BCLKDIV_MASK (15 << PLL_CSCR_BCLK_DIV_SHIFT)
#define PLL_CSCR_PRESC (1 << 15) /* Bit 15: MPU PLL clock prescaler */
#define PLL_CSCR_SYSTEM_SEL (1 << 16) /* Bit 16: System clock source select */
#define PLL_CSCR_OSCEN (1 << 17) /* Bit 17: Ext. 16MHz oscillator enable */
#define PLL_CSCR_CLK16_SEL (1 << 18) /* Bit 18: Select BT ref RFBTCLK16 */
#define PLL_CSCR_MPLLRESTART (1 << 21) /* Bit 21: MPLL Restart */
#define PLL_CSCR_SPLLRESTART (1 << 22) /* Bit 22: SPLL Restart */
#define PLL_CSCR_SDCNT_SHIFT 24 /* Bits 25–24: Shut-Down Control */
#define PLL_CSCR_SDCNT_MASK (3 << PLL_CSCR_SDCNT_SHIFT)
#define CSCR_SDCNT_2ndEDGE (1 << PLL_CSCR_SDCNT_SHIFT)
#define CSCR_SDCNT_3rdEDGE (2 << PLL_CSCR_SDCNT_SHIFT)
#define CSCR_SDCNT_4thEDGE (3 << PLL_CSCR_SDCNT_SHIFT)
#define PLL_CSCR_USBDIV_SHIFT 28 /* Bits 28–26: USB Divider */
#define PLL_CSCR_USBDIV_MASK (7 << PLL_CSCR_USB_DIV_SHIFT)
#define PLL_CSCR_CLKOSEL_SHIFT 29 /* Bits 31–29: CLKO Select */
#define PLL_CSCR_CLKOSEL_MASK (7 << PLL_CSCR_CLKOSEL_SHIFT)
#define CSCR_CLKOSEL_PERCLK1 (0 << PLL_CSCR_CLKOSEL_SHIFT)
#define CSCR_CLKOSEL_HCLK (1 << PLL_CSCR_CLKOSEL_SHIFT)
#define CSCR_CLKOSEL_CLK48M (2 << PLL_CSCR_CLKOSEL_SHIFT)
#define CSCR_CLKOSEL_CLK16M (3 << PLL_CSCR_CLKOSEL_SHIFT)
#define CSCR_CLKOSEL_PREMCLK (4 << PLL_CSCR_CLKOSEL_SHIFT)
#define CSCR_CLKOSEL_FCLK (5 << PLL_CSCR_CLKOSEL_SHIFT)
#define PLL_MPCTL0_MFN_SHIFT 0 /* Bits 9–0: Multiplication Factor (Numerator) */
#define PLL_MPCTL0_MFN_MASK (0x03ff << PLL_MPCTL0_MFN_SHIFT)
#define PLL_MPCTL0_MFI_SHIFT 10 /* Bits 13–10: Multiplication Factor (Integer) */
#define PLL_MPCTL0_MFI_MASK (0x0f << PLL_MPCTL0_MFI_SHIFT)
#define PLL_MPCTL0_MFD_SHIFT 16 /* Bits 25–16: Multiplication Factor (Denominator) */
#define PLL_MPCTL0_MFD_MASK (0x03ff << PLL_MPCTL0_MFD_SHIFT)
#define PLL_MPCTL0_PD_SHIFT 26 /* Bits 29–26: Predivider Factor */
#define PLL_MPCTL0_PD_MASK (0x0f << PLL_MPCTL0_PD_SHIFT
#define PLL_MPCTL1_BRMO (1 << 6) /* Bit 6: Controls the BRM order */
#define PLL_SPCTL0_MFN_SHIFT 0 /* Bits 9–0: Multiplication Factor (Numerator) */
#define PLL_SPCTL0_MFN_MASK (0x03ff << PLL_SPCTL0_MFN_SHIFT)
#define PLL_SPCTL0_MFI_SHIFT 10 /* Bits 13–10: Multiplication Factor (Integer) */
#define PLL_SPCTL0_MFI_MASK (0x0f << PLL_SPCTL0_MFI_SHIFT)
#define PLL_SPCTL0_MFD_SHIFT 16 /* Bits 25–16: Multiplication Factor (Denominator) */
#define PLL_SPCTL0_MFD_MASK (0x03ff << PLL_SPCTL0_MFD_SHIFT)
#define PLL_SPCTL0_PD_SHIFT 26 /* Bits 29–26: Predivider Factor */
#define PLL_SPCTL0_PD_MASK (0x0f << PLL_SPCTL0_PD_SHIFT)
#define PLL_SPCTL1_BRMO (1 << 6) /* Bit 6: Controls the BRM order */
#define PLL_SPCTL1_LF (1 << 15) /* Bit 15: Indicates if System PLL is locked */
#define PLL_PCDR_PCLKDIV1_SHIFT 0 /* Bits 3–0: Peripheral Clock Divider 1 */
#define PLL_PCDR_PCLKDIV1_MASK (0x0f << PLL_PCDR_PCLKDIV1_SHIFT)
#define PLL_PCDR_PCLKDIV2_SHIFT 4 /* Bits 7–4: Peripheral Clock Divider 2 */
#define PLL_PCDR_PCLKDIV2_MASK (0x0f << PLL_PCDR_PCLKDIV2_SHIFT)
#define PLL_PCDR_PCLKDIV3_SHIFT 16 /* Bits 22–16: Peripheral Clock Divider 3 */
#define PLL_PCDR_PCLKDIV3_MASK (0x7f << PLL_PCDR_PCLKDIV3_SHIFT)
/* PLL Helper Macros ****************************************************************/
/* SC Register Offsets **************************************************************/
#define SC_RSR_OFFSET 0x0000 /* Reset Source Register */
#define SC_SIDR_OFFSET 0x0004 /* Silicon ID Register */
#define SC_FMCR_OFFSET 0x0008 /* Function Muxing Control Register */
#define SC_GPCR_OFFSET 0x000c /* Global Peripheral Control Regiser */
/* SC Register Addresses ************************************************************/
#define IMX_SC_RSR (IMX_SC_VBASE + SC_RSR_OFFSET)
#define IMX_SC_SIDR (IMX_SC_VBASE + SC_SIDR_OFFSET)
#define IMX_SC_FMCR (IMX_SC_VBASE + SC_FMCR_OFFSET)
#define IMX_SC_GPCR (IMX_SC_VBASE + SC_GPCR_OFFSET)
/* SC Register Bit Definitions ******************************************************/
#define FMCR_SDCS_SEL (1 << 0) /* Bit 0: 1:CSD0 selected */
#define FMCR_SDCS1_SEL (1 << 1) /* Bit 1: 1:CSD1 selected */
#define FMCR_EXT_BREN (1 << 2) /* Bit 2: 1:External bus request enabled */
#define FMCR_SSI_TXCLKSEL (1 << 3) /* Bit 3: 1:Input from Port B[19] SIM_CLK pin */
#define FMCR_SSI_TXFSSEL (1 << 4) /* Bit 4: 1:Input from Port B[18] SIM_RST pin */
#define FMCR_SSI_RXDATSEL (1 << 5) /* Bit 5: 1:Input from Port B[16] SIM_TX pin */
#define FMCR_SSI_RXCLKSEL (1 << 6) /* Bit 6: 1:Input from Port B[15] SIM_PD pin */
#define FMCR_SSI_RXFSSEL (1 << 7) /* Bit 7: 1:Input from Port B[14] SIM_SVEN pin */
#define FMCR_SPI2_RXDSEL (1 << 8) /* Bit 8: 1:Input from SPI2_RXD_1 pin
* (AOUT of Port D[9]) */
/* SDRAMC Register Offsets **********************************************************/
#define SDRAMC_SDCTL0_OFFSET 0x0000
#define SDRAMC_SDCTL1_OFFSET 0x0004
/* SDRAMC Register Addresses ********************************************************/
#define IMX_SDRAMC_SDCTL0 (IMX_SDRAMC_VBASE + SDRAMC_SDCTL0_OFFSET)
#define IMX_SDRAMC_SDCTL1 (IMX_SDRAMC_VBASE + SDRAMC_SDCTL1_OFFSET))
/* SDRAMC Register Bit Definitions **************************************************/
/************************************************************************************
* Inline Functions
************************************************************************************/
#endif /* __ARCH_ARM_IMX_SYSTEM_H */
/************************************************************************************
* arch/arm/src/imx/imx_system.h
*
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_IMX_SYSTEM_H
#define __ARCH_ARM_IMX_SYSTEM_H
/************************************************************************************
* Included Files
************************************************************************************/
/************************************************************************************
* Definitions
************************************************************************************/
/* AIPI Register Offsets ************************************************************/
#define AIPI_PSR0_OFFSET 0x0000 /* Peripheral Size Register 0 */
#define AIPI_PSR1_OFFSET 0x0004 /* Peripheral Size Register 1 */
#define AIPI_PAR_OFFSET 0x0008 /* Peripheral Access Register */
/* AIPI Register Addresses **********************************************************/
#define IMX_AIPI1_PSR0 (IMX_AIPI1_VBASE + AIPI_PSR0_OFFSET)
#define IMX_AIPI1_PSR1 (IMX_AIPI1_VBASE + AIPI_PSR1_OFFSET)
#define IMX_AIPI1_PAR (IMX_AIPI1_VBASE + AIPI_PAR_OFFSET)
#define IMX_AIPI2_PSR0 (IMX_AIP2_VBASE + AIPI_PSR0_OFFSET)
#define IMX_AIPI2_PSR1 (IMX_AIP2_VBASE + AIPI_PSR1_OFFSET)
#define IMX_AIPI2_PAR (IMX_AIP2_VBASE + 0xAIPI_PAR_OFFSET)
/* AIPI Register Bit Definitions ****************************************************/
/* PLL Register Offsets *************************************************************/
#define PLL_CSCR_OFFSET 0x0000 /* Clock Source Control Register */
#define PLL_MPCTL0_OFFSET 0x0004 /* MCU PLL Control Register 0 */
#define PLL_MPCTL1_OFFSET 0x0008 /* MCU PLL & System Clock Control Register 1 */
#define PLL_SPCTL0_OFFSET 0x000c /* System PLL Control Register 0 */
#define PLL_SPCTL1_OFFSET 0x0010 /* System PLL Control Register 1 */
#define PLL_PCDR_OFFSET 0x0020 /* Peripherial Clock Divider Register */
/* PLL Register Addresses ***********************************************************/
#define IMX_PLL_CSCR (IMX_PLL_VBASE + PLL_CSCR_OFFSET)
#define IMX_PLL_MPCTL0 (IMX_PLL_VBASE + PLL_MPCTL0_OFFSET)
#define IMX_PLL_MPCTL1 (IMX_PLL_VBASE + PLL_MPCTL1_OFFSET)
#define IMX_PLL_SPCTL0 (IMX_PLL_VBASE + PLL_SPCTL0_OFFSET)
#define IMX_PLL_SPCTL1 (IMX_PLL_VBASE + PLL_SPCTL1_OFFSET)
#define IMX_PLL_PCDR (IMX_PLL_VBASE + PLL_PCDR_OFFSET)
/* PLL Register Bit Definitions *****************************************************/
#define PLL_CSCR_MPEN (1 << 0) /* Bit 0: 1 = MCU PLL enabled */
#define PLL_CSCR_SPEN (1 << 1) /* Bit 1: System PLL Enable */
#define PLL_CSCR_BCLKDIV_SHIFT 10 /* Bits 13–10: BClock Divider */
#define PLL_CSCR_BCLKDIV_MASK (15 << PLL_CSCR_BCLK_DIV_SHIFT)
#define PLL_CSCR_PRESC (1 << 15) /* Bit 15: MPU PLL clock prescaler */
#define PLL_CSCR_SYSTEM_SEL (1 << 16) /* Bit 16: System clock source select */
#define PLL_CSCR_OSCEN (1 << 17) /* Bit 17: Ext. 16MHz oscillator enable */
#define PLL_CSCR_CLK16_SEL (1 << 18) /* Bit 18: Select BT ref RFBTCLK16 */
#define PLL_CSCR_MPLLRESTART (1 << 21) /* Bit 21: MPLL Restart */
#define PLL_CSCR_SPLLRESTART (1 << 22) /* Bit 22: SPLL Restart */
#define PLL_CSCR_SDCNT_SHIFT 24 /* Bits 25–24: Shut-Down Control */
#define PLL_CSCR_SDCNT_MASK (3 << PLL_CSCR_SDCNT_SHIFT)
#define CSCR_SDCNT_2ndEDGE (1 << PLL_CSCR_SDCNT_SHIFT)
#define CSCR_SDCNT_3rdEDGE (2 << PLL_CSCR_SDCNT_SHIFT)
#define CSCR_SDCNT_4thEDGE (3 << PLL_CSCR_SDCNT_SHIFT)
#define PLL_CSCR_USBDIV_SHIFT 28 /* Bits 28–26: USB Divider */
#define PLL_CSCR_USBDIV_MASK (7 << PLL_CSCR_USB_DIV_SHIFT)
#define PLL_CSCR_CLKOSEL_SHIFT 29 /* Bits 31–29: CLKO Select */
#define PLL_CSCR_CLKOSEL_MASK (7 << PLL_CSCR_CLKOSEL_SHIFT)
#define CSCR_CLKOSEL_PERCLK1 (0 << PLL_CSCR_CLKOSEL_SHIFT)
#define CSCR_CLKOSEL_HCLK (1 << PLL_CSCR_CLKOSEL_SHIFT)
#define CSCR_CLKOSEL_CLK48M (2 << PLL_CSCR_CLKOSEL_SHIFT)
#define CSCR_CLKOSEL_CLK16M (3 << PLL_CSCR_CLKOSEL_SHIFT)
#define CSCR_CLKOSEL_PREMCLK (4 << PLL_CSCR_CLKOSEL_SHIFT)
#define CSCR_CLKOSEL_FCLK (5 << PLL_CSCR_CLKOSEL_SHIFT)
#define PLL_MPCTL0_MFN_SHIFT 0 /* Bits 9–0: Multiplication Factor (Numerator) */
#define PLL_MPCTL0_MFN_MASK (0x03ff << PLL_MPCTL0_MFN_SHIFT)
#define PLL_MPCTL0_MFI_SHIFT 10 /* Bits 13–10: Multiplication Factor (Integer) */
#define PLL_MPCTL0_MFI_MASK (0x0f << PLL_MPCTL0_MFI_SHIFT)
#define PLL_MPCTL0_MFD_SHIFT 16 /* Bits 25–16: Multiplication Factor (Denominator) */
#define PLL_MPCTL0_MFD_MASK (0x03ff << PLL_MPCTL0_MFD_SHIFT)
#define PLL_MPCTL0_PD_SHIFT 26 /* Bits 29–26: Predivider Factor */
#define PLL_MPCTL0_PD_MASK (0x0f << PLL_MPCTL0_PD_SHIFT
#define PLL_MPCTL1_BRMO (1 << 6) /* Bit 6: Controls the BRM order */
#define PLL_SPCTL0_MFN_SHIFT 0 /* Bits 9–0: Multiplication Factor (Numerator) */
#define PLL_SPCTL0_MFN_MASK (0x03ff << PLL_SPCTL0_MFN_SHIFT)
#define PLL_SPCTL0_MFI_SHIFT 10 /* Bits 13–10: Multiplication Factor (Integer) */
#define PLL_SPCTL0_MFI_MASK (0x0f << PLL_SPCTL0_MFI_SHIFT)
#define PLL_SPCTL0_MFD_SHIFT 16 /* Bits 25–16: Multiplication Factor (Denominator) */
#define PLL_SPCTL0_MFD_MASK (0x03ff << PLL_SPCTL0_MFD_SHIFT)
#define PLL_SPCTL0_PD_SHIFT 26 /* Bits 29–26: Predivider Factor */
#define PLL_SPCTL0_PD_MASK (0x0f << PLL_SPCTL0_PD_SHIFT)
#define PLL_SPCTL1_BRMO (1 << 6) /* Bit 6: Controls the BRM order */
#define PLL_SPCTL1_LF (1 << 15) /* Bit 15: Indicates if System PLL is locked */
#define PLL_PCDR_PCLKDIV1_SHIFT 0 /* Bits 3–0: Peripheral Clock Divider 1 */
#define PLL_PCDR_PCLKDIV1_MASK (0x0f << PLL_PCDR_PCLKDIV1_SHIFT)
#define PLL_PCDR_PCLKDIV2_SHIFT 4 /* Bits 7–4: Peripheral Clock Divider 2 */
#define PLL_PCDR_PCLKDIV2_MASK (0x0f << PLL_PCDR_PCLKDIV2_SHIFT)
#define PLL_PCDR_PCLKDIV3_SHIFT 16 /* Bits 22–16: Peripheral Clock Divider 3 */
#define PLL_PCDR_PCLKDIV3_MASK (0x7f << PLL_PCDR_PCLKDIV3_SHIFT)
/* PLL Helper Macros ****************************************************************/
/* SC Register Offsets **************************************************************/
#define SC_RSR_OFFSET 0x0000 /* Reset Source Register */
#define SC_SIDR_OFFSET 0x0004 /* Silicon ID Register */
#define SC_FMCR_OFFSET 0x0008 /* Function Muxing Control Register */
#define SC_GPCR_OFFSET 0x000c /* Global Peripheral Control Regiser */
/* SC Register Addresses ************************************************************/
#define IMX_SC_RSR (IMX_SC_VBASE + SC_RSR_OFFSET)
#define IMX_SC_SIDR (IMX_SC_VBASE + SC_SIDR_OFFSET)
#define IMX_SC_FMCR (IMX_SC_VBASE + SC_FMCR_OFFSET)
#define IMX_SC_GPCR (IMX_SC_VBASE + SC_GPCR_OFFSET)
/* SC Register Bit Definitions ******************************************************/
#define FMCR_SDCS_SEL (1 << 0) /* Bit 0: 1:CSD0 selected */
#define FMCR_SDCS1_SEL (1 << 1) /* Bit 1: 1:CSD1 selected */
#define FMCR_EXT_BREN (1 << 2) /* Bit 2: 1:External bus request enabled */
#define FMCR_SSI_TXCLKSEL (1 << 3) /* Bit 3: 1:Input from Port B[19] SIM_CLK pin */
#define FMCR_SSI_TXFSSEL (1 << 4) /* Bit 4: 1:Input from Port B[18] SIM_RST pin */
#define FMCR_SSI_RXDATSEL (1 << 5) /* Bit 5: 1:Input from Port B[16] SIM_TX pin */
#define FMCR_SSI_RXCLKSEL (1 << 6) /* Bit 6: 1:Input from Port B[15] SIM_PD pin */
#define FMCR_SSI_RXFSSEL (1 << 7) /* Bit 7: 1:Input from Port B[14] SIM_SVEN pin */
#define FMCR_SPI2_RXDSEL (1 << 8) /* Bit 8: 1:Input from SPI2_RXD_1 pin
* (AOUT of Port D[9]) */
/* SDRAMC Register Offsets **********************************************************/
#define SDRAMC_SDCTL0_OFFSET 0x0000
#define SDRAMC_SDCTL1_OFFSET 0x0004
/* SDRAMC Register Addresses ********************************************************/
#define IMX_SDRAMC_SDCTL0 (IMX_SDRAMC_VBASE + SDRAMC_SDCTL0_OFFSET)
#define IMX_SDRAMC_SDCTL1 (IMX_SDRAMC_VBASE + SDRAMC_SDCTL1_OFFSET))
/* SDRAMC Register Bit Definitions **************************************************/
/************************************************************************************
* Inline Functions
************************************************************************************/
#endif /* __ARCH_ARM_IMX_SYSTEM_H */
nuttx/arch/arm/src/imx/imx_timer.h
+1 -1
View File
@@ -2,7 +2,7 @@
* arch/arm/src/imx/imx_timer.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions

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