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Rebased on master, removing the default_rate field and using default to 0 for rates

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This commit is contained in:
David Sidrane
2016-02-01 10:10:35 +01:00
committed by Lorenz Meier
parent 0d13c41108
commit 7edd07f8cb
1 changed files with 7 additions and 2 deletions
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src/drivers/stm32/drv_io_timer.c
+7 -2
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@@ -413,6 +413,10 @@ static int io_timer_init_timer(unsigned timer)
rCCER(timer) = 0; rCCER(timer) = 0;
rCCMR1(timer) = 0; rCCMR1(timer) = 0;
rCCMR2(timer) = 0; rCCMR2(timer) = 0;
rCCR1(timer) = 0;
rCCR2(timer) = 0;
rCCR3(timer) = 0;
rCCR4(timer) = 0;
rCCER(timer) = 0; rCCER(timer) = 0;
rDCR(timer) = 0; rDCR(timer) = 0;
@@ -548,10 +552,11 @@ int io_timer_channel_init(unsigned channel, io_timer_channel_mode_t mode,
* The beauty here is that per DocID018909 Rev 8 18.3.5 Input capture mode * The beauty here is that per DocID018909 Rev 8 18.3.5 Input capture mode
* As soon as CCxS (in SSMRx becomes different from 00, the channel is configured * As soon as CCxS (in SSMRx becomes different from 00, the channel is configured
* in input and the TIMx_CCR1 register becomes read-only. * in input and the TIMx_CCR1 register becomes read-only.
* so the next line does nothing * so the next line does nothing in capture mode and initializes an PWM out to
* 0
*/ */
REG(timer, ccr_offset) = timer_io_channels[channel].default_value; REG(timer, ccr_offset) = 0;
/* on PWM Out ccer_setbits is 0 */ /* on PWM Out ccer_setbits is 0 */