diff --git a/boards/mro/ctrl-zero-h7-oem/nuttx-config/include/board.h b/boards/mro/ctrl-zero-h7-oem/nuttx-config/include/board.h index 9b1ae6342d..4f60a560b2 100644 --- a/boards/mro/ctrl-zero-h7-oem/nuttx-config/include/board.h +++ b/boards/mro/ctrl-zero-h7-oem/nuttx-config/include/board.h @@ -60,7 +60,6 @@ #define STM32_HSI_FREQUENCY 16000000ul #define STM32_LSI_FREQUENCY 32000 #define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 0 /* Main PLL Configuration. * @@ -82,56 +81,55 @@ * PLLP2,3 = {2, 3, 4, ..., 128} * CPUCLK <= 480 MHz */ -#define STM32_PLLCFG_PLLSRC RCC_PLLCKSELR_PLLSRC_HSE /* PLL1, wide 4 - 8 MHz input, enable DIVP, DIVQ, DIVR * - * PLL1_VCO = (24,000,000 / 2) * 80 = 960 MHz + * PLL1_VCO = (24,000,000 / 3) * 100 = 800 MHz * - * PLL1P = PLL1_VCO/2 = 960 MHz / 2 = 480 MHz - * PLL1Q = PLL1_VCO/4 = 960 MHz / 4 = 240 MHz - * PLL1R = PLL1_VCO/8 = 960 MHz / 8 = 120 MHz + * PLL1P = PLL1_VCO/2 = 800 MHz / 2 = 400 MHz + * PLL1Q = PLL1_VCO/8 = 800 MHz / 8 = 100 MHz + * PLL1R = PLL1_VCO/2 = 800 MHz / 2 = 400 MHz */ #define STM32_PLLCFG_PLL1CFG (RCC_PLLCFGR_PLL1VCOSEL_WIDE|RCC_PLLCFGR_PLL1RGE_4_8_MHZ|RCC_PLLCFGR_DIVP1EN|RCC_PLLCFGR_DIVQ1EN|RCC_PLLCFGR_DIVR1EN) -#define STM32_PLLCFG_PLL1M RCC_PLLCKSELR_DIVM1(2) -#define STM32_PLLCFG_PLL1N RCC_PLL1DIVR_N1(80) +#define STM32_PLLCFG_PLL1M RCC_PLLCKSELR_DIVM1(3) +#define STM32_PLLCFG_PLL1N RCC_PLL1DIVR_N1(100) #define STM32_PLLCFG_PLL1P RCC_PLL1DIVR_P1(2) -#define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR_Q1(4) -#define STM32_PLLCFG_PLL1R RCC_PLL1DIVR_R1(8) +#define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR_Q1(8) +#define STM32_PLLCFG_PLL1R RCC_PLL1DIVR_R1(2) -#define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 80) +#define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 3) * 100) #define STM32_PLL1P_FREQUENCY (STM32_VCO1_FREQUENCY / 2) -#define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / 4) -#define STM32_PLL1R_FREQUENCY (STM32_VCO1_FREQUENCY / 8) +#define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / 8) +#define STM32_PLL1R_FREQUENCY (STM32_VCO1_FREQUENCY / 2) /* PLL2 */ #define STM32_PLLCFG_PLL2CFG (RCC_PLLCFGR_PLL2VCOSEL_WIDE|RCC_PLLCFGR_PLL2RGE_4_8_MHZ|RCC_PLLCFGR_DIVP2EN|RCC_PLLCFGR_DIVQ2EN|RCC_PLLCFGR_DIVR2EN) -#define STM32_PLLCFG_PLL2M RCC_PLLCKSELR_DIVM2(4) -#define STM32_PLLCFG_PLL2N RCC_PLL2DIVR_N2(32) -#define STM32_PLLCFG_PLL2P RCC_PLL2DIVR_P2(2) -#define STM32_PLLCFG_PLL2Q RCC_PLL2DIVR_Q2(2) -#define STM32_PLLCFG_PLL2R RCC_PLL2DIVR_R2(2) +#define STM32_PLLCFG_PLL2M RCC_PLLCKSELR_DIVM2(2) +#define STM32_PLLCFG_PLL2N RCC_PLL2DIVR_N2(30) +#define STM32_PLLCFG_PLL2P RCC_PLL2DIVR_P2(4) +#define STM32_PLLCFG_PLL2Q RCC_PLL2DIVR_Q2(5) +#define STM32_PLLCFG_PLL2R RCC_PLL2DIVR_R2(1) -#define STM32_VCO2_FREQUENCY ((STM32_HSE_FREQUENCY / 4) * 32) -#define STM32_PLL2P_FREQUENCY (STM32_VCO2_FREQUENCY / 2) -#define STM32_PLL2Q_FREQUENCY (STM32_VCO2_FREQUENCY / 2) -#define STM32_PLL2R_FREQUENCY (STM32_VCO2_FREQUENCY / 2) +#define STM32_VCO2_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 30) +#define STM32_PLL2P_FREQUENCY (STM32_VCO2_FREQUENCY / 4) +#define STM32_PLL2Q_FREQUENCY (STM32_VCO2_FREQUENCY / 5) +#define STM32_PLL2R_FREQUENCY (STM32_VCO2_FREQUENCY / 1) /* PLL3 */ #define STM32_PLLCFG_PLL3CFG (RCC_PLLCFGR_PLL3VCOSEL_WIDE|RCC_PLLCFGR_PLL3RGE_4_8_MHZ|RCC_PLLCFGR_DIVQ3EN) -#define STM32_PLLCFG_PLL3M RCC_PLLCKSELR_DIVM3(4) -#define STM32_PLLCFG_PLL3N RCC_PLL3DIVR_N3(32) -#define STM32_PLLCFG_PLL3P RCC_PLL3DIVR_P3(2) -#define STM32_PLLCFG_PLL3Q RCC_PLL3DIVR_Q3(4) -#define STM32_PLLCFG_PLL3R RCC_PLL3DIVR_R3(2) +#define STM32_PLLCFG_PLL3M RCC_PLLCKSELR_DIVM3(6) +#define STM32_PLLCFG_PLL3N RCC_PLL3DIVR_N3(72) +#define STM32_PLLCFG_PLL3P RCC_PLL3DIVR_P3(3) +#define STM32_PLLCFG_PLL3Q RCC_PLL3DIVR_Q3(6) +#define STM32_PLLCFG_PLL3R RCC_PLL3DIVR_R3(9) -#define STM32_VCO3_FREQUENCY ((STM32_HSE_FREQUENCY / 4) * 32) -#define STM32_PLL3P_FREQUENCY (STM32_VCO3_FREQUENCY / 2) -#define STM32_PLL3Q_FREQUENCY (STM32_VCO3_FREQUENCY / 4) -#define STM32_PLL3R_FREQUENCY (STM32_VCO3_FREQUENCY / 2) +#define STM32_VCO3_FREQUENCY ((STM32_HSE_FREQUENCY / 6) * 72) +#define STM32_PLL3P_FREQUENCY (STM32_VCO3_FREQUENCY / 3) +#define STM32_PLL3Q_FREQUENCY (STM32_VCO3_FREQUENCY / 6) +#define STM32_PLL3R_FREQUENCY (STM32_VCO3_FREQUENCY / 9) -/* SYSCLK = PLL1P = 480MHz - * CPUCLK = SYSCLK / 1 = 480 MHz +/* SYSCLK = PLL1P = 400MHz + * CPUCLK = SYSCLK / 1 = 400 MHz */ #define STM32_RCC_D1CFGR_D1CPRE (RCC_D1CFGR_D1CPRE_SYSCLK) #define STM32_SYSCLK_FREQUENCY (STM32_PLL1P_FREQUENCY) @@ -140,14 +138,14 @@ /* Configure Clock Assignments */ /* AHB clock (HCLK) is SYSCLK/2 (240 MHz max) - * HCLK1 = HCLK2 = HCLK3 = HCLK4 = 240 + * HCLK1 = HCLK2 = HCLK3 = HCLK4 = 200 */ #define STM32_RCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_SYSCLKd2 /* HCLK = SYSCLK / 2 */ #define STM32_ACLK_FREQUENCY (STM32_CPUCLK_FREQUENCY / 2) /* ACLK in D1, HCLK3 in D1 */ #define STM32_HCLK_FREQUENCY (STM32_CPUCLK_FREQUENCY / 2) /* HCLK in D2, HCLK4 in D3 */ #define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */ -/* APB1 clock (PCLK1) is HCLK/2 (120 MHz) */ +/* APB1 clock (PCLK1) is HCLK/4 (120 MHz) */ #define STM32_RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) @@ -186,37 +184,29 @@ /* Kernel Clock Configuration * Note: look at Table 54 in ST Manual */ +#define STM32_RCC_D1CCIPR_SDMMCSEL RCC_D1CCIPR_SDMMC_PLL1 + #define STM32_RCC_D2CCIP2R_I2C123SRC RCC_D2CCIP2R_I2C123SEL_HSI /* I2C123 clock source */ -#define STM32_RCC_D3CCIPR_I2C4SRC RCC_D3CCIPR_I2C4SEL_HSI /* I2C4 clock source */ #define STM32_RCC_D2CCIP1R_SPI123SRC RCC_D2CCIP1R_SPI123SEL_PLL2 /* SPI123 clock source */ #define STM32_RCC_D2CCIP1R_SPI45SRC RCC_D2CCIP1R_SPI45SEL_PLL2 /* SPI45 clock source */ #define STM32_RCC_D3CCIPR_SPI6SRC RCC_D3CCIPR_SPI6SEL_PLL2 /* SPI6 clock source */ #define STM32_RCC_D2CCIP2R_USBSRC RCC_D2CCIP2R_USBSEL_PLL3 /* USB 1 and 2 clock source */ -#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 /* ADC 1 2 3 clock source */ #define STM32_RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_HSE /* FDCAN 1 2 clock source */ -#define STM32_FDCANCLK STM32_HSE_FREQUENCY +#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 /* ADC 1 2 3 clock source */ /* FLASH wait states */ #define BOARD_FLASH_WAITSTATES 2 /* SDMMC definitions ********************************************************/ /* Init 400kHz, freq = PLL1Q/(2*div) div = PLL1Q/(2*freq) */ -#define STM32_SDMMC_INIT_CLKDIV (300 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#define STM32_SDMMC_INIT_CLKDIV (125 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -/* 25 MHz Max for now, 25 mHZ = PLL1Q/(2*div), div = PLL1Q/(2*freq) - * div = 4.8 = 240 / 50, So round up to 5 for default speed 24 MB/s +/* 25 MHz Max for now, 25 mHZ = PLL1Q/(2*div), div = PLL1Q/(2*freq) + * div = 100 / (2*25) */ -#if defined(CONFIG_STM32H7_SDMMC_XDMA) || defined(CONFIG_STM32H7_SDMMC_IDMA) -# define STM32_SDMMC_MMCXFR_CLKDIV (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -#else -# define STM32_SDMMC_MMCXFR_CLKDIV (100 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -#endif -#if defined(CONFIG_STM32H7_SDMMC_XDMA) || defined(CONFIG_STM32H7_SDMMC_IDMA) -# define STM32_SDMMC_SDXFR_CLKDIV (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -#else -# define STM32_SDMMC_SDXFR_CLKDIV (100 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -#endif +#define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) #define STM32_SDMMC_CLKCR_EDGE STM32_SDMMC_CLKCR_NEGEDGE diff --git a/boards/mro/ctrl-zero-h7/nuttx-config/include/board.h b/boards/mro/ctrl-zero-h7/nuttx-config/include/board.h index 78a0048760..f34670a3db 100644 --- a/boards/mro/ctrl-zero-h7/nuttx-config/include/board.h +++ b/boards/mro/ctrl-zero-h7/nuttx-config/include/board.h @@ -60,7 +60,6 @@ #define STM32_HSI_FREQUENCY 16000000ul #define STM32_LSI_FREQUENCY 32000 #define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 0 /* Main PLL Configuration. * @@ -82,56 +81,55 @@ * PLLP2,3 = {2, 3, 4, ..., 128} * CPUCLK <= 480 MHz */ -#define STM32_PLLCFG_PLLSRC RCC_PLLCKSELR_PLLSRC_HSE /* PLL1, wide 4 - 8 MHz input, enable DIVP, DIVQ, DIVR * - * PLL1_VCO = (24,000,000 / 2) * 80 = 960 MHz + * PLL1_VCO = (24,000,000 / 3) * 100 = 800 MHz * - * PLL1P = PLL1_VCO/2 = 960 MHz / 2 = 480 MHz - * PLL1Q = PLL1_VCO/4 = 960 MHz / 4 = 240 MHz - * PLL1R = PLL1_VCO/8 = 960 MHz / 8 = 120 MHz + * PLL1P = PLL1_VCO/2 = 800 MHz / 2 = 400 MHz + * PLL1Q = PLL1_VCO/8 = 800 MHz / 8 = 100 MHz + * PLL1R = PLL1_VCO/2 = 800 MHz / 2 = 400 MHz */ #define STM32_PLLCFG_PLL1CFG (RCC_PLLCFGR_PLL1VCOSEL_WIDE|RCC_PLLCFGR_PLL1RGE_4_8_MHZ|RCC_PLLCFGR_DIVP1EN|RCC_PLLCFGR_DIVQ1EN|RCC_PLLCFGR_DIVR1EN) -#define STM32_PLLCFG_PLL1M RCC_PLLCKSELR_DIVM1(2) -#define STM32_PLLCFG_PLL1N RCC_PLL1DIVR_N1(80) +#define STM32_PLLCFG_PLL1M RCC_PLLCKSELR_DIVM1(3) +#define STM32_PLLCFG_PLL1N RCC_PLL1DIVR_N1(100) #define STM32_PLLCFG_PLL1P RCC_PLL1DIVR_P1(2) -#define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR_Q1(4) -#define STM32_PLLCFG_PLL1R RCC_PLL1DIVR_R1(8) +#define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR_Q1(8) +#define STM32_PLLCFG_PLL1R RCC_PLL1DIVR_R1(2) -#define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 80) +#define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 3) * 100) #define STM32_PLL1P_FREQUENCY (STM32_VCO1_FREQUENCY / 2) -#define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / 4) -#define STM32_PLL1R_FREQUENCY (STM32_VCO1_FREQUENCY / 8) +#define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / 8) +#define STM32_PLL1R_FREQUENCY (STM32_VCO1_FREQUENCY / 2) /* PLL2 */ #define STM32_PLLCFG_PLL2CFG (RCC_PLLCFGR_PLL2VCOSEL_WIDE|RCC_PLLCFGR_PLL2RGE_4_8_MHZ|RCC_PLLCFGR_DIVP2EN|RCC_PLLCFGR_DIVQ2EN|RCC_PLLCFGR_DIVR2EN) -#define STM32_PLLCFG_PLL2M RCC_PLLCKSELR_DIVM2(4) -#define STM32_PLLCFG_PLL2N RCC_PLL2DIVR_N2(32) -#define STM32_PLLCFG_PLL2P RCC_PLL2DIVR_P2(2) -#define STM32_PLLCFG_PLL2Q RCC_PLL2DIVR_Q2(2) -#define STM32_PLLCFG_PLL2R RCC_PLL2DIVR_R2(2) +#define STM32_PLLCFG_PLL2M RCC_PLLCKSELR_DIVM2(2) +#define STM32_PLLCFG_PLL2N RCC_PLL2DIVR_N2(30) +#define STM32_PLLCFG_PLL2P RCC_PLL2DIVR_P2(4) +#define STM32_PLLCFG_PLL2Q RCC_PLL2DIVR_Q2(5) +#define STM32_PLLCFG_PLL2R RCC_PLL2DIVR_R2(1) -#define STM32_VCO2_FREQUENCY ((STM32_HSE_FREQUENCY / 4) * 32) -#define STM32_PLL2P_FREQUENCY (STM32_VCO2_FREQUENCY / 2) -#define STM32_PLL2Q_FREQUENCY (STM32_VCO2_FREQUENCY / 2) -#define STM32_PLL2R_FREQUENCY (STM32_VCO2_FREQUENCY / 2) +#define STM32_VCO2_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 30) +#define STM32_PLL2P_FREQUENCY (STM32_VCO2_FREQUENCY / 4) +#define STM32_PLL2Q_FREQUENCY (STM32_VCO2_FREQUENCY / 5) +#define STM32_PLL2R_FREQUENCY (STM32_VCO2_FREQUENCY / 1) /* PLL3 */ #define STM32_PLLCFG_PLL3CFG (RCC_PLLCFGR_PLL3VCOSEL_WIDE|RCC_PLLCFGR_PLL3RGE_4_8_MHZ|RCC_PLLCFGR_DIVQ3EN) -#define STM32_PLLCFG_PLL3M RCC_PLLCKSELR_DIVM3(4) -#define STM32_PLLCFG_PLL3N RCC_PLL3DIVR_N3(32) -#define STM32_PLLCFG_PLL3P RCC_PLL3DIVR_P3(2) -#define STM32_PLLCFG_PLL3Q RCC_PLL3DIVR_Q3(4) -#define STM32_PLLCFG_PLL3R RCC_PLL3DIVR_R3(2) +#define STM32_PLLCFG_PLL3M RCC_PLLCKSELR_DIVM3(6) +#define STM32_PLLCFG_PLL3N RCC_PLL3DIVR_N3(72) +#define STM32_PLLCFG_PLL3P RCC_PLL3DIVR_P3(3) +#define STM32_PLLCFG_PLL3Q RCC_PLL3DIVR_Q3(6) +#define STM32_PLLCFG_PLL3R RCC_PLL3DIVR_R3(9) -#define STM32_VCO3_FREQUENCY ((STM32_HSE_FREQUENCY / 4) * 32) -#define STM32_PLL3P_FREQUENCY (STM32_VCO3_FREQUENCY / 2) -#define STM32_PLL3Q_FREQUENCY (STM32_VCO3_FREQUENCY / 4) -#define STM32_PLL3R_FREQUENCY (STM32_VCO3_FREQUENCY / 2) +#define STM32_VCO3_FREQUENCY ((STM32_HSE_FREQUENCY / 6) * 72) +#define STM32_PLL3P_FREQUENCY (STM32_VCO3_FREQUENCY / 3) +#define STM32_PLL3Q_FREQUENCY (STM32_VCO3_FREQUENCY / 6) +#define STM32_PLL3R_FREQUENCY (STM32_VCO3_FREQUENCY / 9) -/* SYSCLK = PLL1P = 480MHz - * CPUCLK = SYSCLK / 1 = 480 MHz +/* SYSCLK = PLL1P = 400MHz + * CPUCLK = SYSCLK / 1 = 400 MHz */ #define STM32_RCC_D1CFGR_D1CPRE (RCC_D1CFGR_D1CPRE_SYSCLK) #define STM32_SYSCLK_FREQUENCY (STM32_PLL1P_FREQUENCY) @@ -140,14 +138,14 @@ /* Configure Clock Assignments */ /* AHB clock (HCLK) is SYSCLK/2 (240 MHz max) - * HCLK1 = HCLK2 = HCLK3 = HCLK4 = 240 + * HCLK1 = HCLK2 = HCLK3 = HCLK4 = 200 */ #define STM32_RCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_SYSCLKd2 /* HCLK = SYSCLK / 2 */ #define STM32_ACLK_FREQUENCY (STM32_CPUCLK_FREQUENCY / 2) /* ACLK in D1, HCLK3 in D1 */ #define STM32_HCLK_FREQUENCY (STM32_CPUCLK_FREQUENCY / 2) /* HCLK in D2, HCLK4 in D3 */ #define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */ -/* APB1 clock (PCLK1) is HCLK/2 (120 MHz) */ +/* APB1 clock (PCLK1) is HCLK/4 (120 MHz) */ #define STM32_RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) @@ -186,36 +184,29 @@ /* Kernel Clock Configuration * Note: look at Table 54 in ST Manual */ +#define STM32_RCC_D1CCIPR_SDMMCSEL RCC_D1CCIPR_SDMMC_PLL1 + #define STM32_RCC_D2CCIP2R_I2C123SRC RCC_D2CCIP2R_I2C123SEL_HSI /* I2C123 clock source */ #define STM32_RCC_D2CCIP1R_SPI123SRC RCC_D2CCIP1R_SPI123SEL_PLL2 /* SPI123 clock source */ #define STM32_RCC_D2CCIP1R_SPI45SRC RCC_D2CCIP1R_SPI45SEL_PLL2 /* SPI45 clock source */ #define STM32_RCC_D3CCIPR_SPI6SRC RCC_D3CCIPR_SPI6SEL_PLL2 /* SPI6 clock source */ #define STM32_RCC_D2CCIP2R_USBSRC RCC_D2CCIP2R_USBSEL_PLL3 /* USB 1 and 2 clock source */ -#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 /* ADC 1 2 3 clock source */ #define STM32_RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_HSE /* FDCAN 1 2 clock source */ -#define STM32_FDCANCLK STM32_HSE_FREQUENCY +#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 /* ADC 1 2 3 clock source */ /* FLASH wait states */ #define BOARD_FLASH_WAITSTATES 2 /* SDMMC definitions ********************************************************/ /* Init 400kHz, freq = PLL1Q/(2*div) div = PLL1Q/(2*freq) */ -#define STM32_SDMMC_INIT_CLKDIV (300 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#define STM32_SDMMC_INIT_CLKDIV (125 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -/* 25 MHz Max for now, 25 mHZ = PLL1Q/(2*div), div = PLL1Q/(2*freq) - * div = 4.8 = 240 / 50, So round up to 5 for default speed 24 MB/s +/* 25 MHz Max for now, 25 mHZ = PLL1Q/(2*div), div = PLL1Q/(2*freq) + * div = 100 / (2*25) */ -#if defined(CONFIG_STM32H7_SDMMC_XDMA) || defined(CONFIG_STM32H7_SDMMC_IDMA) -# define STM32_SDMMC_MMCXFR_CLKDIV (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -#else -# define STM32_SDMMC_MMCXFR_CLKDIV (100 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -#endif -#if defined(CONFIG_STM32H7_SDMMC_XDMA) || defined(CONFIG_STM32H7_SDMMC_IDMA) -# define STM32_SDMMC_SDXFR_CLKDIV (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -#else -# define STM32_SDMMC_SDXFR_CLKDIV (100 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -#endif +#define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) #define STM32_SDMMC_CLKCR_EDGE STM32_SDMMC_CLKCR_NEGEDGE diff --git a/boards/mro/pixracerpro/nuttx-config/include/board.h b/boards/mro/pixracerpro/nuttx-config/include/board.h index 2377d529f4..a18d6e38ab 100644 --- a/boards/mro/pixracerpro/nuttx-config/include/board.h +++ b/boards/mro/pixracerpro/nuttx-config/include/board.h @@ -60,7 +60,6 @@ #define STM32_HSI_FREQUENCY 16000000ul #define STM32_LSI_FREQUENCY 32000 #define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 0 /* Main PLL Configuration. * @@ -82,56 +81,55 @@ * PLLP2,3 = {2, 3, 4, ..., 128} * CPUCLK <= 480 MHz */ -#define STM32_PLLCFG_PLLSRC RCC_PLLCKSELR_PLLSRC_HSE /* PLL1, wide 4 - 8 MHz input, enable DIVP, DIVQ, DIVR * - * PLL1_VCO = (24,000,000 / 2) * 80 = 960 MHz + * PLL1_VCO = (24,000,000 / 3) * 100 = 800 MHz * - * PLL1P = PLL1_VCO/2 = 960 MHz / 2 = 480 MHz - * PLL1Q = PLL1_VCO/4 = 960 MHz / 4 = 240 MHz - * PLL1R = PLL1_VCO/8 = 960 MHz / 8 = 120 MHz + * PLL1P = PLL1_VCO/2 = 800 MHz / 2 = 400 MHz + * PLL1Q = PLL1_VCO/8 = 800 MHz / 8 = 100 MHz + * PLL1R = PLL1_VCO/2 = 800 MHz / 2 = 400 MHz */ #define STM32_PLLCFG_PLL1CFG (RCC_PLLCFGR_PLL1VCOSEL_WIDE|RCC_PLLCFGR_PLL1RGE_4_8_MHZ|RCC_PLLCFGR_DIVP1EN|RCC_PLLCFGR_DIVQ1EN|RCC_PLLCFGR_DIVR1EN) -#define STM32_PLLCFG_PLL1M RCC_PLLCKSELR_DIVM1(2) -#define STM32_PLLCFG_PLL1N RCC_PLL1DIVR_N1(80) +#define STM32_PLLCFG_PLL1M RCC_PLLCKSELR_DIVM1(3) +#define STM32_PLLCFG_PLL1N RCC_PLL1DIVR_N1(100) #define STM32_PLLCFG_PLL1P RCC_PLL1DIVR_P1(2) -#define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR_Q1(4) -#define STM32_PLLCFG_PLL1R RCC_PLL1DIVR_R1(8) +#define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR_Q1(8) +#define STM32_PLLCFG_PLL1R RCC_PLL1DIVR_R1(2) -#define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 80) +#define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 3) * 100) #define STM32_PLL1P_FREQUENCY (STM32_VCO1_FREQUENCY / 2) -#define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / 4) -#define STM32_PLL1R_FREQUENCY (STM32_VCO1_FREQUENCY / 8) +#define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / 8) +#define STM32_PLL1R_FREQUENCY (STM32_VCO1_FREQUENCY / 2) /* PLL2 */ #define STM32_PLLCFG_PLL2CFG (RCC_PLLCFGR_PLL2VCOSEL_WIDE|RCC_PLLCFGR_PLL2RGE_4_8_MHZ|RCC_PLLCFGR_DIVP2EN|RCC_PLLCFGR_DIVQ2EN|RCC_PLLCFGR_DIVR2EN) -#define STM32_PLLCFG_PLL2M RCC_PLLCKSELR_DIVM2(4) -#define STM32_PLLCFG_PLL2N RCC_PLL2DIVR_N2(32) -#define STM32_PLLCFG_PLL2P RCC_PLL2DIVR_P2(2) -#define STM32_PLLCFG_PLL2Q RCC_PLL2DIVR_Q2(2) -#define STM32_PLLCFG_PLL2R RCC_PLL2DIVR_R2(2) +#define STM32_PLLCFG_PLL2M RCC_PLLCKSELR_DIVM2(2) +#define STM32_PLLCFG_PLL2N RCC_PLL2DIVR_N2(30) +#define STM32_PLLCFG_PLL2P RCC_PLL2DIVR_P2(4) +#define STM32_PLLCFG_PLL2Q RCC_PLL2DIVR_Q2(5) +#define STM32_PLLCFG_PLL2R RCC_PLL2DIVR_R2(1) -#define STM32_VCO2_FREQUENCY ((STM32_HSE_FREQUENCY / 4) * 32) -#define STM32_PLL2P_FREQUENCY (STM32_VCO2_FREQUENCY / 2) -#define STM32_PLL2Q_FREQUENCY (STM32_VCO2_FREQUENCY / 2) -#define STM32_PLL2R_FREQUENCY (STM32_VCO2_FREQUENCY / 2) +#define STM32_VCO2_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 30) +#define STM32_PLL2P_FREQUENCY (STM32_VCO2_FREQUENCY / 4) +#define STM32_PLL2Q_FREQUENCY (STM32_VCO2_FREQUENCY / 5) +#define STM32_PLL2R_FREQUENCY (STM32_VCO2_FREQUENCY / 1) /* PLL3 */ #define STM32_PLLCFG_PLL3CFG (RCC_PLLCFGR_PLL3VCOSEL_WIDE|RCC_PLLCFGR_PLL3RGE_4_8_MHZ|RCC_PLLCFGR_DIVQ3EN) -#define STM32_PLLCFG_PLL3M RCC_PLLCKSELR_DIVM3(4) -#define STM32_PLLCFG_PLL3N RCC_PLL3DIVR_N3(32) -#define STM32_PLLCFG_PLL3P RCC_PLL3DIVR_P3(2) -#define STM32_PLLCFG_PLL3Q RCC_PLL3DIVR_Q3(4) -#define STM32_PLLCFG_PLL3R RCC_PLL3DIVR_R3(2) +#define STM32_PLLCFG_PLL3M RCC_PLLCKSELR_DIVM3(6) +#define STM32_PLLCFG_PLL3N RCC_PLL3DIVR_N3(72) +#define STM32_PLLCFG_PLL3P RCC_PLL3DIVR_P3(3) +#define STM32_PLLCFG_PLL3Q RCC_PLL3DIVR_Q3(6) +#define STM32_PLLCFG_PLL3R RCC_PLL3DIVR_R3(9) -#define STM32_VCO3_FREQUENCY ((STM32_HSE_FREQUENCY / 4) * 32) -#define STM32_PLL3P_FREQUENCY (STM32_VCO3_FREQUENCY / 2) -#define STM32_PLL3Q_FREQUENCY (STM32_VCO3_FREQUENCY / 4) -#define STM32_PLL3R_FREQUENCY (STM32_VCO3_FREQUENCY / 2) +#define STM32_VCO3_FREQUENCY ((STM32_HSE_FREQUENCY / 6) * 72) +#define STM32_PLL3P_FREQUENCY (STM32_VCO3_FREQUENCY / 3) +#define STM32_PLL3Q_FREQUENCY (STM32_VCO3_FREQUENCY / 6) +#define STM32_PLL3R_FREQUENCY (STM32_VCO3_FREQUENCY / 9) -/* SYSCLK = PLL1P = 480MHz - * CPUCLK = SYSCLK / 1 = 480 MHz +/* SYSCLK = PLL1P = 400MHz + * CPUCLK = SYSCLK / 1 = 400 MHz */ #define STM32_RCC_D1CFGR_D1CPRE (RCC_D1CFGR_D1CPRE_SYSCLK) #define STM32_SYSCLK_FREQUENCY (STM32_PLL1P_FREQUENCY) @@ -140,14 +138,14 @@ /* Configure Clock Assignments */ /* AHB clock (HCLK) is SYSCLK/2 (240 MHz max) - * HCLK1 = HCLK2 = HCLK3 = HCLK4 = 240 + * HCLK1 = HCLK2 = HCLK3 = HCLK4 = 200 */ #define STM32_RCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_SYSCLKd2 /* HCLK = SYSCLK / 2 */ #define STM32_ACLK_FREQUENCY (STM32_CPUCLK_FREQUENCY / 2) /* ACLK in D1, HCLK3 in D1 */ #define STM32_HCLK_FREQUENCY (STM32_CPUCLK_FREQUENCY / 2) /* HCLK in D2, HCLK4 in D3 */ #define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */ -/* APB1 clock (PCLK1) is HCLK/2 (120 MHz) */ +/* APB1 clock (PCLK1) is HCLK/4 (120 MHz) */ #define STM32_RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) @@ -186,36 +184,29 @@ /* Kernel Clock Configuration * Note: look at Table 54 in ST Manual */ +#define STM32_RCC_D1CCIPR_SDMMCSEL RCC_D1CCIPR_SDMMC_PLL1 + #define STM32_RCC_D2CCIP2R_I2C123SRC RCC_D2CCIP2R_I2C123SEL_HSI /* I2C123 clock source */ #define STM32_RCC_D2CCIP1R_SPI123SRC RCC_D2CCIP1R_SPI123SEL_PLL2 /* SPI123 clock source */ #define STM32_RCC_D2CCIP1R_SPI45SRC RCC_D2CCIP1R_SPI45SEL_PLL2 /* SPI45 clock source */ #define STM32_RCC_D3CCIPR_SPI6SRC RCC_D3CCIPR_SPI6SEL_PLL2 /* SPI6 clock source */ #define STM32_RCC_D2CCIP2R_USBSRC RCC_D2CCIP2R_USBSEL_PLL3 /* USB 1 and 2 clock source */ -#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 /* ADC 1 2 3 clock source */ #define STM32_RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_HSE /* FDCAN 1 2 clock source */ -#define STM32_FDCANCLK STM32_HSE_FREQUENCY +#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 /* ADC 1 2 3 clock source */ /* FLASH wait states */ #define BOARD_FLASH_WAITSTATES 2 /* SDMMC definitions ********************************************************/ /* Init 400kHz, freq = PLL1Q/(2*div) div = PLL1Q/(2*freq) */ -#define STM32_SDMMC_INIT_CLKDIV (300 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#define STM32_SDMMC_INIT_CLKDIV (125 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -/* 25 MHz Max for now, 25 mHZ = PLL1Q/(2*div), div = PLL1Q/(2*freq) - * div = 4.8 = 240 / 50, So round up to 5 for default speed 24 MB/s +/* 25 MHz Max for now, 25 mHZ = PLL1Q/(2*div), div = PLL1Q/(2*freq) + * div = 100 / (2*25) */ -#if defined(CONFIG_STM32H7_SDMMC_XDMA) || defined(CONFIG_STM32H7_SDMMC_IDMA) -# define STM32_SDMMC_MMCXFR_CLKDIV (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -#else -# define STM32_SDMMC_MMCXFR_CLKDIV (100 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -#endif -#if defined(CONFIG_STM32H7_SDMMC_XDMA) || defined(CONFIG_STM32H7_SDMMC_IDMA) -# define STM32_SDMMC_SDXFR_CLKDIV (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -#else -# define STM32_SDMMC_SDXFR_CLKDIV (100 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -#endif +#define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) #define STM32_SDMMC_CLKCR_EDGE STM32_SDMMC_CLKCR_NEGEDGE