mirror of
https://gitee.com/mirrors_PX4/PX4-Autopilot.git
synced 2026-05-23 16:47:35 +08:00
Enable ARKV6X SPIX SYNC, enable icm426889 and iim42652 CLKIN
This commit is contained in:
alexklimaj
@@ -1,6 +1,6 @@
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############################################################################
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#
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# Copyright (c) 2020 PX4 Development Team. All rights reserved.
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# Copyright (c) 2020-2023 PX4 Development Team. All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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@@ -35,6 +35,7 @@ px4_add_module(
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MAIN icm42688p
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COMPILE_FLAGS
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${MAX_CUSTOM_OPT_LEVEL}
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#-DDEBUG_BUILD
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SRCS
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icm42688p_main.cpp
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ICM42688P.cpp
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@@ -1,6 +1,6 @@
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/****************************************************************************
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*
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* Copyright (c) 2020-2022 PX4 Development Team. All rights reserved.
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* Copyright (c) 2020-2023 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@@ -40,6 +40,11 @@ static constexpr int16_t combine(uint8_t msb, uint8_t lsb)
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return (msb << 8u) | lsb;
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}
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static constexpr uint16_t combine_uint(uint8_t msb, uint8_t lsb)
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{
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return (msb << 8u) | lsb;
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}
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ICM42688P::ICM42688P(const I2CSPIDriverConfig &config) :
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SPI(config),
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I2CSPIDriver(config),
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@@ -51,6 +56,15 @@ ICM42688P::ICM42688P(const I2CSPIDriverConfig &config) :
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_drdy_missed_perf = perf_alloc(PC_COUNT, MODULE_NAME": DRDY missed");
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}
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if (config.custom1 != 0) {
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_enable_clock_input = true;
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_input_clock_freq = config.custom1;
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ConfigureCLKIN();
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} else {
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_enable_clock_input = false;
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}
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ConfigureSampleRate(_px4_gyro.get_max_rate_hz());
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}
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@@ -96,6 +110,7 @@ void ICM42688P::print_status()
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I2CSPIDriverBase::print_status();
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PX4_INFO("FIFO empty interval: %d us (%.1f Hz)", _fifo_empty_interval_us, 1e6 / _fifo_empty_interval_us);
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PX4_INFO("Clock input: %s", _enable_clock_input ? "enabled" : "disabled");
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perf_print_counter(_bad_register_perf);
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perf_print_counter(_bad_transfer_perf);
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@@ -334,6 +349,22 @@ void ICM42688P::ConfigureFIFOWatermark(uint8_t samples)
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}
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}
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void ICM42688P::ConfigureCLKIN()
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{
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for (auto &r0 : _register_bank0_cfg) {
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if (r0.reg == Register::BANK_0::INTF_CONFIG1) {
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r0.set_bits = INTF_CONFIG1_BIT::RTC_MODE;
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}
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}
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for (auto &r1 : _register_bank1_cfg) {
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if (r1.reg == Register::BANK_1::INTF_CONFIG5) {
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r1.set_bits = PIN9_FUNCTION_BIT::CLKIN;
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r1.clear_bits = PIN9_FUNCTION_BIT::FSYNC_PIN9;
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}
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}
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}
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void ICM42688P::SelectRegisterBank(enum REG_BANK_SEL_BIT bank, bool force)
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{
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if (bank != _last_register_bank || force) {
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@@ -544,6 +575,10 @@ bool ICM42688P::FIFORead(const hrt_abstime ×tamp_sample, uint8_t samples)
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// Packet does not contain a new and valid extended 20-bit data
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valid = false;
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} else if ((FIFO_HEADER & FIFO::FIFO_HEADER_BIT::HEADER_TIMESTAMP_FSYNC) != Bit3) {
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// Packet does not contain ODR timestamp
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valid = false;
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} else if (FIFO_HEADER & FIFO::FIFO_HEADER_BIT::HEADER_ODR_ACCEL) {
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// accel ODR changed
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valid = false;
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@@ -606,13 +641,22 @@ void ICM42688P::ProcessAccel(const hrt_abstime ×tamp_sample, const FIFO::DA
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sensor_accel_fifo_s accel{};
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accel.timestamp_sample = timestamp_sample;
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accel.samples = 0;
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accel.dt = FIFO_SAMPLE_DT;
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// 18-bits of accelerometer data
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bool scale_20bit = false;
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// first pass
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for (int i = 0; i < samples; i++) {
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uint16_t timestamp_fifo = combine_uint(fifo[i].TimeStamp_h, fifo[i].TimeStamp_l);
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if (_enable_clock_input) {
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accel.dt = (float)timestamp_fifo * ((1.f / _input_clock_freq) * 1e6f);
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} else {
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accel.dt = (float)timestamp_fifo * FIFO_TIMESTAMP_SCALING;
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}
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// 20 bit hires mode
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// Sign extension + Accel [19:12] + Accel [11:4] + Accel [3:2] (20 bit extension byte)
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// Accel data is 18 bit ()
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@@ -693,13 +737,22 @@ void ICM42688P::ProcessGyro(const hrt_abstime ×tamp_sample, const FIFO::DAT
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sensor_gyro_fifo_s gyro{};
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gyro.timestamp_sample = timestamp_sample;
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gyro.samples = 0;
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gyro.dt = FIFO_SAMPLE_DT;
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// 20-bits of gyroscope data
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bool scale_20bit = false;
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// first pass
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for (int i = 0; i < samples; i++) {
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uint16_t timestamp_fifo = combine_uint(fifo[i].TimeStamp_h, fifo[i].TimeStamp_l);
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if (_enable_clock_input) {
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gyro.dt = (float)timestamp_fifo * ((1.f / _input_clock_freq) * 1e6f);
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} else {
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gyro.dt = (float)timestamp_fifo * FIFO_TIMESTAMP_SCALING;
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}
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// 20 bit hires mode
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// Gyro [19:12] + Gyro [11:4] + Gyro [3:0] (bottom 4 bits of 20 bit extension byte)
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int32_t gyro_x = reassemble_20bit(fifo[i].GYRO_DATA_X1, fifo[i].GYRO_DATA_X0, fifo[i].Ext_Accel_X_Gyro_X & 0x0F);
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@@ -1,6 +1,6 @@
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/****************************************************************************
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*
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* Copyright (c) 2020-2021 PX4 Development Team. All rights reserved.
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* Copyright (c) 2020-2023 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@@ -74,6 +74,8 @@ private:
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static constexpr float GYRO_RATE{1e6f / FIFO_SAMPLE_DT};
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static constexpr float ACCEL_RATE{1e6f / FIFO_SAMPLE_DT};
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static constexpr float FIFO_TIMESTAMP_SCALING{16.f *(32.f / 30.f)}; // Used when not using clock input
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// maximum FIFO samples per transfer is limited to the size of sensor_accel_fifo/sensor_gyro_fifo
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static constexpr int32_t FIFO_MAX_SAMPLES{math::min(FIFO::SIZE / sizeof(FIFO::DATA), sizeof(sensor_gyro_fifo_s::x) / sizeof(sensor_gyro_fifo_s::x[0]), sizeof(sensor_accel_fifo_s::x) / sizeof(sensor_accel_fifo_s::x[0]) * (int)(GYRO_RATE / ACCEL_RATE))};
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@@ -113,6 +115,7 @@ private:
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bool Configure();
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void ConfigureSampleRate(int sample_rate);
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void ConfigureFIFOWatermark(uint8_t samples);
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void ConfigureCLKIN();
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void SelectRegisterBank(enum REG_BANK_SEL_BIT bank, bool force = false);
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void SelectRegisterBank(Register::BANK_0 reg) { SelectRegisterBank(REG_BANK_SEL_BIT::BANK_SEL_0); }
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@@ -156,6 +159,9 @@ private:
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hrt_abstime _temperature_update_timestamp{0};
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int _failure_count{0};
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bool _enable_clock_input{false};
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float _input_clock_freq{0.f};
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enum REG_BANK_SEL_BIT _last_register_bank {REG_BANK_SEL_BIT::BANK_SEL_0};
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px4::atomic<hrt_abstime> _drdy_timestamp_sample{0};
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@@ -173,18 +179,20 @@ private:
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int32_t _fifo_gyro_samples{static_cast<int32_t>(_fifo_empty_interval_us / (1000000 / GYRO_RATE))};
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uint8_t _checked_register_bank0{0};
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static constexpr uint8_t size_register_bank0_cfg{14};
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static constexpr uint8_t size_register_bank0_cfg{16};
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register_bank0_config_t _register_bank0_cfg[size_register_bank0_cfg] {
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// Register | Set bits, Clear bits
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{ Register::BANK_0::INT_CONFIG, INT_CONFIG_BIT::INT1_MODE | INT_CONFIG_BIT::INT1_DRIVE_CIRCUIT, INT_CONFIG_BIT::INT1_POLARITY },
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{ Register::BANK_0::FIFO_CONFIG, FIFO_CONFIG_BIT::FIFO_MODE_STOP_ON_FULL, 0 },
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{ Register::BANK_0::INTF_CONFIG1, 0, 0}, // RTC_MODE[2] set at runtime
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{ Register::BANK_0::PWR_MGMT0, PWR_MGMT0_BIT::GYRO_MODE_LOW_NOISE | PWR_MGMT0_BIT::ACCEL_MODE_LOW_NOISE, 0 },
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{ Register::BANK_0::GYRO_CONFIG0, GYRO_CONFIG0_BIT::GYRO_FS_SEL_2000_DPS | GYRO_CONFIG0_BIT::GYRO_ODR_8KHZ_SET, GYRO_CONFIG0_BIT::GYRO_ODR_8KHZ_CLEAR },
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{ Register::BANK_0::ACCEL_CONFIG0, ACCEL_CONFIG0_BIT::ACCEL_FS_SEL_16G | ACCEL_CONFIG0_BIT::ACCEL_ODR_8KHZ_SET, ACCEL_CONFIG0_BIT::ACCEL_ODR_8KHZ_CLEAR },
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{ Register::BANK_0::GYRO_CONFIG1, 0, GYRO_CONFIG1_BIT::GYRO_UI_FILT_ORD },
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{ Register::BANK_0::GYRO_ACCEL_CONFIG0, 0, GYRO_ACCEL_CONFIG0_BIT::ACCEL_UI_FILT_BW | GYRO_ACCEL_CONFIG0_BIT::GYRO_UI_FILT_BW },
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{ Register::BANK_0::ACCEL_CONFIG1, 0, ACCEL_CONFIG1_BIT::ACCEL_UI_FILT_ORD },
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{ Register::BANK_0::FIFO_CONFIG1, FIFO_CONFIG1_BIT::FIFO_WM_GT_TH | FIFO_CONFIG1_BIT::FIFO_HIRES_EN | FIFO_CONFIG1_BIT::FIFO_TEMP_EN | FIFO_CONFIG1_BIT::FIFO_GYRO_EN | FIFO_CONFIG1_BIT::FIFO_ACCEL_EN, 0 },
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{ Register::BANK_0::TMST_CONFIG, TMST_CONFIG_BIT::TMST_EN | TMST_CONFIG_BIT::TMST_DELTA_EN | TMST_CONFIG_BIT::TMST_TO_REGS_EN | TMST_CONFIG_BIT::TMST_RES, TMST_CONFIG_BIT::TMST_FSYNC_EN },
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{ Register::BANK_0::FIFO_CONFIG1, FIFO_CONFIG1_BIT::FIFO_WM_GT_TH | FIFO_CONFIG1_BIT::FIFO_HIRES_EN | FIFO_CONFIG1_BIT::FIFO_TEMP_EN | FIFO_CONFIG1_BIT::FIFO_GYRO_EN | FIFO_CONFIG1_BIT::FIFO_ACCEL_EN, FIFO_CONFIG1_BIT::FIFO_TMST_FSYNC_EN },
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{ Register::BANK_0::FIFO_CONFIG2, 0, 0 }, // FIFO_WM[7:0] set at runtime
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{ Register::BANK_0::FIFO_CONFIG3, 0, 0 }, // FIFO_WM[11:8] set at runtime
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{ Register::BANK_0::INT_CONFIG0, INT_CONFIG0_BIT::CLEAR_ON_FIFO_READ, 0 },
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@@ -193,10 +201,11 @@ private:
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};
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uint8_t _checked_register_bank1{0};
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static constexpr uint8_t size_register_bank1_cfg{1};
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static constexpr uint8_t size_register_bank1_cfg{2};
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register_bank1_config_t _register_bank1_cfg[size_register_bank1_cfg] {
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// Register | Set bits, Clear bits
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{ Register::BANK_1::GYRO_CONFIG_STATIC2, GYRO_CONFIG_STATIC2_BIT::GYRO_AAF_DIS | GYRO_CONFIG_STATIC2_BIT::GYRO_NF_DIS, 0 },
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{ Register::BANK_1::INTF_CONFIG5, 0, 0 },
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};
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uint8_t _checked_register_bank2{0};
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@@ -90,6 +90,7 @@ enum class BANK_0 : uint8_t {
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GYRO_CONFIG1 = 0x51,
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GYRO_ACCEL_CONFIG0 = 0x52,
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ACCEL_CONFIG1 = 0x53,
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TMST_CONFIG = 0x54,
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FIFO_CONFIG1 = 0x5F,
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FIFO_CONFIG2 = 0x60,
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@@ -108,7 +109,6 @@ enum class BANK_0 : uint8_t {
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enum class BANK_1 : uint8_t {
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GYRO_CONFIG_STATIC2 = 0x0B,
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INTF_CONFIG5 = 0x7B,
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};
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@@ -152,6 +152,12 @@ enum SIGNAL_PATH_RESET_BIT : uint8_t {
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FIFO_FLUSH = Bit1,
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};
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enum INTF_CONFIG1_BIT : uint8_t {
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RTC_MODE = Bit2, // 0: No input RTC clock is required, 1: RTC clock input is required
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CLKSEL = Bit0,
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CLKSEL_CLEAR = Bit1,
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};
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// PWR_MGMT0
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enum PWR_MGMT0_BIT : uint8_t {
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GYRO_MODE_LOW_NOISE = Bit3 | Bit2, // 11: Places gyroscope in Low Noise (LN) Mode
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@@ -226,11 +232,21 @@ enum ACCEL_CONFIG1_BIT : uint8_t {
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ACCEL_UI_FILT_ORD = Bit4 | Bit3, // 00: 1st Order
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};
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// TMST_CONFIG
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enum TMST_CONFIG_BIT : uint8_t {
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TMST_TO_REGS_EN = Bit4, // 1: TMST_VALUE[19:0] read returns timestamp value
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TMST_RES = Bit3, // 0: 1us resolution, 1: 16us resolution or 1 RTC period when clock is used
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TMST_DELTA_EN = Bit2, // 1: Time Stamp delta enable
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TMST_FSYNC_EN = Bit1, // 1: The contents of the Timestamp feature of FSYNC is enabled
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TMST_EN = Bit0, // 1: Time Stamp register enable (default)
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};
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// FIFO_CONFIG1
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enum FIFO_CONFIG1_BIT : uint8_t {
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FIFO_RESUME_PARTIAL_RD = Bit6,
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FIFO_WM_GT_TH = Bit5,
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FIFO_HIRES_EN = Bit4,
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FIFO_TMST_FSYNC_EN = Bit3,
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FIFO_TEMP_EN = Bit2,
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FIFO_GYRO_EN = Bit1,
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FIFO_ACCEL_EN = Bit0,
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@@ -277,6 +293,11 @@ enum GYRO_CONFIG_STATIC2_BIT : uint8_t {
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GYRO_NF_DIS = Bit0,
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};
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// PIN9_FUNCTION
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enum PIN9_FUNCTION_BIT : uint8_t {
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FSYNC_PIN9 = Bit1,
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CLKIN = Bit2,
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};
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//---------------- BANK2 Register bits
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@@ -321,7 +342,7 @@ enum FIFO_HEADER_BIT : uint8_t {
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HEADER_ACCEL = Bit6, // 1: Packet is sized so that accel data have location in the packet, FIFO_ACCEL_EN must be 1
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HEADER_GYRO = Bit5, // 1: Packet is sized so that gyro data have location in the packet, FIFO_GYRO_EN must be1
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HEADER_20 = Bit4, // 1: Packet has a new and valid sample of extended 20-bit data for gyro and/or accel
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HEADER_TIMESTAMP_FSYNC = Bit3 | Bit2,
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HEADER_TIMESTAMP_FSYNC = Bit3 | Bit2, // 10: Packet contains ODR Timestamp
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HEADER_ODR_ACCEL = Bit1, // 1: The ODR for accel is different for this accel data packet compared to the previous accel packet
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HEADER_ODR_GYRO = Bit0, // 1: The ODR for gyro is different for this gyro data packet compared to the previous gyro packet
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};
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@@ -1,6 +1,6 @@
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/****************************************************************************
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*
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* Copyright (c) 2020-2021 PX4 Development Team. All rights reserved.
|
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* Copyright (c) 2020-2023 PX4 Development Team. All rights reserved.
|
||||
*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
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@@ -43,6 +43,7 @@ void ICM42688P::print_usage()
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PRINT_MODULE_USAGE_COMMAND("start");
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PRINT_MODULE_USAGE_PARAMS_I2C_SPI_DRIVER(false, true);
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PRINT_MODULE_USAGE_PARAM_INT('R', 0, 0, 35, "Rotation", true);
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PRINT_MODULE_USAGE_PARAM_INT('C', 0, 0, 35000, "Input clock frequency (Hz)", true);
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PRINT_MODULE_USAGE_DEFAULT_COMMANDS();
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}
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@@ -53,8 +54,12 @@ extern "C" int icm42688p_main(int argc, char *argv[])
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BusCLIArguments cli{false, true};
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cli.default_spi_frequency = SPI_SPEED;
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while ((ch = cli.getOpt(argc, argv, "R:")) != EOF) {
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while ((ch = cli.getOpt(argc, argv, "C:R:")) != EOF) {
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switch (ch) {
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case 'C':
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cli.custom1 = atoi(cli.optArg());
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break;
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case 'R':
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cli.rotation = (enum Rotation)atoi(cli.optArg());
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break;
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@@ -35,6 +35,7 @@ px4_add_module(
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MAIN iim42652
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COMPILE_FLAGS
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${MAX_CUSTOM_OPT_LEVEL}
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#-DDEBUG_BUILD
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SRCS
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iim42652_main.cpp
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IIM42652.cpp
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@@ -1,6 +1,6 @@
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/****************************************************************************
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*
|
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* Copyright (c) 2022 PX4 Development Team. All rights reserved.
|
||||
* Copyright (c) 2023 PX4 Development Team. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -40,6 +40,11 @@ static constexpr int16_t combine(uint8_t msb, uint8_t lsb)
|
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return (msb << 8u) | lsb;
|
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}
|
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static constexpr uint16_t combine_uint(uint8_t msb, uint8_t lsb)
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{
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return (msb << 8u) | lsb;
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}
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IIM42652::IIM42652(const I2CSPIDriverConfig &config) :
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SPI(config),
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I2CSPIDriver(config),
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@@ -51,6 +56,15 @@ IIM42652::IIM42652(const I2CSPIDriverConfig &config) :
|
||||
_drdy_missed_perf = perf_alloc(PC_COUNT, MODULE_NAME": DRDY missed");
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||||
}
|
||||
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if (config.custom1 != 0) {
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_enable_clock_input = true;
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_input_clock_freq = config.custom1;
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ConfigureCLKIN();
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} else {
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_enable_clock_input = false;
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}
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ConfigureSampleRate(_px4_gyro.get_max_rate_hz());
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}
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@@ -96,6 +110,7 @@ void IIM42652::print_status()
|
||||
I2CSPIDriverBase::print_status();
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|
||||
PX4_INFO("FIFO empty interval: %d us (%.1f Hz)", _fifo_empty_interval_us, 1e6 / _fifo_empty_interval_us);
|
||||
PX4_INFO("Clock input: %s", _enable_clock_input ? "enabled" : "disabled");
|
||||
|
||||
perf_print_counter(_bad_register_perf);
|
||||
perf_print_counter(_bad_transfer_perf);
|
||||
@@ -122,7 +137,7 @@ int IIM42652::probe()
|
||||
if (bank >= 1 && bank <= 3) {
|
||||
DEVICE_DEBUG("incorrect register bank for WHO_AM_I REG_BANK_SEL:0x%02x, bank:%d", reg_bank_sel, bank);
|
||||
// force bank selection and retry
|
||||
SelectRegisterBank(REG_BANK_SEL_BIT::USER_BANK_0, true);
|
||||
SelectRegisterBank(REG_BANK_SEL_BIT::BANK_SEL_0, true);
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -171,21 +186,9 @@ void IIM42652::RunImpl()
|
||||
|
||||
case STATE::CONFIGURE:
|
||||
if (Configure()) {
|
||||
// if configure succeeded then start reading from FIFO
|
||||
_state = STATE::FIFO_READ;
|
||||
|
||||
if (DataReadyInterruptConfigure()) {
|
||||
_data_ready_interrupt_enabled = true;
|
||||
|
||||
// backup schedule as a watchdog timeout
|
||||
ScheduleDelayed(100_ms);
|
||||
|
||||
} else {
|
||||
_data_ready_interrupt_enabled = false;
|
||||
ScheduleOnInterval(_fifo_empty_interval_us, _fifo_empty_interval_us);
|
||||
}
|
||||
|
||||
FIFOReset();
|
||||
// if configure succeeded then reset the FIFO
|
||||
_state = STATE::FIFO_RESET;
|
||||
ScheduleDelayed(1_ms);
|
||||
|
||||
} else {
|
||||
// CONFIGURE not complete
|
||||
@@ -202,6 +205,24 @@ void IIM42652::RunImpl()
|
||||
|
||||
break;
|
||||
|
||||
case STATE::FIFO_RESET:
|
||||
|
||||
_state = STATE::FIFO_READ;
|
||||
FIFOReset();
|
||||
|
||||
if (DataReadyInterruptConfigure()) {
|
||||
_data_ready_interrupt_enabled = true;
|
||||
|
||||
// backup schedule as a watchdog timeout
|
||||
ScheduleDelayed(100_ms);
|
||||
|
||||
} else {
|
||||
_data_ready_interrupt_enabled = false;
|
||||
ScheduleOnInterval(_fifo_empty_interval_us, _fifo_empty_interval_us);
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case STATE::FIFO_READ: {
|
||||
hrt_abstime timestamp_sample = now;
|
||||
uint8_t samples = 0;
|
||||
@@ -328,6 +349,22 @@ void IIM42652::ConfigureFIFOWatermark(uint8_t samples)
|
||||
}
|
||||
}
|
||||
|
||||
void IIM42652::ConfigureCLKIN()
|
||||
{
|
||||
for (auto &r0 : _register_bank0_cfg) {
|
||||
if (r0.reg == Register::BANK_0::INTF_CONFIG1) {
|
||||
r0.set_bits = INTF_CONFIG1_BIT::RTC_MODE;
|
||||
}
|
||||
}
|
||||
|
||||
for (auto &r1 : _register_bank1_cfg) {
|
||||
if (r1.reg == Register::BANK_1::INTF_CONFIG5) {
|
||||
r1.set_bits = PIN9_FUNCTION_BIT::CLKIN;
|
||||
r1.clear_bits = PIN9_FUNCTION_BIT::FSYNC_PIN9;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void IIM42652::SelectRegisterBank(enum REG_BANK_SEL_BIT bank, bool force)
|
||||
{
|
||||
if (bank != _last_register_bank || force) {
|
||||
@@ -471,7 +508,7 @@ uint16_t IIM42652::FIFOReadCount()
|
||||
// read FIFO count
|
||||
uint8_t fifo_count_buf[3] {};
|
||||
fifo_count_buf[0] = static_cast<uint8_t>(Register::BANK_0::FIFO_COUNTH) | DIR_READ;
|
||||
SelectRegisterBank(REG_BANK_SEL_BIT::USER_BANK_0);
|
||||
SelectRegisterBank(REG_BANK_SEL_BIT::BANK_SEL_0);
|
||||
|
||||
if (transfer(fifo_count_buf, fifo_count_buf, sizeof(fifo_count_buf)) != PX4_OK) {
|
||||
perf_count(_bad_transfer_perf);
|
||||
@@ -485,7 +522,7 @@ bool IIM42652::FIFORead(const hrt_abstime ×tamp_sample, uint8_t samples)
|
||||
{
|
||||
FIFOTransferBuffer buffer{};
|
||||
const size_t transfer_size = math::min(samples * sizeof(FIFO::DATA) + 4, FIFO::SIZE);
|
||||
SelectRegisterBank(REG_BANK_SEL_BIT::USER_BANK_0);
|
||||
SelectRegisterBank(REG_BANK_SEL_BIT::BANK_SEL_0);
|
||||
|
||||
if (transfer((uint8_t *)&buffer, (uint8_t *)&buffer, transfer_size) != PX4_OK) {
|
||||
perf_count(_bad_transfer_perf);
|
||||
@@ -538,6 +575,10 @@ bool IIM42652::FIFORead(const hrt_abstime ×tamp_sample, uint8_t samples)
|
||||
// Packet does not contain a new and valid extended 20-bit data
|
||||
valid = false;
|
||||
|
||||
} else if ((FIFO_HEADER & FIFO::FIFO_HEADER_BIT::HEADER_TIMESTAMP_FSYNC) != Bit3) {
|
||||
// Packet does not contain ODR timestamp
|
||||
valid = false;
|
||||
|
||||
} else if (FIFO_HEADER & FIFO::FIFO_HEADER_BIT::HEADER_ODR_ACCEL) {
|
||||
// accel ODR changed
|
||||
valid = false;
|
||||
@@ -600,13 +641,22 @@ void IIM42652::ProcessAccel(const hrt_abstime ×tamp_sample, const FIFO::DAT
|
||||
sensor_accel_fifo_s accel{};
|
||||
accel.timestamp_sample = timestamp_sample;
|
||||
accel.samples = 0;
|
||||
accel.dt = FIFO_SAMPLE_DT;
|
||||
|
||||
// 18-bits of accelerometer data
|
||||
bool scale_20bit = false;
|
||||
|
||||
// first pass
|
||||
for (int i = 0; i < samples; i++) {
|
||||
|
||||
uint16_t timestamp_fifo = combine_uint(fifo[i].TimeStamp_h, fifo[i].TimeStamp_l);
|
||||
|
||||
if (_enable_clock_input) {
|
||||
accel.dt = (float)timestamp_fifo * ((1.f / _input_clock_freq) * 1e6f);
|
||||
|
||||
} else {
|
||||
accel.dt = (float)timestamp_fifo * FIFO_TIMESTAMP_SCALING;
|
||||
}
|
||||
|
||||
// 20 bit hires mode
|
||||
// Sign extension + Accel [19:12] + Accel [11:4] + Accel [3:2] (20 bit extension byte)
|
||||
// Accel data is 18 bit ()
|
||||
@@ -687,13 +737,22 @@ void IIM42652::ProcessGyro(const hrt_abstime ×tamp_sample, const FIFO::DATA
|
||||
sensor_gyro_fifo_s gyro{};
|
||||
gyro.timestamp_sample = timestamp_sample;
|
||||
gyro.samples = 0;
|
||||
gyro.dt = FIFO_SAMPLE_DT;
|
||||
|
||||
// 20-bits of gyroscope data
|
||||
bool scale_20bit = false;
|
||||
|
||||
// first pass
|
||||
for (int i = 0; i < samples; i++) {
|
||||
|
||||
uint16_t timestamp_fifo = combine_uint(fifo[i].TimeStamp_h, fifo[i].TimeStamp_l);
|
||||
|
||||
if (_enable_clock_input) {
|
||||
gyro.dt = (float)timestamp_fifo * ((1.f / _input_clock_freq) * 1e6f);
|
||||
|
||||
} else {
|
||||
gyro.dt = (float)timestamp_fifo * FIFO_TIMESTAMP_SCALING;
|
||||
}
|
||||
|
||||
// 20 bit hires mode
|
||||
// Gyro [19:12] + Gyro [11:4] + Gyro [3:0] (bottom 4 bits of 20 bit extension byte)
|
||||
int32_t gyro_x = reassemble_20bit(fifo[i].GYRO_DATA_X1, fifo[i].GYRO_DATA_X0, fifo[i].Ext_Accel_X_Gyro_X & 0x0F);
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/****************************************************************************
|
||||
*
|
||||
* Copyright (c) 2022 PX4 Development Team. All rights reserved.
|
||||
* Copyright (c) 2023 PX4 Development Team. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -74,6 +74,8 @@ private:
|
||||
static constexpr float GYRO_RATE{1e6f / FIFO_SAMPLE_DT};
|
||||
static constexpr float ACCEL_RATE{1e6f / FIFO_SAMPLE_DT};
|
||||
|
||||
static constexpr float FIFO_TIMESTAMP_SCALING{16.f *(32.f / 30.f)}; // Used when not using clock input
|
||||
|
||||
// maximum FIFO samples per transfer is limited to the size of sensor_accel_fifo/sensor_gyro_fifo
|
||||
static constexpr int32_t FIFO_MAX_SAMPLES{math::min(FIFO::SIZE / sizeof(FIFO::DATA), sizeof(sensor_gyro_fifo_s::x) / sizeof(sensor_gyro_fifo_s::x[0]), sizeof(sensor_accel_fifo_s::x) / sizeof(sensor_accel_fifo_s::x[0]) * (int)(GYRO_RATE / ACCEL_RATE))};
|
||||
|
||||
@@ -113,11 +115,12 @@ private:
|
||||
bool Configure();
|
||||
void ConfigureSampleRate(int sample_rate);
|
||||
void ConfigureFIFOWatermark(uint8_t samples);
|
||||
void ConfigureCLKIN();
|
||||
|
||||
void SelectRegisterBank(enum REG_BANK_SEL_BIT bank, bool force = false);
|
||||
void SelectRegisterBank(Register::BANK_0 reg) { SelectRegisterBank(REG_BANK_SEL_BIT::USER_BANK_0); }
|
||||
void SelectRegisterBank(Register::BANK_1 reg) { SelectRegisterBank(REG_BANK_SEL_BIT::USER_BANK_1); }
|
||||
void SelectRegisterBank(Register::BANK_2 reg) { SelectRegisterBank(REG_BANK_SEL_BIT::USER_BANK_2); }
|
||||
void SelectRegisterBank(Register::BANK_0 reg) { SelectRegisterBank(REG_BANK_SEL_BIT::BANK_SEL_0); }
|
||||
void SelectRegisterBank(Register::BANK_1 reg) { SelectRegisterBank(REG_BANK_SEL_BIT::BANK_SEL_1); }
|
||||
void SelectRegisterBank(Register::BANK_2 reg) { SelectRegisterBank(REG_BANK_SEL_BIT::BANK_SEL_2); }
|
||||
|
||||
static int DataReadyInterruptCallback(int irq, void *context, void *arg);
|
||||
void DataReady();
|
||||
@@ -156,7 +159,10 @@ private:
|
||||
hrt_abstime _temperature_update_timestamp{0};
|
||||
int _failure_count{0};
|
||||
|
||||
enum REG_BANK_SEL_BIT _last_register_bank {REG_BANK_SEL_BIT::USER_BANK_0};
|
||||
bool _enable_clock_input{false};
|
||||
float _input_clock_freq{0.f};
|
||||
|
||||
enum REG_BANK_SEL_BIT _last_register_bank {REG_BANK_SEL_BIT::BANK_SEL_0};
|
||||
|
||||
px4::atomic<hrt_abstime> _drdy_timestamp_sample{0};
|
||||
bool _data_ready_interrupt_enabled{false};
|
||||
@@ -165,6 +171,7 @@ private:
|
||||
RESET,
|
||||
WAIT_FOR_RESET,
|
||||
CONFIGURE,
|
||||
FIFO_RESET,
|
||||
FIFO_READ,
|
||||
} _state{STATE::RESET};
|
||||
|
||||
@@ -172,29 +179,33 @@ private:
|
||||
int32_t _fifo_gyro_samples{static_cast<int32_t>(_fifo_empty_interval_us / (1000000 / GYRO_RATE))};
|
||||
|
||||
uint8_t _checked_register_bank0{0};
|
||||
static constexpr uint8_t size_register_bank0_cfg{13};
|
||||
static constexpr uint8_t size_register_bank0_cfg{16};
|
||||
register_bank0_config_t _register_bank0_cfg[size_register_bank0_cfg] {
|
||||
// Register | Set bits, Clear bits
|
||||
{ Register::BANK_0::INT_CONFIG, INT_CONFIG_BIT::INT1_MODE | INT_CONFIG_BIT::INT1_DRIVE_CIRCUIT, INT_CONFIG_BIT::INT1_POLARITY },
|
||||
{ Register::BANK_0::FIFO_CONFIG, FIFO_CONFIG_BIT::FIFO_MODE_STOP_ON_FULL, 0 },
|
||||
{ Register::BANK_0::INTF_CONFIG1, 0, 0}, // RTC_MODE[2] set at runtime
|
||||
{ Register::BANK_0::PWR_MGMT0, PWR_MGMT0_BIT::GYRO_MODE_LOW_NOISE | PWR_MGMT0_BIT::ACCEL_MODE_LOW_NOISE, 0 },
|
||||
{ Register::BANK_0::GYRO_CONFIG0, GYRO_CONFIG0_BIT::GYRO_FS_SEL_2000_DPS | GYRO_CONFIG0_BIT::GYRO_ODR_8KHZ_SET, GYRO_CONFIG0_BIT::GYRO_ODR_8KHZ_CLEAR },
|
||||
{ Register::BANK_0::ACCEL_CONFIG0, ACCEL_CONFIG0_BIT::ACCEL_FS_SEL_16G | ACCEL_CONFIG0_BIT::ACCEL_ODR_8KHZ_SET, ACCEL_CONFIG0_BIT::ACCEL_ODR_8KHZ_CLEAR },
|
||||
{ Register::BANK_0::GYRO_CONFIG1, 0, GYRO_CONFIG1_BIT::GYRO_UI_FILT_ORD },
|
||||
{ Register::BANK_0::GYRO_ACCEL_CONFIG0, 0, GYRO_ACCEL_CONFIG0_BIT::ACCEL_UI_FILT_BW | GYRO_ACCEL_CONFIG0_BIT::GYRO_UI_FILT_BW },
|
||||
{ Register::BANK_0::ACCEL_CONFIG1, 0, ACCEL_CONFIG1_BIT::ACCEL_UI_FILT_ORD },
|
||||
{ Register::BANK_0::FIFO_CONFIG1, FIFO_CONFIG1_BIT::FIFO_WM_GT_TH | FIFO_CONFIG1_BIT::FIFO_HIRES_EN | FIFO_CONFIG1_BIT::FIFO_TEMP_EN | FIFO_CONFIG1_BIT::FIFO_GYRO_EN | FIFO_CONFIG1_BIT::FIFO_ACCEL_EN, 0 },
|
||||
{ Register::BANK_0::TMST_CONFIG, TMST_CONFIG_BIT::TMST_EN | TMST_CONFIG_BIT::TMST_DELTA_EN | TMST_CONFIG_BIT::TMST_TO_REGS_EN | TMST_CONFIG_BIT::TMST_RES, TMST_CONFIG_BIT::TMST_FSYNC_EN },
|
||||
{ Register::BANK_0::FIFO_CONFIG1, FIFO_CONFIG1_BIT::FIFO_WM_GT_TH | FIFO_CONFIG1_BIT::FIFO_HIRES_EN | FIFO_CONFIG1_BIT::FIFO_TEMP_EN | FIFO_CONFIG1_BIT::FIFO_GYRO_EN | FIFO_CONFIG1_BIT::FIFO_ACCEL_EN, FIFO_CONFIG1_BIT::FIFO_TMST_FSYNC_EN },
|
||||
{ Register::BANK_0::FIFO_CONFIG2, 0, 0 }, // FIFO_WM[7:0] set at runtime
|
||||
{ Register::BANK_0::FIFO_CONFIG3, 0, 0 }, // FIFO_WM[11:8] set at runtime
|
||||
{ Register::BANK_0::INT_CONFIG0, INT_CONFIG0_BIT::CLEAR_ON_FIFO_READ, 0 },
|
||||
{ Register::BANK_0::INT_CONFIG1, 0, INT_CONFIG1_BIT::INT_ASYNC_RESET },
|
||||
{ Register::BANK_0::INT_SOURCE0, INT_SOURCE0_BIT::FIFO_THS_INT1_EN, 0 },
|
||||
};
|
||||
|
||||
uint8_t _checked_register_bank1{0};
|
||||
static constexpr uint8_t size_register_bank1_cfg{1};
|
||||
static constexpr uint8_t size_register_bank1_cfg{2};
|
||||
register_bank1_config_t _register_bank1_cfg[size_register_bank1_cfg] {
|
||||
// Register | Set bits, Clear bits
|
||||
{ Register::BANK_1::GYRO_CONFIG_STATIC2, GYRO_CONFIG_STATIC2_BIT::GYRO_AAF_DIS | GYRO_CONFIG_STATIC2_BIT::GYRO_NF_DIS, 0 },
|
||||
{ Register::BANK_1::INTF_CONFIG5, 0, 0 },
|
||||
};
|
||||
|
||||
uint8_t _checked_register_bank2{0};
|
||||
|
||||
@@ -90,12 +90,14 @@ enum class BANK_0 : uint8_t {
|
||||
GYRO_CONFIG1 = 0x51,
|
||||
GYRO_ACCEL_CONFIG0 = 0x52,
|
||||
ACCEL_CONFIG1 = 0x53,
|
||||
TMST_CONFIG = 0x54,
|
||||
|
||||
FIFO_CONFIG1 = 0x5F,
|
||||
FIFO_CONFIG2 = 0x60,
|
||||
FIFO_CONFIG3 = 0x61,
|
||||
|
||||
INT_CONFIG0 = 0x63,
|
||||
INT_CONFIG1 = 0x64,
|
||||
|
||||
INT_SOURCE0 = 0x65,
|
||||
|
||||
@@ -107,7 +109,6 @@ enum class BANK_0 : uint8_t {
|
||||
|
||||
enum class BANK_1 : uint8_t {
|
||||
GYRO_CONFIG_STATIC2 = 0x0B,
|
||||
|
||||
INTF_CONFIG5 = 0x7B,
|
||||
};
|
||||
|
||||
@@ -151,6 +152,12 @@ enum SIGNAL_PATH_RESET_BIT : uint8_t {
|
||||
FIFO_FLUSH = Bit1,
|
||||
};
|
||||
|
||||
enum INTF_CONFIG1_BIT : uint8_t {
|
||||
RTC_MODE = Bit2, // 0: No input RTC clock is required, 1: RTC clock input is required
|
||||
CLKSEL = Bit0,
|
||||
CLKSEL_CLEAR = Bit1,
|
||||
};
|
||||
|
||||
// PWR_MGMT0
|
||||
enum PWR_MGMT0_BIT : uint8_t {
|
||||
GYRO_MODE_LOW_NOISE = Bit3 | Bit2, // 11: Places gyroscope in Low Noise (LN) Mode
|
||||
@@ -225,11 +232,21 @@ enum ACCEL_CONFIG1_BIT : uint8_t {
|
||||
ACCEL_UI_FILT_ORD = Bit4 | Bit3, // 00: 1st Order
|
||||
};
|
||||
|
||||
// TMST_CONFIG
|
||||
enum TMST_CONFIG_BIT : uint8_t {
|
||||
TMST_TO_REGS_EN = Bit4, // 1: TMST_VALUE[19:0] read returns timestamp value
|
||||
TMST_RES = Bit3, // 0: 1us resolution, 1: 16us resolution
|
||||
TMST_DELTA_EN = Bit2, // 1: Time Stamp delta enable
|
||||
TMST_FSYNC_EN = Bit1, // 1: The contents of the Timestamp feature of FSYNC is enabled
|
||||
TMST_EN = Bit0, // 1: Time Stamp register enable (default)
|
||||
};
|
||||
|
||||
// FIFO_CONFIG1
|
||||
enum FIFO_CONFIG1_BIT : uint8_t {
|
||||
FIFO_RESUME_PARTIAL_RD = Bit6,
|
||||
FIFO_WM_GT_TH = Bit5,
|
||||
FIFO_HIRES_EN = Bit4,
|
||||
FIFO_TMST_FSYNC_EN = Bit3,
|
||||
FIFO_TEMP_EN = Bit2,
|
||||
FIFO_GYRO_EN = Bit1,
|
||||
FIFO_ACCEL_EN = Bit0,
|
||||
@@ -241,6 +258,11 @@ enum INT_CONFIG0_BIT : uint8_t {
|
||||
CLEAR_ON_FIFO_READ = Bit3,
|
||||
};
|
||||
|
||||
// INT_CONFIG1
|
||||
enum INT_CONFIG1_BIT : uint8_t {
|
||||
INT_ASYNC_RESET = Bit4,
|
||||
};
|
||||
|
||||
// INT_SOURCE0
|
||||
enum INT_SOURCE0_BIT : uint8_t {
|
||||
UI_FSYNC_INT1_EN = Bit6,
|
||||
@@ -254,10 +276,12 @@ enum INT_SOURCE0_BIT : uint8_t {
|
||||
|
||||
// REG_BANK_SEL
|
||||
enum REG_BANK_SEL_BIT : uint8_t {
|
||||
USER_BANK_0 = 0, // 0: Select USER BANK 0.
|
||||
USER_BANK_1 = Bit4, // 1: Select USER BANK 1.
|
||||
USER_BANK_2 = Bit5, // 2: Select USER BANK 2.
|
||||
USER_BANK_3 = Bit5 | Bit4, // 3: Select USER BANK 3.
|
||||
// 2:0 BANK_SEL
|
||||
BANK_SEL_0 = 0, // 000: Bank 0 (default)
|
||||
BANK_SEL_1 = Bit0, // 001: Bank 1
|
||||
BANK_SEL_2 = Bit1, // 010: Bank 2
|
||||
BANK_SEL_3 = Bit1 | Bit0, // 011: Bank 3
|
||||
BANK_SEL_4 = Bit2, // 100: Bank 4
|
||||
};
|
||||
|
||||
|
||||
@@ -269,6 +293,11 @@ enum GYRO_CONFIG_STATIC2_BIT : uint8_t {
|
||||
GYRO_NF_DIS = Bit0,
|
||||
};
|
||||
|
||||
// PIN9_FUNCTION
|
||||
enum PIN9_FUNCTION_BIT : uint8_t {
|
||||
FSYNC_PIN9 = Bit1,
|
||||
CLKIN = Bit2,
|
||||
};
|
||||
|
||||
//---------------- BANK2 Register bits
|
||||
|
||||
@@ -313,7 +342,7 @@ enum FIFO_HEADER_BIT : uint8_t {
|
||||
HEADER_ACCEL = Bit6, // 1: Packet is sized so that accel data have location in the packet, FIFO_ACCEL_EN must be 1
|
||||
HEADER_GYRO = Bit5, // 1: Packet is sized so that gyro data have location in the packet, FIFO_GYRO_EN must be1
|
||||
HEADER_20 = Bit4, // 1: Packet has a new and valid sample of extended 20-bit data for gyro and/or accel
|
||||
HEADER_TIMESTAMP_FSYNC = Bit3 | Bit2,
|
||||
HEADER_TIMESTAMP_FSYNC = Bit3 | Bit2, // 10: Packet contains ODR Timestamp
|
||||
HEADER_ODR_ACCEL = Bit1, // 1: The ODR for accel is different for this accel data packet compared to the previous accel packet
|
||||
HEADER_ODR_GYRO = Bit0, // 1: The ODR for gyro is different for this gyro data packet compared to the previous gyro packet
|
||||
};
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/****************************************************************************
|
||||
*
|
||||
* Copyright (c) 2022 PX4 Development Team. All rights reserved.
|
||||
* Copyright (c) 2023 PX4 Development Team. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -43,6 +43,7 @@ void IIM42652::print_usage()
|
||||
PRINT_MODULE_USAGE_COMMAND("start");
|
||||
PRINT_MODULE_USAGE_PARAMS_I2C_SPI_DRIVER(false, true);
|
||||
PRINT_MODULE_USAGE_PARAM_INT('R', 0, 0, 35, "Rotation", true);
|
||||
PRINT_MODULE_USAGE_PARAM_INT('C', 0, 0, 35000, "Input clock frequency (Hz)", true);
|
||||
PRINT_MODULE_USAGE_DEFAULT_COMMANDS();
|
||||
}
|
||||
|
||||
@@ -53,8 +54,12 @@ extern "C" int iim42652_main(int argc, char *argv[])
|
||||
BusCLIArguments cli{false, true};
|
||||
cli.default_spi_frequency = SPI_SPEED;
|
||||
|
||||
while ((ch = cli.getOpt(argc, argv, "R:")) != EOF) {
|
||||
while ((ch = cli.getOpt(argc, argv, "C:R:")) != EOF) {
|
||||
switch (ch) {
|
||||
case 'C':
|
||||
cli.custom1 = atoi(cli.optArg());
|
||||
break;
|
||||
|
||||
case 'R':
|
||||
cli.rotation = (enum Rotation)atoi(cli.optArg());
|
||||
break;
|
||||
|
||||
Reference in New Issue
Block a user