mirror of
https://gitee.com/mirrors_PX4/PX4-Autopilot.git
synced 2026-10-03 16:58:54 +08:00
Enable ARKV6X SPIX SYNC, enable icm426889 and iim42652 CLKIN
This commit is contained in:
alexklimaj
@@ -47,14 +47,14 @@ then
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fi
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fi
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# Internal SPI bus IIM42652
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iim42652 -R 3 -s -b 1 start
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# Internal SPI bus IIM42652 with SPIX measured frequency of 32.051kHz
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iim42652 -R 3 -s -b 1 -C 32051 start
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# Internal SPI bus ICM42688p
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icm42688p -R 9 -s -b 2 start
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# Internal SPI bus ICM42688p with SPIX measured frequency of 32.051kHz
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icm42688p -R 9 -s -b 2 -C 32051 start
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# Internal SPI bus ICM42688p
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icm42688p -R 6 -s -b 3 start
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# Internal SPI bus ICM42688p with SPIX measured frequency of 32.051kHz
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icm42688p -R 6 -s -b 3 -C 32051 start
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# Internal magnetometer on I2C
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bmm150 -I start
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@@ -31,14 +31,19 @@
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#
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############################################################################
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if("${PX4_BOARD_LABEL}" STREQUAL "bootloader")
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add_compile_definitions(BOOTLOADER)
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add_library(drivers_board
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bootloader_main.c
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init.c
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usb.c
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timer_config.cpp
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)
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target_link_libraries(drivers_board
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PRIVATE
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nuttx_arch # sdio
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nuttx_drivers # sdio
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px4_layer #gpio
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arch_io_pins # iotimer
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bootloader
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)
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target_include_directories(drivers_board PRIVATE ${PX4_SOURCE_DIR}/platforms/nuttx/src/bootloader/common)
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@@ -53,6 +58,8 @@ else()
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manifest.c
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sdio.c
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spi.cpp
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spix_sync.c
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spix_sync.h
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timer_config.cpp
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usb.c
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)
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@@ -125,7 +125,9 @@
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/* SPI */
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#define SPI6_nRESET_EXTERNAL1 /* PF10 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTF|GPIO_PIN10)
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#define GPIO_SYNC /* PE9 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_100MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN9)
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#define GPIO_SYNC /* PE9 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN9)
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#define GPIO_SYNC_TIMER /* PE9 */ (GPIO_ALT|GPIO_AF1|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_PULLDOWN|GPIO_PORTE|GPIO_PIN9)
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/* I2C busses */
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@@ -251,7 +253,8 @@
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/* PWM
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*/
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#define DIRECT_PWM_OUTPUT_CHANNELS 9
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#define DIRECT_PWM_OUTPUT_CHANNELS 8
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#define BOARD_PWM_FREQ 1024000
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/* Power supply control and monitoring GPIOs */
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@@ -458,7 +461,6 @@
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GPIO_VDD_3V3_SPEKTRUM_POWER_EN, \
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GPIO_VDD_3V3_SD_CARD_EN, \
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GPIO_PD15, \
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GPIO_SYNC, \
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SPI6_nRESET_EXTERNAL1, \
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GPIO_ETH_POWER_EN, \
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GPIO_NFC_GPIO, \
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@@ -474,7 +476,8 @@
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#define PX4_I2C_BUS_MTD 4,5
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#define BOARD_NUM_IO_TIMERS 5
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#define BOARD_NUM_IO_TIMERS 3
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#define BOARD_SPIX_SYNC_FREQ 32000
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__BEGIN_DECLS
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@@ -46,6 +46,7 @@
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****************************************************************************/
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#include "board_config.h"
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#include "spix_sync.h"
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#include <stdbool.h>
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#include <stdio.h>
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@@ -279,5 +280,9 @@ __EXPORT int board_app_initialize(uintptr_t arg)
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#endif /* CONFIG_MMCSD */
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/* Configure the SPIX_SYNC output */
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spix_sync_servo_init(BOARD_SPIX_SYNC_FREQ);
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spix_sync_servo_set(0, 150);
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return OK;
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}
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@@ -0,0 +1,311 @@
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/****************************************************************************
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*
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* Copyright (C) 2023 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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||||
* are met:
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||||
*
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* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
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||||
* 2. Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
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||||
* distribution.
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* 3. Neither the name Airmind nor the names of its contributors may be
|
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* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
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*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/**
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* @file spix_sync.c
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*
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*
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*/
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#include <px4_platform_common/px4_config.h>
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#include <board_config.h>
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#include <sys/types.h>
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#include <stdint.h>
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#include <string.h>
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#include <stdlib.h>
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#include <stdbool.h>
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#include <fcntl.h>
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#include <unistd.h>
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#include <stdio.h>
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#include <ctype.h>
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#include <perf/perf_counter.h>
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#include <systemlib/err.h>
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#include <systemlib/px4_macros.h>
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#include <px4_arch/io_timer.h>
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#include "spix_sync.h"
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#define REG(_tmr, _reg) (*(volatile uint32_t *)(spix_sync_timers[_tmr].base + _reg))
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#define rCR1(_tmr) REG(_tmr, STM32_GTIM_CR1_OFFSET)
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#define rCR2(_tmr) REG(_tmr, STM32_GTIM_CR2_OFFSET)
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#define rSMCR(_tmr) REG(_tmr, STM32_GTIM_SMCR_OFFSET)
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#define rDIER(_tmr) REG(_tmr, STM32_GTIM_DIER_OFFSET)
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#define rSR(_tmr) REG(_tmr, STM32_GTIM_SR_OFFSET)
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#define rEGR(_tmr) REG(_tmr, STM32_GTIM_EGR_OFFSET)
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#define rCCMR1(_tmr) REG(_tmr, STM32_GTIM_CCMR1_OFFSET)
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#define rCCMR2(_tmr) REG(_tmr, STM32_GTIM_CCMR2_OFFSET)
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#define rCCER(_tmr) REG(_tmr, STM32_GTIM_CCER_OFFSET)
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#define rCNT(_tmr) REG(_tmr, STM32_GTIM_CNT_OFFSET)
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#define rPSC(_tmr) REG(_tmr, STM32_GTIM_PSC_OFFSET)
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#define rARR(_tmr) REG(_tmr, STM32_GTIM_ARR_OFFSET)
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#define rCCR1(_tmr) REG(_tmr, STM32_GTIM_CCR1_OFFSET)
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#define rCCR2(_tmr) REG(_tmr, STM32_GTIM_CCR2_OFFSET)
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#define rCCR3(_tmr) REG(_tmr, STM32_GTIM_CCR3_OFFSET)
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#define rCCR4(_tmr) REG(_tmr, STM32_GTIM_CCR4_OFFSET)
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#define rDCR(_tmr) REG(_tmr, STM32_GTIM_DCR_OFFSET)
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#define rDMAR(_tmr) REG(_tmr, STM32_GTIM_DMAR_OFFSET)
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#define rBDTR(_tmr) REG(_tmr, STM32_ATIM_BDTR_OFFSET)
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#if !defined(BOARD_PWM_FREQ)
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#define BOARD_PWM_FREQ 1000000
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#endif
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unsigned
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spix_sync_timer_get_period(unsigned timer)
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{
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return (rARR(timer));
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}
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static void spix_sync_timer_init_timer(unsigned timer, unsigned rate)
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{
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if (spix_sync_timers[timer].base) {
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irqstate_t flags = px4_enter_critical_section();
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/* enable the timer clock before we try to talk to it */
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modifyreg32(spix_sync_timers[timer].clock_register, 0, spix_sync_timers[timer].clock_bit);
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/* disable and configure the timer */
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rCR1(timer) = 0;
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rCR2(timer) = 0;
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rSMCR(timer) = 0;
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rDIER(timer) = 0;
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rCCER(timer) = 0;
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rCCMR1(timer) = 0;
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rCCMR2(timer) = 0;
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rCCR1(timer) = 0;
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rCCR2(timer) = 0;
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rCCR3(timer) = 0;
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rCCR4(timer) = 0;
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rCCER(timer) = 0;
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rDCR(timer) = 0;
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if ((spix_sync_timers[timer].base == STM32_TIM1_BASE) || (spix_sync_timers[timer].base == STM32_TIM8_BASE)) {
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/* master output enable = on */
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rBDTR(timer) = ATIM_BDTR_MOE;
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}
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/* If the timer clock source provided as clock_freq is the STM32_APBx_TIMx_CLKIN
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* then configure the timer to free-run at 1MHz.
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* Otherwise, other frequencies are attainable by adjusting .clock_freq accordingly.
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*/
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rPSC(timer) = (spix_sync_timers[timer].clock_freq / BOARD_PWM_FREQ) - 1;
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/* configure the timer to update at the desired rate */
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rARR(timer) = (BOARD_PWM_FREQ / rate) - 1;
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/* generate an update event; reloads the counter and all registers */
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rEGR(timer) = GTIM_EGR_UG;
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px4_leave_critical_section(flags);
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}
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}
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void spix_sync_channel_init(unsigned channel)
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{
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/* Only initialize used channels */
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if (spix_sync_channels[channel].timer_channel) {
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unsigned timer = spix_sync_channels[channel].timer_index;
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/* configure the GPIO first */
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px4_arch_configgpio(spix_sync_channels[channel].gpio_out);
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uint16_t polarity = spix_sync_channels[channel].masks;
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/* configure the channel */
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switch (spix_sync_channels[channel].timer_channel) {
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case 1:
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rCCMR1(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) | GTIM_CCMR1_OC1PE;
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rCCER(timer) |= polarity | GTIM_CCER_CC1E;
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break;
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case 2:
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rCCMR1(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC2M_SHIFT) | GTIM_CCMR1_OC2PE;
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rCCER(timer) |= polarity | GTIM_CCER_CC2E;
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break;
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case 3:
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rCCMR2(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR2_OC3M_SHIFT) | GTIM_CCMR2_OC3PE;
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rCCER(timer) |= polarity | GTIM_CCER_CC3E;
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break;
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case 4:
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rCCMR2(timer) |= (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR2_OC4M_SHIFT) | GTIM_CCMR2_OC4PE;
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rCCER(timer) |= polarity | GTIM_CCER_CC4E;
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break;
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}
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}
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}
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int
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spix_sync_servo_set(unsigned channel, uint8_t cvalue)
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{
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if (channel >= arraySize(spix_sync_channels)) {
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return -1;
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}
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unsigned timer = spix_sync_channels[channel].timer_index;
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/* test timer for validity */
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if ((spix_sync_timers[timer].base == 0) ||
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(spix_sync_channels[channel].gpio_out == 0)) {
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return -1;
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}
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unsigned period = spix_sync_timer_get_period(timer);
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unsigned value = (unsigned)cvalue * period / 255;
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/* configure the channel */
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if (value > 0) {
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value--;
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}
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switch (spix_sync_channels[channel].timer_channel) {
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case 1:
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rCCR1(timer) = value;
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break;
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case 2:
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rCCR2(timer) = value;
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break;
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case 3:
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rCCR3(timer) = value;
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break;
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case 4:
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rCCR4(timer) = value;
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break;
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default:
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return -1;
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}
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return 0;
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}
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unsigned spix_sync_servo_get(unsigned channel)
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{
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if (channel >= 3) {
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return 0;
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}
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unsigned timer = spix_sync_channels[channel].timer_index;
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uint16_t value = 0;
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/* test timer for validity */
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if ((spix_sync_timers[timer].base == 0) ||
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(spix_sync_channels[channel].timer_channel == 0)) {
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return 0;
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}
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/* configure the channel */
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switch (spix_sync_channels[channel].timer_channel) {
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case 1:
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value = rCCR1(timer);
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break;
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case 2:
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value = rCCR2(timer);
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break;
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case 3:
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value = rCCR3(timer);
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break;
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case 4:
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value = rCCR4(timer);
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break;
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}
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unsigned period = spix_sync_timer_get_period(timer);
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return ((value + 1) * 255 / period);
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}
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int spix_sync_servo_init(unsigned rate)
|
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{
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/* do basic timer initialisation first */
|
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for (unsigned i = 0; i < arraySize(spix_sync_timers); i++) {
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spix_sync_timer_init_timer(i, rate);
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}
|
||||
|
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/* now init channels */
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for (unsigned i = 0; i < arraySize(spix_sync_channels); i++) {
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spix_sync_channel_init(i);
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}
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||||
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spix_sync_servo_arm(true);
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return OK;
|
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}
|
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|
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void
|
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spix_sync_servo_deinit(void)
|
||||
{
|
||||
/* disable the timers */
|
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spix_sync_servo_arm(false);
|
||||
}
|
||||
void
|
||||
spix_sync_servo_arm(bool armed)
|
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{
|
||||
/* iterate timers and arm/disarm appropriately */
|
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for (unsigned i = 0; i < arraySize(spix_sync_timers); i++) {
|
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if (spix_sync_timers[i].base != 0) {
|
||||
if (armed) {
|
||||
/* force an update to preload all registers */
|
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rEGR(i) = GTIM_EGR_UG;
|
||||
|
||||
/* arm requires the timer be enabled */
|
||||
rCR1(i) |= GTIM_CR1_CEN | GTIM_CR1_ARPE;
|
||||
|
||||
} else {
|
||||
rCR1(i) = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,42 @@
|
||||
/****************************************************************************
|
||||
*
|
||||
* Copyright (C) 2023 PX4 Development Team. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name PX4 nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
__BEGIN_DECLS
|
||||
void spix_sync_channel_init(unsigned channel);
|
||||
int spix_sync_servo_set(unsigned channel, uint8_t value);
|
||||
unsigned spix_sync_servo_get(unsigned channel);
|
||||
int spix_sync_servo_init(unsigned rate);
|
||||
void spix_sync_servo_deinit(void);
|
||||
void spix_sync_servo_arm(bool armed);
|
||||
unsigned spix_sync_timer_get_period(unsigned timer);
|
||||
__END_DECLS
|
||||
@@ -60,8 +60,8 @@ constexpr io_timers_t io_timers[MAX_IO_TIMERS] = {
|
||||
initIOTimer(Timer::Timer5, DMA{DMA::Index1}),
|
||||
initIOTimer(Timer::Timer4, DMA{DMA::Index1}),
|
||||
initIOTimer(Timer::Timer12),
|
||||
initIOTimer(Timer::Timer1),
|
||||
initIOTimer(Timer::Timer2),
|
||||
//initIOTimer(Timer::Timer1),
|
||||
//initIOTimer(Timer::Timer2),
|
||||
};
|
||||
|
||||
constexpr timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
|
||||
@@ -73,8 +73,18 @@ constexpr timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
|
||||
initIOTimerChannel(io_timers, {Timer::Timer4, Timer::Channel3}, {GPIO::PortD, GPIO::Pin14}),
|
||||
initIOTimerChannel(io_timers, {Timer::Timer12, Timer::Channel1}, {GPIO::PortH, GPIO::Pin6}),
|
||||
initIOTimerChannel(io_timers, {Timer::Timer12, Timer::Channel2}, {GPIO::PortH, GPIO::Pin9}),
|
||||
initIOTimerChannelCapture(io_timers, {Timer::Timer1, Timer::Channel2}, {GPIO::PortE, GPIO::Pin11}),
|
||||
//initIOTimerChannel(io_timers, {Timer::Timer1, Timer::Channel2}, {GPIO::PortE, GPIO::Pin11}),
|
||||
//initIOTimerChannel(io_timers, {Timer::Timer1, Timer::Channel1}, {GPIO::PortE, GPIO::Pin9}),
|
||||
};
|
||||
|
||||
constexpr io_timers_channel_mapping_t io_timers_channel_mapping =
|
||||
initIOTimerChannelMapping(io_timers, timer_io_channels);
|
||||
|
||||
|
||||
constexpr io_timers_t spix_sync_timers[MAX_SPIX_SYNC_TIMERS] = {
|
||||
initIOTimer(Timer::Timer1),
|
||||
};
|
||||
|
||||
constexpr timer_io_channels_t spix_sync_channels[MAX_SPIX_SYNC_TIMERS] = {
|
||||
initIOTimerChannel(spix_sync_timers, {Timer::Timer1, Timer::Channel1}, {GPIO::PortE, GPIO::Pin9}),
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user