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px4_fmuv5x:Update to master single wire

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This commit is contained in:
David Sidrane 2019-07-26 15:04:35 -07:00 committed by Daniel Agar
parent 7c1d616187
commit 72c742f53d
4 changed files with 5 additions and 65 deletions
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2
boards/px4/fmu-v5x/nuttx-config/nsh/defconfig
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@ -204,7 +204,9 @@ CONFIG_STM32F7_USART2=y
CONFIG_STM32F7_USART3=y
CONFIG_STM32F7_USART6=y
CONFIG_STM32F7_USART_BREAKS=y
CONFIG_STM32F7_USART_INVERT=y
CONFIG_STM32F7_USART_SINGLEWIRE=y
CONFIG_STM32F7_USART_SWAP=y
CONFIG_STM32F7_WWDG=y
CONFIG_SYSTEM_CDCACM=y
CONFIG_SYSTEM_NSH=y

8
boards/px4/fmu-v5x/src/board_config.h
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@ -512,12 +512,10 @@
#define HRT_PPM_CHANNEL /* T8C1 */ 1 /* use capture/compare channel 1 */
#define GPIO_PPM_IN /* PI5 T8C1 */ GPIO_TIM8_CH1IN_2
#define RC_UXART_BASE STM32_USART6_BASE
/* RC Serial port */
#define RC_SERIAL_PORT "/dev/ttyS5"
#define BOARD_HAS_SINGLE_WIRE 1 /* HW is capable of Single Wire */
#define BOARD_HAS_SINGLE_WIRE_ON_TX 0 /* HW default is wired as Single Wire On RX pin */
#define BOARD_HAS_RX_TX_SWAP 1 /* HW Can swap TX and RX */
#define RC_SERIAL_PORT_IS_SWAPED 1 /* Board wired with RC's TX is on cpu RX */
#define RC_SERIAL_SINGLEWIRE
/* Input Capture Channels. */
#define INPUT_CAP1_TIMER 5

46
boards/px4/fmu-v5x/src/init.c
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@ -56,7 +56,6 @@
#include <nuttx/config.h>
#include <nuttx/board.h>
#include <nuttx/spi/spi.h>
#include <nuttx/i2c/i2c_master.h>
#include <nuttx/sdio.h>
#include <nuttx/mmcsd.h>
#include <nuttx/analog/adc.h>
@ -92,51 +91,6 @@ extern void led_off(int led);
__END_DECLS
/************************************************************************************
* Name: board_rc_input
*
* Description:
* All boards my optionally provide this API to invert the Serial RC input.
* This is needed on SoCs that support the notion RXINV or TXINV as apposed to
* and external XOR controlled by a GPIO
*
************************************************************************************/
__EXPORT void board_rc_input(bool invert_on, uint32_t uxart_base)
{
irqstate_t irqstate = px4_enter_critical_section();
uint32_t cr1 = getreg32(STM32_USART_CR1_OFFSET + uxart_base);
uint32_t cr2 = getreg32(STM32_USART_CR2_OFFSET + uxart_base);
uint32_t regval = cr1;
/* {R|T}XINV bit fields can only be written when the USART is disabled (UE=0). */
regval &= ~USART_CR1_UE;
putreg32(regval, STM32_USART_CR1_OFFSET + uxart_base);
if (invert_on) {
#if defined(BOARD_HAS_RX_TX_SWAP) && RC_SERIAL_PORT_IS_SWAPED == 1
/* This is only ever turned on */
cr2 |= (USART_CR2_RXINV | USART_CR2_TXINV | USART_CR2_SWAP);
#else
cr2 |= (USART_CR2_RXINV | USART_CR2_TXINV);
#endif
} else {
cr2 &= ~(USART_CR2_RXINV | USART_CR2_TXINV);
}
putreg32(cr2, STM32_USART_CR2_OFFSET + uxart_base);
putreg32(cr1, STM32_USART_CR1_OFFSET + uxart_base);
leave_critical_section(irqstate);
}
/************************************************************************************
* Name: board_peripheral_reset
*

14
boards/px4/fmu-v5x/src/manifest.c
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@ -93,20 +93,6 @@ static px4_hw_mft_list_entry_t mft_lists[] = {
};
/************************************************************************************
* Name: board_rc_input
*
* Description:
* All boards my optionally provide this API to invert the Serial RC input.
* This is needed on SoCs that support the notion RXINV or TXINV as opposed to
* and external XOR controlled by a GPIO
*
************************************************************************************/
__EXPORT bool board_supports_single_wire(uint32_t uxart_base)
{
return uxart_base == RC_UXART_BASE;
}
/************************************************************************************
* Name: board_query_manifest
*