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Initial IMXRT1170-EVK support
RT7 Boot from debugger now RT7 Version OCOTP GUID/Rev Fix RT7 I2C & SPI Partly working RT7 Add FRAM support Co-authored-by: David Sidrane <david.sidrane@nscdg.com> nxp_imxrt1170-evk:Finish 1170 iomux versioning nxp_imxrt1170-evk:Use FMUM1170 GPIO for PWM nxp_imxrt1170-evk:Add to CI nxp_imxrt1170-evk:Move to 192.168.0 network nxp_imxrt1170-evk:Use LPADC nxp_imxrt1170-evk:Entry is start nxp_imxrt1170-evk:Correct Manifest nxp_imxrt1170-evk:Correct USB VBUS Detect nxp_imxrt1170-evk:Work twords FMURT1170
This commit is contained in:
Peter van der Perk
committed by
David Sidrane
David Sidrane
co-authored by
David Sidrane
David Sidrane
parent
aa786db9e3
commit
7005e14e8e
@@ -0,0 +1,179 @@
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/****************************************************************************
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*
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* Copyright (C) 2016, 2018-2019 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name PX4 nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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// TODO:Stubbed out for now
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#include <stdint.h>
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#include <chip.h>
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#include "hardware/imxrt_tmr.h"
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#include "hardware/imxrt_flexpwm.h"
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#include "imxrt_gpio.h"
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#include "imxrt_iomuxc.h"
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#include "hardware/imxrt_pinmux.h"
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#include "imxrt_xbar.h"
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#include "imxrt_periphclks.h"
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#include <drivers/drv_pwm_output.h>
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#include <px4_arch/io_timer_hw_description.h>
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#include "board_config.h"
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/****************************************************************************************************
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* Definitions
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****************************************************************************************************/
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/* Register accessors */
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#define _REG(_addr) (*(volatile uint16_t *)(_addr))
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/* QTimer3 register accessors */
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#define REG(_reg) _REG(IMXRT_TMR3_BASE + IMXRT_TMR_OFFSET(IMXRT_TMR_CH0,(_reg)))
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#define rCOMP1 REG(IMXRT_TMR_COMP1_OFFSET)
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#define rCOMP2 REG(IMXRT_TMR_COMP2_OFFSET)
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#define rCAPT REG(IMXRT_TMR_CAPT_OFFSET)
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#define rLOAD REG(IMXRT_TMR_LOAD_OFFSET)
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#define rHOLD REG(IMXRT_TMR_HOLD_OFFSET)
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#define rCNTR REG(IMXRT_TMR_CNTR_OFFSET)
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#define rCTRL REG(IMXRT_TMR_CTRL_OFFSET)
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#define rSCTRL REG(IMXRT_TMR_SCTRL_OFFSET)
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#define rCMPLD1 REG(IMXRT_TMR_CMPLD1_OFFSET)
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#define rCMPLD2 REG(IMXRT_TMR_CMPLD2_OFFSET)
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#define rCSCTRL REG(IMXRT_TMR_CSCTRL_OFFSET)
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#define rFILT REG(IMXRT_TMR_FILT_OFFSET)
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#define rDMA REG(IMXRT_TMR_DMA_OFFSET)
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#define rENBL REG(IMXRT_TMR_ENBL_OFFSET)
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// GPIO_EMC_B1_23 FMU_CH1 FLEXPWM1_PWM0_A
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// GPIO_EMC_B1_25 FMU_CH2 FLEXPWM1_PWM1_A + FLEXIO1_IO25
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// GPIO_EMC_B1_27 FMU_CH3 FLEXPWM1_PWM2_A + FLEXIO1_IO27
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// GPIO_EMC_B1_06 FMU_CH4 FLEXPWM2_PWM0_A + FLEXIO1_IO06
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// GPIO_EMC_B1_08 FMU_CH5 FLEXPWM2_PWM1_A + FLEXIO1_IO08
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// GPIO_EMC_B1_10 FMU_CH6 FLEXPWM2_PWM2_A + FLEXIO1_IO10
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// GPIO_EMC_B1_19 FMU_CH7 FLEXPWM2_PWM3_A + FLEXIO1_IO19
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// GPIO_EMC_B1_29 FMU_CH8 FLEXPWM3_PWM0_A + FLEXIO1_IO29
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// GPIO_EMC_B1_31 FMU_CH9 FLEXPWM3_PWM1_A + FLEXIO1_IO31
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// GPIO_EMC_B1_21 FMU_CH10 FLEXPWM3_PWM3_A + FLEXIO1_IO21
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// GPIO_EMC_B1_00 FMU_CH11 FLEXPWM4_PWM0_A + FLEXIO1_IO00
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// GPIO_EMC_B1_02 FMU_CH12 FLEXPWM4_PWM1_A + FLEXIO1_IO02
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constexpr io_timers_t io_timers[MAX_IO_TIMERS] = {
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initIOPWM(PWM::FlexPWM1, PWM::Submodule0),
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initIOPWM(PWM::FlexPWM1, PWM::Submodule1),
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initIOPWM(PWM::FlexPWM1, PWM::Submodule2),
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initIOPWM(PWM::FlexPWM2, PWM::Submodule0),
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initIOPWM(PWM::FlexPWM2, PWM::Submodule1),
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initIOPWM(PWM::FlexPWM2, PWM::Submodule2),
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initIOPWM(PWM::FlexPWM2, PWM::Submodule3),
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initIOPWM(PWM::FlexPWM3, PWM::Submodule0),
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initIOPWM(PWM::FlexPWM3, PWM::Submodule1),
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initIOPWM(PWM::FlexPWM3, PWM::Submodule3),
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initIOPWM(PWM::FlexPWM4, PWM::Submodule0),
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initIOPWM(PWM::FlexPWM4, PWM::Submodule1),
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};
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constexpr timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
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/* FMU_CH1 */ initIOTimerChannel(io_timers, {PWM::PWM1_PWM_A, PWM::Submodule0}, IOMUX::Pad::GPIO_EMC_B1_23),
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/* FMU_CH2 */ initIOTimerChannel(io_timers, {PWM::PWM1_PWM_A, PWM::Submodule1}, IOMUX::Pad::GPIO_EMC_B1_25),
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/* FMU_CH3 */ initIOTimerChannel(io_timers, {PWM::PWM1_PWM_A, PWM::Submodule2}, IOMUX::Pad::GPIO_EMC_B1_27),
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/* FMU_CH4 */ initIOTimerChannel(io_timers, {PWM::PWM2_PWM_A, PWM::Submodule0}, IOMUX::Pad::GPIO_EMC_B1_06),
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/* FMU_CH5 */ initIOTimerChannel(io_timers, {PWM::PWM2_PWM_A, PWM::Submodule1}, IOMUX::Pad::GPIO_EMC_B1_08),
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/* FMU_CH6 */ initIOTimerChannel(io_timers, {PWM::PWM2_PWM_A, PWM::Submodule2}, IOMUX::Pad::GPIO_EMC_B1_10),
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/* FMU_CH7 */ initIOTimerChannel(io_timers, {PWM::PWM2_PWM_A, PWM::Submodule3}, IOMUX::Pad::GPIO_EMC_B1_19),
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/* FMU_CH8 */ initIOTimerChannel(io_timers, {PWM::PWM3_PWM_A, PWM::Submodule0}, IOMUX::Pad::GPIO_EMC_B1_29),
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/* FMU_CH9 */ initIOTimerChannel(io_timers, {PWM::PWM3_PWM_A, PWM::Submodule1}, IOMUX::Pad::GPIO_EMC_B1_31),
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/* FMU_CH10 */ initIOTimerChannel(io_timers, {PWM::PWM3_PWM_A, PWM::Submodule3}, IOMUX::Pad::GPIO_EMC_B1_21),
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/* FMU_CH11 */ initIOTimerChannel(io_timers, {PWM::PWM4_PWM_A, PWM::Submodule0}, IOMUX::Pad::GPIO_EMC_B1_00),
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/* FMU_CH12 */ initIOTimerChannel(io_timers, {PWM::PWM4_PWM_A, PWM::Submodule1}, IOMUX::Pad::GPIO_EMC_B1_02),
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};
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constexpr io_timers_channel_mapping_t io_timers_channel_mapping =
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initIOTimerChannelMapping(io_timers, timer_io_channels);
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constexpr io_timers_t led_pwm_timers[MAX_LED_TIMERS] = {
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};
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constexpr timer_io_channels_t led_pwm_channels[MAX_TIMER_LED_CHANNELS] = {
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};
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void fmurt107x_timer_initialize(void)
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{
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/* We must configure Qtimer 3 as the IPG divide by to yield 16 Mhz
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* and deliver that clock to the eFlexPWM1,2,34 via XBAR
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*
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* IPG = 144 Mhz
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* 16Mhz = 144 / 9
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* COMP 1 = 5, COMP2 = 4
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*
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* */
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/* Enable Block Clocks for Qtimer and XBAR1 */
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imxrt_clockall_timer3();
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imxrt_clockall_xbar1();
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/* Disable Timer */
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rCTRL = 0;
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rCOMP1 = 5 - 1; // N - 1
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rCOMP2 = 4 - 1;
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rCAPT = 0;
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rLOAD = 0;
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rCNTR = 0;
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rSCTRL = TMR_SCTRL_OEN;
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rCMPLD1 = 0;
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rCMPLD2 = 0;
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rCSCTRL = 0;
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rFILT = 0;
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rDMA = 0;
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/* Count rising edges of primary source,
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* Prescaler is /1
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* Count UP until compare, then re-initialize. a successful compare occurs when the counter reaches a COMP1 value.
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* Toggle OFLAG output using alternating compare registers
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*/
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rCTRL = (TMR_CTRL_CM_MODE1 | TMR_CTRL_PCS_DIV1 | TMR_CTRL_LENGTH | TMR_CTRL_OUTMODE_TOG_ALT);
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/* QTIMER3_TIMER0 -> Flexpwm1,2,34ExtClk */
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imxrt_xbar_connect(IMXRT_XBARA1_OUT_FLEXPWM1_EXT_CLK_SEL_OFFSET, IMXRT_XBARA1_IN_QTIMER3_TMR0_OUT);
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imxrt_xbar_connect(IMXRT_XBARA1_OUT_FLEXPWM2_EXT_CLK_SEL_OFFSET, IMXRT_XBARA1_IN_QTIMER3_TMR0_OUT);
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imxrt_xbar_connect(IMXRT_XBARA1_OUT_FLEXPWM34_EXT_CLK_SEL_OFFSET, IMXRT_XBARA1_IN_QTIMER3_TMR0_OUT);
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}
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