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boards: matek h743-slim clock tree adjust
This commit is contained in:
Daniel Agar
parent
b6607a7b78
commit
7004ce102d
@ -32,12 +32,7 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __NUTTX_CONFIG_MATEKH743SLIM_INCLUDE_BOARD_H
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#define __NUTTX_CONFIG_MATEKH743SLIM_INCLUDE_BOARD_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#pragma once
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#include "board_dma_map.h"
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@ -50,12 +45,8 @@
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#include "stm32_rcc.h"
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#include "stm32_sdmmc.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Clocking *************************************************************************/
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/* The MatekH743-Slim board provides the following clock sources:
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/* The board provides the following clock sources:
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*
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* X1: 8 MHz crystal for HSE
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*
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@ -64,13 +55,11 @@
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* HSI: 64 MHz RC factory-trimmed
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* HSE: 8 MHz crystal for HSE
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*/
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#define STM32_BOARD_XTAL 8000000ul
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 32000
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 32768
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/* Main PLL Configuration.
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*
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@ -93,112 +82,88 @@
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* CPUCLK <= 480 MHz
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*/
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#define STM32_BOARD_USEHSE
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#define STM32_PLLCFG_PLLSRC RCC_PLLCKSELR_PLLSRC_HSE
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/* PLL1, wide 4 - 8 MHz input, enable DIVP, DIVQ, DIVR
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*
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* PLL1_VCO = (8,000,000 / 1) * 120 = 960 MHz
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* PLL1_VCO = (8,000,000 / 2) * 200 = 800 MHz
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*
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* PLL1P = PLL1_VCO/2 = 960 MHz / 2 = 480 MHz
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* PLL1Q = PLL1_VCO/4 = 960 MHz / 4 = 240 MHz
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* PLL1R = PLL1_VCO/8 = 960 MHz / 8 = 120 MHz
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* PLL1P = PLL1_VCO/2 = 800 MHz / 2 = 400 MHz
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* PLL1Q = PLL1_VCO/4 = 800 MHz / 4 = 200 MHz
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* PLL1R = PLL1_VCO/2 = 800 MHz / 2 = 400 MHz
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*/
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#define STM32_PLLCFG_PLL1CFG (RCC_PLLCFGR_PLL1VCOSEL_WIDE | \
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RCC_PLLCFGR_PLL1RGE_4_8_MHZ | \
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RCC_PLLCFGR_DIVP1EN | \
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RCC_PLLCFGR_DIVQ1EN | \
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RCC_PLLCFGR_DIVR1EN)
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#define STM32_PLLCFG_PLL1M RCC_PLLCKSELR_DIVM1(1)
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#define STM32_PLLCFG_PLL1N RCC_PLL1DIVR_N1(120)
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#define STM32_PLLCFG_PLL1CFG (RCC_PLLCFGR_PLL1VCOSEL_WIDE|RCC_PLLCFGR_PLL1RGE_4_8_MHZ|RCC_PLLCFGR_DIVP1EN|RCC_PLLCFGR_DIVQ1EN|RCC_PLLCFGR_DIVR1EN)
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#define STM32_PLLCFG_PLL1M RCC_PLLCKSELR_DIVM1(2)
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#define STM32_PLLCFG_PLL1N RCC_PLL1DIVR_N1(200)
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#define STM32_PLLCFG_PLL1P RCC_PLL1DIVR_P1(2)
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#define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR_Q1(4)
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#define STM32_PLLCFG_PLL1R RCC_PLL1DIVR_R1(8)
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#define STM32_PLLCFG_PLL1R RCC_PLL1DIVR_R1(2)
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#define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 1) * 120)
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#define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 200)
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#define STM32_PLL1P_FREQUENCY (STM32_VCO1_FREQUENCY / 2)
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#define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / 4)
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#define STM32_PLL1R_FREQUENCY (STM32_VCO1_FREQUENCY / 8)
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#define STM32_PLL1R_FREQUENCY (STM32_VCO1_FREQUENCY / 2)
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/* PLL2 */
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#define STM32_PLLCFG_PLL2CFG (RCC_PLLCFGR_PLL2VCOSEL_WIDE | \
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RCC_PLLCFGR_PLL2RGE_4_8_MHZ | \
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RCC_PLLCFGR_DIVP2EN | \
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RCC_PLLCFGR_DIVQ2EN | \
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RCC_PLLCFGR_DIVR2EN)
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#define STM32_PLLCFG_PLL2M RCC_PLLCKSELR_DIVM2(2)
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#define STM32_PLLCFG_PLL2N RCC_PLL2DIVR_N2(48)
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#define STM32_PLLCFG_PLL2CFG (RCC_PLLCFGR_PLL2VCOSEL_WIDE|RCC_PLLCFGR_PLL2RGE_4_8_MHZ|RCC_PLLCFGR_DIVP2EN|RCC_PLLCFGR_DIVQ2EN|RCC_PLLCFGR_DIVR2EN)
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#define STM32_PLLCFG_PLL2M RCC_PLLCKSELR_DIVM2(4)
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#define STM32_PLLCFG_PLL2N RCC_PLL2DIVR_N2(260)
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#define STM32_PLLCFG_PLL2P RCC_PLL2DIVR_P2(2)
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#define STM32_PLLCFG_PLL2Q RCC_PLL2DIVR_Q2(2)
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#define STM32_PLLCFG_PLL2Q RCC_PLL2DIVR_Q2(10)
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#define STM32_PLLCFG_PLL2R RCC_PLL2DIVR_R2(2)
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#define STM32_VCO2_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 48)
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#define STM32_VCO2_FREQUENCY ((STM32_HSE_FREQUENCY / 4) * 260)
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#define STM32_PLL2P_FREQUENCY (STM32_VCO2_FREQUENCY / 2)
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#define STM32_PLL2Q_FREQUENCY (STM32_VCO2_FREQUENCY / 2)
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#define STM32_PLL2Q_FREQUENCY (STM32_VCO2_FREQUENCY / 10)
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#define STM32_PLL2R_FREQUENCY (STM32_VCO2_FREQUENCY / 2)
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/* PLL3 */
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#define STM32_PLLCFG_PLL3CFG (RCC_PLLCFGR_PLL3VCOSEL_WIDE | \
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RCC_PLLCFGR_PLL3RGE_4_8_MHZ | \
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RCC_PLLCFGR_DIVQ3EN)
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#define STM32_PLLCFG_PLL3CFG (RCC_PLLCFGR_PLL3VCOSEL_WIDE|RCC_PLLCFGR_PLL3RGE_4_8_MHZ|RCC_PLLCFGR_DIVP3EN|RCC_PLLCFGR_DIVQ3EN|RCC_PLLCFGR_DIVR3EN)
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#define STM32_PLLCFG_PLL3M RCC_PLLCKSELR_DIVM3(2)
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#define STM32_PLLCFG_PLL3N RCC_PLL3DIVR_N3(48)
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#define STM32_PLLCFG_PLL3N RCC_PLL3DIVR_N3(50)
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#define STM32_PLLCFG_PLL3P RCC_PLL3DIVR_P3(2)
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#define STM32_PLLCFG_PLL3Q RCC_PLL3DIVR_Q3(4)
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#define STM32_PLLCFG_PLL3Q RCC_PLL3DIVR_Q3(2)
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#define STM32_PLLCFG_PLL3R RCC_PLL3DIVR_R3(2)
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#define STM32_VCO3_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 48)
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#define STM32_VCO3_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 50)
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#define STM32_PLL3P_FREQUENCY (STM32_VCO3_FREQUENCY / 2)
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#define STM32_PLL3Q_FREQUENCY (STM32_VCO3_FREQUENCY / 4)
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#define STM32_PLL3Q_FREQUENCY (STM32_VCO3_FREQUENCY / 2)
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#define STM32_PLL3R_FREQUENCY (STM32_VCO3_FREQUENCY / 2)
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/* SYSCLK = PLL1P = 480MHz
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* CPUCLK = SYSCLK / 1 = 480 MHz
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/* SYSCLK = PLL1P = 400MHz
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* CPUCLK = SYSCLK / 1 = 400 MHz
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*/
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#define STM32_RCC_D1CFGR_D1CPRE (RCC_D1CFGR_D1CPRE_SYSCLK)
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#define STM32_SYSCLK_FREQUENCY (STM32_PLL1P_FREQUENCY)
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#define STM32_CPUCLK_FREQUENCY (STM32_SYSCLK_FREQUENCY / 1)
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/* Configure Clock Assignments */
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/* AHB clock (HCLK) is SYSCLK/2 (240 MHz max)
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* HCLK1 = HCLK2 = HCLK3 = HCLK4 = 240
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/* AHB clock (HCLK) is SYSCLK/2 (200 MHz max)
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* HCLK1 = HCLK2 = HCLK3 = HCLK4 = 200
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*/
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#define STM32_RCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_SYSCLKd2 /* HCLK = SYSCLK / 2 */
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#define STM32_ACLK_FREQUENCY (STM32_CPUCLK_FREQUENCY / 2) /* ACLK in D1, HCLK3 in D1 */
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#define STM32_HCLK_FREQUENCY (STM32_CPUCLK_FREQUENCY / 2) /* HCLK in D2, HCLK4 in D3 */
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
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/* APB1 clock (PCLK1) is HCLK/2 (120 MHz) */
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/* APB1 clock (PCLK1) is HCLK/2 (100 MHz) */
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#define STM32_RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* APB2 clock (PCLK2) is HCLK/2 (120 MHz) */
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/* APB2 clock (PCLK2) is HCLK/2 (50 MHz) */
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#define STM32_RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* APB3 clock (PCLK3) is HCLK/2 (120 MHz) */
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/* APB3 clock (PCLK3) is HCLK/2 (50 MHz) */
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#define STM32_RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_HCLKd2 /* PCLK3 = HCLK / 2 */
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#define STM32_PCLK3_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* APB4 clock (PCLK4) is HCLK/4 (120 MHz) */
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/* APB4 clock (PCLK4) is HCLK/4 (50 MHz) */
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#define STM32_RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_HCLKd2 /* PCLK4 = HCLK / 2 */
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#define STM32_PCLK4_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* Timer clock frequencies */
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/* Timers driven from APB1 will be twice PCLK1 */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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@ -210,7 +175,6 @@
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* Timers driven from APB2 will be twice PCLK2 */
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#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY)
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@ -218,69 +182,27 @@
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#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY)
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/* Kernel Clock Configuration
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*
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* Note: look at Table 54 in ST Manual
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* Note: look at Table 54 in ST Manual
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*/
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/* I2C123 clock source */
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#define STM32_RCC_D2CCIP2R_I2C123SRC RCC_D2CCIP2R_I2C123SEL_HSI
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/* I2C4 clock source */
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#define STM32_RCC_D3CCIPR_I2C4SRC RCC_D3CCIPR_I2C4SEL_HSI
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/* SPI123 clock source */
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#define STM32_RCC_D2CCIP1R_SPI123SRC RCC_D2CCIP1R_SPI123SEL_PLL2
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/* SPI45 clock source */
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#define STM32_RCC_D2CCIP1R_SPI45SRC RCC_D2CCIP1R_SPI45SEL_PLL2
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/* SPI6 clock source */
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#define STM32_RCC_D3CCIPR_SPI6SRC RCC_D3CCIPR_SPI6SEL_PLL2
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/* USB 1 and 2 clock source */
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#define STM32_RCC_D2CCIP2R_USBSRC RCC_D2CCIP2R_USBSEL_PLL3
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/* ADC 1 2 3 clock source */
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#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2
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/* FDCAN 1 clock source */
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#define STM32_RCC_D1CCIPR_SDMMCSEL RCC_D1CCIPR_SDMMC_PLL1
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#define STM32_RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_HSE /* FDCAN 1 2 clock source */
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#define STM32_RCC_D2CCIP1R_SPI123SRC RCC_D2CCIP1R_SPI123SEL_PLL2 /* SPI123 clock source */
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#define STM32_RCC_D2CCIP1R_SPI45SRC RCC_D2CCIP1R_SPI45SEL_PLL2 /* SPI45 clock source */
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#define STM32_RCC_D2CCIP2R_I2C123SRC RCC_D2CCIP2R_I2C123SEL_HSI /* I2C123 clock source */
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#define STM32_RCC_D2CCIP2R_USBSRC RCC_D2CCIP2R_USBSEL_PLL3 /* USB 1 and 2 clock source */
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#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 /* ADC 1 2 3 clock source */
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#define STM32_RCC_D3CCIPR_I2C4SRC RCC_D3CCIPR_I2C4SEL_HSI /* I2C4 clock source */
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#define STM32_RCC_D3CCIPR_SPI6SRC RCC_D3CCIPR_SPI6SEL_PLL2 /* SPI6 clock source */
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#define STM32_FDCANCLK STM32_HSE_FREQUENCY
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/* FLASH wait states
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*
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* ------------ ---------- -----------
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* Vcore MAX ACLK WAIT STATES
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* ------------ ---------- -----------
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* 1.15-1.26 V 70 MHz 0
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* (VOS1 level) 140 MHz 1
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* 210 MHz 2
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* 1.05-1.15 V 55 MHz 0
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* (VOS2 level) 110 MHz 1
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* 165 MHz 2
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* 220 MHz 3
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* 0.95-1.05 V 45 MHz 0
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* (VOS3 level) 90 MHz 1
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* 135 MHz 2
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* 180 MHz 3
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* 225 MHz 4
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* ------------ ---------- -----------
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*/
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/* FLASH wait states */
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#define BOARD_FLASH_WAITSTATES 2
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/* SDMMC definitions ********************************************************/
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/* Init 480kHz, freq = PLL1Q/(2*div) div = PLL1Q/(2*freq) */
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/* Init 400kHz, freq = PLL1Q/(2*div) div = PLL1Q/(2*freq) */
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#define STM32_SDMMC_INIT_CLKDIV (300 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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@ -489,5 +411,3 @@
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# define PROBE(n,s)
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# define PROBE_MARK(n)
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#endif
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#endif /*__NUTTX_CONFIG_MATEKH743SLIM_INCLUDE_BOARD_H */
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