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https://gitee.com/mirrors_PX4/PX4-Autopilot.git
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WIP: mRO CANnode m10025
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Daniel Agar
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/************************************************************************************
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* configs/px4fmu/include/board.h
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* include/arch/board/board.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_BOARD_BOARD_H
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#define __ARCH_BOARD_BOARD_H
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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#include <stm32.h>
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/* Clocking *****************************************************************/
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/* HSI - Internal 8 MHz RC Oscillator
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* LSI - 32 KHz RC
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* HSE - 8 MHz from MCO output of ST-LINK
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* LSE - 32.768 kHz
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*/
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#define STM32_BOARD_XTAL 8000000ul /* X1 on board */
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#define STM32_HSEBYP_ENABLE
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#define STM32_HSI_FREQUENCY 8000000ul
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#define STM32_LSI_FREQUENCY 40000 /* Between 30kHz and 60kHz */
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 0
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/* PLL source is HSE/1, PLL multipler is 9: PLL frequency is 8MHz (XTAL) x 9 = 72MHz */
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#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC
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#define STM32_CFGR_PLLXTPRE 0
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#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9
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#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL)
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/* Use the PLL and set the SYSCLK source to be the PLL */
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#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL
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#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
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#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY
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/* AHB clock (HCLK) is SYSCLK (72MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
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/* APB2 clock (PCLK2) is HCLK (72MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
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#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
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#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 1 and 8, 15-17 */
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/* APB2 timers 1 and 8, 15-17 will receive PCLK2. */
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/* Timers driven from APB2 will be PCLK2 */
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#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY)
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/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* APB1 timers 2-7 will be twice PCLK1 */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* USB divider -- Divide PLL clock by 1.5 */
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#define STM32_CFGR_USBPRE 0
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,8 are on APB2, others on APB1
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*/
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#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
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/* Alternate function pin selections ************************************************/
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/* UARTs */
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#define GPIO_USART1_TX GPIO_USART1_TX_1 /* PA9 */
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#define GPIO_USART1_RX GPIO_USART1_RX_1 /* PA10 */
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#define GPIO_USART2_TX GPIO_USART2_TX_2 /* PA2 */
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#define GPIO_USART2_RX GPIO_USART2_RX_2 /* PA3 */
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/* CAN */
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#define GPIO_CAN1_RX GPIO_CAN_RX_2 /* PA11 */
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#define GPIO_CAN1_TX GPIO_CAN_TX_2 /* PA12 */
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/* I2C */
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#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2 /* PB6 */
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#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 /* PB7 */
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/* SPI */
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#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 /* PA5 */
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#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 /* PA6 */
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#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 /* PA7 */
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#endif /* __ARCH_BOARD_BOARD_H */
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@@ -0,0 +1,45 @@
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/****************************************************************************
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*
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* Copyright (c) 2021 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name PX4 nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#pragma once
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// DMA1 Channel/Stream Selections
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//--------------------------------------------//---------------------------//----------------
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// DMA2 Channel/Stream Selections
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//--------------------------------------------//---------------------------//----------------
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#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_2 // DMA2, Stream 2, Channel 3
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#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX // DMA2, Stream 3, Channel 0
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#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX // DMA2, Stream 4, Channel 0
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#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 // DMA2, Stream 5, Channel 3
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