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Basic functionality: CAN IO Manager, unit tests, debug stuff, memory management
This commit is contained in:
Pavel Kirienko
@@ -0,0 +1,446 @@
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/*
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* Copyright (C) 2014 Pavel Kirienko <pavel.kirienko@gmail.com>
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*/
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#include <queue>
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#include <vector>
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#include <gtest/gtest.h>
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#include "common.hpp"
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class CanIfaceMock : public uavcan::ICanIface
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{
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public:
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struct FrameWithTime
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{
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uavcan::CanFrame frame;
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uint64_t time;
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FrameWithTime(const uavcan::CanFrame& frame, uint64_t time)
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: frame(frame)
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, time(time)
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{ }
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};
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std::queue<FrameWithTime> tx; ///< Queue of outgoing frames (bus <-- library)
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std::queue<FrameWithTime> rx; ///< Queue of incoming frames (bus --> library)
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bool writeable;
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bool tx_failure;
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bool rx_failure;
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uint64_t num_errors;
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SystemClockMock& clockmock;
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CanIfaceMock(SystemClockMock& clockmock)
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: writeable(true)
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, tx_failure(false)
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, rx_failure(false)
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, num_errors(0)
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, clockmock(clockmock)
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{ }
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void pushRx(uavcan::CanFrame frame)
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{
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rx.push(FrameWithTime(frame, clockmock.utc));
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}
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bool matchAndPopTx(const uavcan::CanFrame& frame, uint64_t tx_deadline)
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{
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if (tx.empty())
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{
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std::cout << "Tx buffer is empty" << std::endl;
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return false;
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}
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const FrameWithTime frame_time = tx.front();
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tx.pop();
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return (frame_time.frame == frame) && (frame_time.time == tx_deadline);
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}
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int send(const uavcan::CanFrame& frame, uint64_t tx_timeout_usec)
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{
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assert(this);
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EXPECT_TRUE(writeable); // Shall never be called when not writeable
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if (tx_failure)
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return -1;
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if (!writeable)
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return 0;
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const uint64_t monotonic_deadline = tx_timeout_usec + clockmock.monotonic;
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tx.push(FrameWithTime(frame, monotonic_deadline));
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return 1;
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}
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int receive(uavcan::CanFrame& out_frame, uint64_t& out_utc_timestamp_usec)
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{
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assert(this);
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EXPECT_TRUE(rx.size()); // Shall never be called when not readable
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if (rx_failure)
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return -1;
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if (rx.empty())
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return 0;
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const FrameWithTime frame = rx.front();
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rx.pop();
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out_frame = frame.frame;
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out_utc_timestamp_usec = frame.time;
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return 1;
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}
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int configureFilters(const uavcan::CanFilterConfig* filter_configs, int num_configs) { return -1; }
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int getNumFilters() const { return 0; }
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uint64_t getNumErrors() const { return num_errors; }
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};
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class CanDriverMock : public uavcan::ICanDriver
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{
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public:
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std::vector<CanIfaceMock> ifaces;
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SystemClockMock& clockmock;
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bool select_failure;
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CanDriverMock(int num_ifaces, SystemClockMock& clockmock)
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: ifaces(num_ifaces, CanIfaceMock(clockmock))
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, clockmock(clockmock)
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, select_failure(false)
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{ }
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int select(int& inout_write_iface_mask, int& inout_read_iface_mask, uint64_t timeout_usec)
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{
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assert(this);
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std::cout << "Write/read masks: " << inout_write_iface_mask << "/" << inout_read_iface_mask << std::endl;
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if (select_failure)
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return -1;
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const int valid_iface_mask = (1 << getNumIfaces()) - 1;
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EXPECT_FALSE(inout_write_iface_mask & ~valid_iface_mask);
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EXPECT_FALSE(inout_read_iface_mask & ~valid_iface_mask);
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int out_write_mask = 0;
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int out_read_mask = 0;
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for (int i = 0; i < getNumIfaces(); i++)
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{
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const int mask = 1 << i;
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if ((inout_write_iface_mask & mask) && ifaces.at(i).writeable)
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out_write_mask |= mask;
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if ((inout_read_iface_mask & mask) && ifaces.at(i).rx.size())
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out_read_mask |= mask;
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}
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inout_write_iface_mask = out_write_mask;
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inout_read_iface_mask = out_read_mask;
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if ((out_write_mask | out_read_mask) == 0)
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{
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clockmock.advance(timeout_usec); // Emulating timeout
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return 0;
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}
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return 1; // This value is not being checked anyway, it just has to be greater than zero
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}
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uavcan::ICanIface* getIface(int iface_index) { return &ifaces.at(iface_index); }
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int getNumIfaces() const { return ifaces.size(); }
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};
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TEST(CanIOManager, CanDriverMock)
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{
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using uavcan::CanFrame;
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SystemClockMock clockmock;
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CanDriverMock driver(3, clockmock);
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ASSERT_EQ(3, driver.getNumIfaces());
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// All WR, no RD
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int mask_wr = 7;
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int mask_rd = 7;
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EXPECT_LT(0, driver.select(mask_wr, mask_rd, 100));
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EXPECT_EQ(7, mask_wr);
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EXPECT_EQ(0, mask_rd);
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for (int i = 0; i < 3; i++)
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driver.ifaces.at(i).writeable = false;
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// No WR, no RD
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mask_wr = 7;
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mask_rd = 7;
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EXPECT_EQ(0, driver.select(mask_wr, mask_rd, 100));
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EXPECT_EQ(0, mask_wr);
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EXPECT_EQ(0, mask_rd);
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EXPECT_EQ(100, clockmock.monotonic);
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EXPECT_EQ(100, clockmock.utc);
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// No WR, #1 RD
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const CanFrame fr1 = makeFrame(123, "foo", EXT);
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driver.ifaces.at(1).pushRx(fr1);
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mask_wr = 7;
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mask_rd = 6;
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EXPECT_LT(0, driver.select(mask_wr, mask_rd, 100));
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EXPECT_EQ(0, mask_wr);
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EXPECT_EQ(2, mask_rd);
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CanFrame fr2;
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uint64_t timestamp;
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EXPECT_EQ(1, driver.getIface(1)->receive(fr2, timestamp));
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EXPECT_EQ(fr1, fr2);
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EXPECT_EQ(100, timestamp);
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// #0 WR, #1 RD, Select failure
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driver.ifaces.at(0).writeable = true;
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driver.select_failure = true;
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mask_wr = 1;
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mask_rd = 7;
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EXPECT_EQ(-1, driver.select(mask_wr, mask_rd, 100));
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EXPECT_EQ(1, mask_wr); // Leaving masks unchanged - library must ignore them
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EXPECT_EQ(7, mask_rd);
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}
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static bool rxFrameEquals(const uavcan::CanRxFrame& rxframe, const uavcan::CanFrame& frame,
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uint64_t timestamp, int iface_index)
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{
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if (rxframe.frame != frame)
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{
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std::cout << "Frame mismatch:\n"
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<< " " << rxframe.frame.toString(uavcan::CanFrame::STR_ALIGNED) << "\n"
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<< " " << frame.toString(uavcan::CanFrame::STR_ALIGNED) << std::endl;
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}
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return (rxframe.frame == frame) && (rxframe.timestamp == timestamp) && (rxframe.iface_index == iface_index);
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}
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TEST(CanIOManager, Reception)
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{
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// Memory
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uavcan::PoolAllocator<sizeof(uavcan::CanTxQueue::Entry) * 4, sizeof(uavcan::CanTxQueue::Entry)> pool;
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uavcan::PoolManager<2> poolmgr;
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poolmgr.addPool(&pool);
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// Platform interface
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SystemClockMock clockmock;
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CanDriverMock driver(2, clockmock);
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// IO Manager
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uavcan::CanIOManager iomgr(&driver, &poolmgr, &clockmock);
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ASSERT_EQ(2, iomgr.getNumIfaces());
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/*
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* Empty, will time out
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*/
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uavcan::CanRxFrame frame;
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EXPECT_EQ(0, iomgr.receive(frame, 100));
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EXPECT_EQ(100, clockmock.monotonic);
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EXPECT_EQ(100, clockmock.utc);
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/*
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* Non empty from multiple ifaces
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*/
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const uavcan::CanFrame frames[2][3] = {
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{ makeFrame(1, "a0", EXT), makeFrame(99, "a1", EXT), makeFrame(803, "a2", STD) },
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{ makeFrame(6341, "b0", EXT), makeFrame(196, "b1", STD), makeFrame(73, "b2", EXT) },
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};
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clockmock.advance(10);
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driver.ifaces.at(0).pushRx(frames[0][0]); // Timestamp 110
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driver.ifaces.at(1).pushRx(frames[1][0]);
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clockmock.advance(10);
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driver.ifaces.at(0).pushRx(frames[0][1]); // Timestamp 120
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driver.ifaces.at(1).pushRx(frames[1][1]);
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clockmock.advance(10);
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driver.ifaces.at(0).pushRx(frames[0][2]); // Timestamp 130
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driver.ifaces.at(1).pushRx(frames[1][2]);
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clockmock.advance(10);
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EXPECT_EQ(1, iomgr.receive(frame, 0));
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EXPECT_TRUE(rxFrameEquals(frame, frames[0][0], 110, 0));
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EXPECT_EQ(1, iomgr.receive(frame, 0));
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EXPECT_TRUE(rxFrameEquals(frame, frames[0][1], 120, 0));
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EXPECT_EQ(1, iomgr.receive(frame, 0));
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EXPECT_TRUE(rxFrameEquals(frame, frames[0][2], 130, 0));
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EXPECT_EQ(1, iomgr.receive(frame, 0));
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EXPECT_TRUE(rxFrameEquals(frame, frames[1][0], 110, 1));
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EXPECT_EQ(1, iomgr.receive(frame, 0));
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EXPECT_TRUE(rxFrameEquals(frame, frames[1][1], 120, 1));
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EXPECT_EQ(1, iomgr.receive(frame, 0));
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EXPECT_TRUE(rxFrameEquals(frame, frames[1][2], 130, 1));
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EXPECT_EQ(0, iomgr.receive(frame, 0)); // Will time out
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/*
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* Errors
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*/
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driver.select_failure = true;
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EXPECT_EQ(-1, iomgr.receive(frame, 0));
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driver.select_failure = false;
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driver.ifaces.at(1).pushRx(frames[0][0]);
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driver.ifaces.at(1).rx_failure = true;
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EXPECT_EQ(-1, iomgr.receive(frame, 0));
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driver.ifaces.at(0).num_errors = 9000;
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driver.ifaces.at(1).num_errors = 100500;
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EXPECT_EQ(9000, iomgr.getNumErrors(0));
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EXPECT_EQ(100500, iomgr.getNumErrors(1));
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}
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TEST(CanIOManager, Transmission)
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{
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using uavcan::CanIOManager;
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using uavcan::CanTxQueue;
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// Memory
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typedef uavcan::PoolAllocator<sizeof(CanTxQueue::Entry) * 4, sizeof(CanTxQueue::Entry)> Pool1;
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Pool1* ppool = new Pool1();
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Pool1& pool = *ppool;
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uavcan::PoolManager<2> poolmgr;
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poolmgr.addPool(&pool);
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// Platform interface
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SystemClockMock clockmock;
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CanDriverMock driver(2, clockmock);
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// IO Manager
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CanIOManager iomgr(&driver, &poolmgr, &clockmock);
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ASSERT_EQ(2, iomgr.getNumIfaces());
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const int ALL_IFACES_MASK = 3;
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const uavcan::CanFrame frames[] = {
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makeFrame(1, "a0", EXT), makeFrame(99, "a1", EXT), makeFrame(803, "a2", STD)
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};
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/*
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* Simple transmission
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*/
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EXPECT_EQ(2, iomgr.send(frames[0], 100, 0, ALL_IFACES_MASK, CanTxQueue::VOLATILE)); // To both
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EXPECT_TRUE(driver.ifaces.at(0).matchAndPopTx(frames[0], 100));
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EXPECT_TRUE(driver.ifaces.at(1).matchAndPopTx(frames[0], 100));
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EXPECT_EQ(1, iomgr.send(frames[1], 200, 100, 2, CanTxQueue::PERSISTENT)); // To #1
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EXPECT_TRUE(driver.ifaces.at(1).matchAndPopTx(frames[1], 200));
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EXPECT_EQ(0, clockmock.monotonic);
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EXPECT_EQ(0, clockmock.utc);
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EXPECT_TRUE(driver.ifaces.at(0).tx.empty());
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EXPECT_TRUE(driver.ifaces.at(1).tx.empty());
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EXPECT_EQ(0, iomgr.getNumErrors(0));
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EXPECT_EQ(0, iomgr.getNumErrors(1));
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/*
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* TX Queue basics
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*/
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EXPECT_EQ(0, pool.getNumUsedBlocks());
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// Sending to both, #0 blocked
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driver.ifaces.at(0).writeable = false;
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EXPECT_LT(0, iomgr.send(frames[0], 201, 200, ALL_IFACES_MASK, CanTxQueue::PERSISTENT));
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EXPECT_TRUE(driver.ifaces.at(1).matchAndPopTx(frames[0], 201));
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EXPECT_EQ(200, clockmock.monotonic);
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EXPECT_EQ(200, clockmock.utc);
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EXPECT_TRUE(driver.ifaces.at(0).tx.empty());
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EXPECT_TRUE(driver.ifaces.at(1).tx.empty());
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EXPECT_EQ(1, pool.getNumUsedBlocks()); // One frame went into TX queue, and will expire soon
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// Sending to both, both blocked
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driver.ifaces.at(1).writeable = false;
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EXPECT_EQ(0, iomgr.send(frames[1], 777, 300, ALL_IFACES_MASK, CanTxQueue::VOLATILE));
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EXPECT_EQ(3, pool.getNumUsedBlocks()); // Total 3 frames in TX queue now
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// Sending to #0, both blocked
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EXPECT_EQ(0, iomgr.send(frames[2], 888, 400, 1, CanTxQueue::PERSISTENT));
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EXPECT_EQ(400, clockmock.monotonic);
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EXPECT_EQ(400, clockmock.utc);
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EXPECT_TRUE(driver.ifaces.at(0).tx.empty());
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EXPECT_TRUE(driver.ifaces.at(1).tx.empty());
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EXPECT_EQ(4, pool.getNumUsedBlocks());
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// At this time TX queues are containing the following data:
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// iface 0: frames[0] (EXPIRED), frames[1], frames[2]
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// iface 1: frames[1]
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// Sending to #1, both writeable
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driver.ifaces.at(0).writeable = true;
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driver.ifaces.at(1).writeable = true;
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EXPECT_LT(0, iomgr.send(frames[0], 999, 500, 2, CanTxQueue::PERSISTENT));
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EXPECT_TRUE(driver.ifaces.at(0).matchAndPopTx(frames[1], 777)); // Note that frame[0] on iface #0 has expired
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EXPECT_TRUE(driver.ifaces.at(0).matchAndPopTx(frames[2], 888));
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EXPECT_TRUE(driver.ifaces.at(1).matchAndPopTx(frames[0], 999)); // In different order due to prioritization
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EXPECT_TRUE(driver.ifaces.at(1).matchAndPopTx(frames[1], 777));
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// Final checks
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ASSERT_EQ(0, driver.ifaces.at(0).tx.size());
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ASSERT_EQ(0, driver.ifaces.at(1).tx.size());
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EXPECT_EQ(0, pool.getNumUsedBlocks()); // Make sure the memory was properly released
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EXPECT_EQ(1, iomgr.getNumErrors(0)); // This is because of expired frame[0]
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EXPECT_EQ(0, iomgr.getNumErrors(1));
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/*
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* TX Queue updates from receive() call
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*/
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driver.ifaces.at(0).writeable = false;
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driver.ifaces.at(1).writeable = false;
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// Sending 5 frames, one will be rejected
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EXPECT_EQ(0, iomgr.send(frames[2], 2222, 1000, ALL_IFACES_MASK, CanTxQueue::PERSISTENT));
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EXPECT_EQ(0, iomgr.send(frames[0], 3333, 1100, 2, CanTxQueue::PERSISTENT));
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EXPECT_EQ(0, iomgr.send(frames[1], 4444, 1200, ALL_IFACES_MASK, CanTxQueue::VOLATILE)); // One frame kicked here
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// State checks
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EXPECT_EQ(4, pool.getNumUsedBlocks()); // TX queue is full
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EXPECT_EQ(1200, clockmock.monotonic);
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EXPECT_EQ(1200, clockmock.utc);
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EXPECT_TRUE(driver.ifaces.at(0).tx.empty());
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EXPECT_TRUE(driver.ifaces.at(1).tx.empty());
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// Preparing the driver mock for receive() call
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driver.ifaces.at(0).writeable = true;
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driver.ifaces.at(1).writeable = true;
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const uavcan::CanFrame rx_frames[] = { makeFrame(123, "rx0", STD), makeFrame(321, "rx1", EXT) };
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driver.ifaces.at(0).pushRx(rx_frames[0]);
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driver.ifaces.at(1).pushRx(rx_frames[1]);
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// This shall transmit _some_ frames now, at least one per iface (exact number can be changed - it will be OK)
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uavcan::CanRxFrame rx_frame;
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EXPECT_EQ(1, iomgr.receive(rx_frame, 0)); // Non-blocking
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EXPECT_TRUE(rxFrameEquals(rx_frame, rx_frames[0], 1200, 0));
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EXPECT_TRUE(driver.ifaces.at(0).matchAndPopTx(frames[1], 4444));
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EXPECT_TRUE(driver.ifaces.at(1).matchAndPopTx(frames[0], 3333));
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EXPECT_EQ(1, iomgr.receive(rx_frame, 0));
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EXPECT_TRUE(rxFrameEquals(rx_frame, rx_frames[1], 1200, 1));
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EXPECT_TRUE(driver.ifaces.at(0).matchAndPopTx(frames[2], 2222));
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EXPECT_TRUE(driver.ifaces.at(1).matchAndPopTx(frames[2], 2222)); // Iface #1, frame[1] was rejected (VOLATILE)
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// State checks
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EXPECT_EQ(0, pool.getNumUsedBlocks()); // TX queue is empty
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EXPECT_EQ(1200, clockmock.monotonic);
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EXPECT_EQ(1200, clockmock.utc);
|
||||
EXPECT_TRUE(driver.ifaces.at(0).tx.empty());
|
||||
EXPECT_TRUE(driver.ifaces.at(1).tx.empty());
|
||||
EXPECT_EQ(1, iomgr.getNumErrors(0));
|
||||
EXPECT_EQ(1, iomgr.getNumErrors(1)); // This is because of rejected frame[1]
|
||||
|
||||
/*
|
||||
* Error handling
|
||||
*/
|
||||
// Select failure
|
||||
driver.select_failure = true;
|
||||
EXPECT_EQ(-1, iomgr.receive(rx_frame, 2000));
|
||||
EXPECT_EQ(-1, iomgr.send(frames[0], 2100, 2000, ALL_IFACES_MASK, CanTxQueue::VOLATILE));
|
||||
EXPECT_EQ(1200, clockmock.monotonic);
|
||||
EXPECT_EQ(1200, clockmock.utc);
|
||||
|
||||
// Transmission failure
|
||||
driver.select_failure = false;
|
||||
driver.ifaces.at(0).writeable = true;
|
||||
driver.ifaces.at(1).writeable = true;
|
||||
driver.ifaces.at(0).tx_failure = true;
|
||||
driver.ifaces.at(1).tx_failure = true;
|
||||
EXPECT_GE(0, iomgr.send(frames[0], 2200, 0, ALL_IFACES_MASK, CanTxQueue::PERSISTENT)); // Non-blocking - return < 0
|
||||
|
||||
ASSERT_EQ(2, pool.getNumUsedBlocks()); // Untransmitted frames will be buffered
|
||||
|
||||
// Failure removed - transmission shall proceed
|
||||
driver.ifaces.at(0).tx_failure = false;
|
||||
driver.ifaces.at(1).tx_failure = false;
|
||||
EXPECT_EQ(0, iomgr.receive(rx_frame, 2500));
|
||||
EXPECT_TRUE(driver.ifaces.at(0).matchAndPopTx(frames[0], 2200));
|
||||
EXPECT_TRUE(driver.ifaces.at(1).matchAndPopTx(frames[0], 2200));
|
||||
EXPECT_EQ(0, pool.getNumUsedBlocks()); // All transmitted
|
||||
}
|
||||
Reference in New Issue
Block a user