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Incoporate new ARMv7-M exception handling logic contributed by Mike Smith

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git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4413 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
2012-02-22 18:14:18 +00:00
parent 58e84b6b86
commit 6c02000ba4
16 changed files with 721 additions and 107 deletions
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nuttx/arch/arm/include/armv7-m/irq.h
+80 -74
View File
@@ -71,80 +71,33 @@
#define REG_R9 (7) /* R9 */
#define REG_R10 (8) /* R10 */
#define REG_R11 (9) /* R11 */
#ifdef CONFIG_NUTTX_KERNEL
# define REG_EXC_RETURN (10) /* EXC_RETURN */
# define SW_INT_REGS (11)
#else
# define SW_INT_REGS (10)
#endif
/* If the MCU supports a floating point unit, then it will be necessary
* to save the state of the FPU status register and data registers on
* each context switch. These registers are not saved during interrupt
* level processing, however. So, as a consequence, floating point
* operations may NOT be performed in interrupt handlers.
*
* The FPU provides an extension register file containing 32 single-
* precision registers. These can be viewed as:
*
* - Sixteen 64-bit doubleword registers, D0-D15
* - Thirty-two 32-bit single-word registers, S0-S31
* S<2n> maps to the least significant half of D<n>
* S<2n+1> maps to the most significant half of D<n>.
*/
#define REG_EXC_RETURN (10) /* EXC_RETURN */
#define SW_INT_REGS (11)
#ifdef CONFIG_ARCH_FPU
# define REG_D0 (SW_INT_REGS+0) /* D0 */
# define REG_S0 (SW_INT_REGS+0) /* S0 */
# define REG_S1 (SW_INT_REGS+1) /* S1 */
# define REG_D1 (SW_INT_REGS+2) /* D1 */
# define REG_S2 (SW_INT_REGS+2) /* S2 */
# define REG_S3 (SW_INT_REGS+3) /* S3 */
# define REG_D2 (SW_INT_REGS+4) /* D2 */
# define REG_S4 (SW_INT_REGS+4) /* S4 */
# define REG_S5 (SW_INT_REGS+5) /* S5 */
# define REG_D3 (SW_INT_REGS+6) /* D3 */
# define REG_S6 (SW_INT_REGS+6) /* S6 */
# define REG_S7 (SW_INT_REGS+7) /* S7 */
# define REG_D4 (SW_INT_REGS+8) /* D4 */
# define REG_S8 (SW_INT_REGS+8) /* S8 */
# define REG_S9 (SW_INT_REGS+9) /* S9 */
# define REG_D5 (SW_INT_REGS+10) /* D5 */
# define REG_S10 (SW_INT_REGS+10) /* S10 */
# define REG_S11 (SW_INT_REGS+11) /* S11 */
# define REG_D6 (SW_INT_REGS+12) /* D6 */
# define REG_S12 (SW_INT_REGS+12) /* S12 */
# define REG_S13 (SW_INT_REGS+13) /* S13 */
# define REG_D7 (SW_INT_REGS+14) /* D7 */
# define REG_S14 (SW_INT_REGS+14) /* S14 */
# define REG_S15 (SW_INT_REGS+15) /* S15 */
# define REG_D8 (SW_INT_REGS+16) /* D8 */
# define REG_S16 (SW_INT_REGS+16) /* S16 */
# define REG_S17 (SW_INT_REGS+17) /* S17 */
# define REG_D9 (SW_INT_REGS+18) /* D9 */
# define REG_S18 (SW_INT_REGS+18) /* S18 */
# define REG_S19 (SW_INT_REGS+19) /* S19 */
# define REG_D10 (SW_INT_REGS+20) /* D10 */
# define REG_S20 (SW_INT_REGS+20) /* S20 */
# define REG_S21 (SW_INT_REGS+21) /* S21 */
# define REG_D11 (SW_INT_REGS+22) /* D11 */
# define REG_S22 (SW_INT_REGS+22) /* S22 */
# define REG_S23 (SW_INT_REGS+23) /* S23 */
# define REG_D12 (SW_INT_REGS+24) /* D12 */
# define REG_S24 (SW_INT_REGS+24) /* S24 */
# define REG_S25 (SW_INT_REGS+25) /* S25 */
# define REG_D13 (SW_INT_REGS+26) /* D13 */
# define REG_S26 (SW_INT_REGS+26) /* S26 */
# define REG_S27 (SW_INT_REGS+27) /* S27 */
# define REG_D14 (SW_INT_REGS+28) /* D14 */
# define REG_S28 (SW_INT_REGS+28) /* S28 */
# define REG_S29 (SW_INT_REGS+29) /* S29 */
# define REG_D15 (SW_INT_REGS+30) /* D15 */
# define REG_S30 (SW_INT_REGS+30) /* S30 */
# define REG_S31 (SW_INT_REGS+31) /* S31 */
# define REG_FPSCR (SW_INT_REGS+32) /* Floating point status and control */
# define SW_FPU_REGS (33)
/* If the MCU supports a floating point unit, then it will be necessary
* to save the state of the non-volatile registers before calling code
* that may save and overwrite them.
*/
# define REG_S16 (SW_INT_REGS+0) /* S16 */
# define REG_S17 (SW_INT_REGS+1) /* S17 */
# define REG_S18 (SW_INT_REGS+2) /* S18 */
# define REG_S19 (SW_INT_REGS+3) /* S19 */
# define REG_S20 (SW_INT_REGS+4) /* S20 */
# define REG_S21 (SW_INT_REGS+5) /* S21 */
# define REG_S22 (SW_INT_REGS+6) /* S22 */
# define REG_S23 (SW_INT_REGS+7) /* S23 */
# define REG_S24 (SW_INT_REGS+8) /* S24 */
# define REG_S25 (SW_INT_REGS+9) /* S25 */
# define REG_S26 (SW_INT_REGS+10) /* S26 */
# define REG_S27 (SW_INT_REGS+11) /* S27 */
# define REG_S28 (SW_INT_REGS+12) /* S28 */
# define REG_S29 (SW_INT_REGS+13) /* S29 */
# define REG_S30 (SW_INT_REGS+14) /* S30 */
# define REG_S31 (SW_INT_REGS+15) /* S31 */
# define SW_FPU_REGS (16)
#else
# define SW_FPU_REGS (0)
#endif
@@ -166,12 +119,41 @@
#define REG_R14 (SW_XCPT_REGS+5) /* R14 = LR */
#define REG_R15 (SW_XCPT_REGS+6) /* R15 = PC */
#define REG_XPSR (SW_XCPT_REGS+7) /* xPSR */
#define HW_INT_REGS (8)
#define HW_XCPT_REGS (8)
#ifdef CONFIG_ARCH_FPU
/* If the FPU is enabled, the hardware also saves the volatile FP registers.
*/
# define REG_S0 (SW_XCPT_REGS+8) /* S0 */
# define REG_S1 (SW_XCPT_REGS+9) /* S1 */
# define REG_S2 (SW_XCPT_REGS+10) /* S2 */
# define REG_S3 (SW_XCPT_REGS+11) /* S3 */
# define REG_S4 (SW_XCPT_REGS+12) /* S4 */
# define REG_S5 (SW_XCPT_REGS+13) /* S5 */
# define REG_S6 (SW_XCPT_REGS+14) /* S6 */
# define REG_S7 (SW_XCPT_REGS+15) /* S7 */
# define REG_S8 (SW_XCPT_REGS+16) /* S8 */
# define REG_S9 (SW_XCPT_REGS+17) /* S9 */
# define REG_S10 (SW_XCPT_REGS+18) /* S10 */
# define REG_S11 (SW_XCPT_REGS+19) /* S11 */
# define REG_S12 (SW_XCPT_REGS+20) /* S12 */
# define REG_S13 (SW_XCPT_REGS+21) /* S13 */
# define REG_S14 (SW_XCPT_REGS+22) /* S14 */
# define REG_S15 (SW_XCPT_REGS+23) /* S15 */
# define REG_FPSCR (SW_XCPT_REGS+24) /* FPSCR */
# define REG_FPReserved (SW_XCPT_REGS+25) /* Reserved */
# define HW_FPU_REGS (18)
#else
# define HW_FPU_REGS (0)
#endif
#define HW_XCPT_REGS (HW_INT_REGS + HW_FPU_REGS)
#define HW_XCPT_SIZE (4 * HW_XCPT_REGS)
#define XCPTCONTEXT_REGS (HW_XCPT_REGS + SW_XCPT_REGS)
#define XCPTCONTEXT_SIZE (HW_XCPT_SIZE + SW_XCPT_SIZE)
#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
/* Alternate register names */
@@ -364,6 +346,30 @@ static inline void setipsr(uint32_t ipsr)
: "memory");
}
/* Get/set CONTROL */
static inline uint32_t getcontrol(void)
{
uint32_t control;
__asm__ __volatile__
(
"\tmrs %0, control\n"
: "=r" (control)
:
: "memory");
return control;
}
static inline void setcontrol(uint32_t control)
{
__asm__ __volatile__
(
"\tmsr control, %0\n"
:
: "r" (control)
: "memory");
}
#endif /* __ASSEMBLY__ */
/****************************************************************************