From 6b4c14a15c10ea6e78049ac1018cb19e60233645 Mon Sep 17 00:00:00 2001 From: Daniel Agar Date: Thu, 9 Jul 2020 12:23:10 -0400 Subject: [PATCH] mpu6500: accumulated minor improvements and cleanup - perform reset as per the datasheet (disable I2C immediately, set power mode, wait for appropriate time, etc) - only track consecutive errors (not total) to trigger full reset if necessary - remove interrupt perf counter and instead only count misses - minor style changes to stay in sync with the other Invensense drivers --- .../mpu6500/InvenSense_MPU6500_registers.hpp | 8 +- .../imu/invensense/mpu6500/MPU6500.cpp | 282 +++++++++--------- .../imu/invensense/mpu6500/MPU6500.hpp | 39 ++- 3 files changed, 170 insertions(+), 159 deletions(-) diff --git a/src/drivers/imu/invensense/mpu6500/InvenSense_MPU6500_registers.hpp b/src/drivers/imu/invensense/mpu6500/InvenSense_MPU6500_registers.hpp index 2691604004..d1e04aa3b3 100644 --- a/src/drivers/imu/invensense/mpu6500/InvenSense_MPU6500_registers.hpp +++ b/src/drivers/imu/invensense/mpu6500/InvenSense_MPU6500_registers.hpp @@ -151,7 +151,7 @@ enum SIGNAL_PATH_RESET_BIT : uint8_t { enum USER_CTRL_BIT : uint8_t { FIFO_EN = Bit6, I2C_MST_EN = Bit5, - I2C_IF_DIS = Bit4, + I2C_IF_DIS = Bit4, // Always write 0 to I2C_IF_DIS. FIFO_RST = Bit2, I2C_MST_RST = Bit1, @@ -163,12 +163,10 @@ enum PWR_MGMT_1_BIT : uint8_t { H_RESET = Bit7, SLEEP = Bit6, - CLKSEL_2 = Bit2, - CLKSEL_1 = Bit1, - CLKSEL_0 = Bit0, + // CLKSEL[2:0] + CLKSEL_0 = Bit0, // It is required that CLKSEL[2:0] be set to 001 to achieve full gyroscope performance. }; - namespace FIFO { static constexpr size_t SIZE = 512; diff --git a/src/drivers/imu/invensense/mpu6500/MPU6500.cpp b/src/drivers/imu/invensense/mpu6500/MPU6500.cpp index 303119558b..57a08acfd0 100644 --- a/src/drivers/imu/invensense/mpu6500/MPU6500.cpp +++ b/src/drivers/imu/invensense/mpu6500/MPU6500.cpp @@ -48,6 +48,10 @@ MPU6500::MPU6500(I2CSPIBusOption bus_option, int bus, uint32_t device, enum Rota _px4_accel(get_device_id(), ORB_PRIO_HIGH, rotation), _px4_gyro(get_device_id(), ORB_PRIO_HIGH, rotation) { + if (drdy_gpio != 0) { + _drdy_missed_perf = perf_alloc(PC_COUNT, MODULE_NAME": DRDY missed"); + } + ConfigureSampleRate(_px4_gyro.get_max_rate_hz()); } @@ -58,7 +62,7 @@ MPU6500::~MPU6500() perf_free(_fifo_empty_perf); perf_free(_fifo_overflow_perf); perf_free(_fifo_reset_perf); - perf_free(_drdy_interval_perf); + perf_free(_drdy_missed_perf); } int MPU6500::init() @@ -76,6 +80,7 @@ int MPU6500::init() bool MPU6500::Reset() { _state = STATE::RESET; + DataReadyInterruptDisable(); ScheduleClear(); ScheduleNow(); return true; @@ -90,16 +95,15 @@ void MPU6500::exit_and_cleanup() void MPU6500::print_status() { I2CSPIDriverBase::print_status(); - PX4_INFO("FIFO empty interval: %d us (%.3f Hz)", _fifo_empty_interval_us, - static_cast(1000000 / _fifo_empty_interval_us)); + + PX4_INFO("FIFO empty interval: %d us (%.1f Hz)", _fifo_empty_interval_us, 1e6 / _fifo_empty_interval_us); perf_print_counter(_bad_register_perf); perf_print_counter(_bad_transfer_perf); perf_print_counter(_fifo_empty_perf); perf_print_counter(_fifo_overflow_perf); perf_print_counter(_fifo_reset_perf); - perf_print_counter(_drdy_interval_perf); - + perf_print_counter(_drdy_missed_perf); } int MPU6500::probe() @@ -116,11 +120,14 @@ int MPU6500::probe() void MPU6500::RunImpl() { + const hrt_abstime now = hrt_absolute_time(); + switch (_state) { case STATE::RESET: // PWR_MGMT_1: Device Reset RegisterWrite(Register::PWR_MGMT_1, PWR_MGMT_1_BIT::H_RESET); - _reset_timestamp = hrt_absolute_time(); + _reset_timestamp = now; + _failure_count = 0; _state = STATE::WAIT_FOR_RESET; ScheduleDelayed(100_ms); break; @@ -132,9 +139,10 @@ void MPU6500::RunImpl() if ((RegisterRead(Register::WHO_AM_I) == WHOAMI) && (RegisterRead(Register::PWR_MGMT_1) == 0x01)) { - // SIGNAL_PATH_RESET: ensure the reset is performed properly - RegisterWrite(Register::SIGNAL_PATH_RESET, - SIGNAL_PATH_RESET_BIT::GYRO_RESET | SIGNAL_PATH_RESET_BIT::ACCEL_RESET | SIGNAL_PATH_RESET_BIT::TEMP_RESET); + // Wakeup and reset digital signal path + RegisterWrite(Register::PWR_MGMT_1, PWR_MGMT_1_BIT::CLKSEL_0); + RegisterWrite(Register::SIGNAL_PATH_RESET, SIGNAL_PATH_RESET_BIT::ACCEL_RESET | SIGNAL_PATH_RESET_BIT::TEMP_RESET); + RegisterWrite(Register::USER_CTRL, USER_CTRL_BIT::SIG_COND_RST | USER_CTRL_BIT::I2C_IF_DIS); // if reset succeeded then configure _state = STATE::CONFIGURE; @@ -142,7 +150,7 @@ void MPU6500::RunImpl() } else { // RESET not complete - if (hrt_elapsed_time(&_reset_timestamp) > 100_ms) { + if (hrt_elapsed_time(&_reset_timestamp) > 1000_ms) { PX4_DEBUG("Reset failed, retrying"); _state = STATE::RESET; ScheduleDelayed(100_ms); @@ -164,7 +172,7 @@ void MPU6500::RunImpl() _data_ready_interrupt_enabled = true; // backup schedule as a watchdog timeout - ScheduleDelayed(10_ms); + ScheduleDelayed(100_ms); } else { _data_ready_interrupt_enabled = false; @@ -174,73 +182,90 @@ void MPU6500::RunImpl() FIFOReset(); } else { - PX4_DEBUG("Configure failed, retrying"); - // try again in 10 ms - ScheduleDelayed(10_ms); + // CONFIGURE not complete + if (hrt_elapsed_time(&_reset_timestamp) > 1000_ms) { + PX4_DEBUG("Configure failed, resetting"); + _state = STATE::RESET; + + } else { + PX4_DEBUG("Configure failed, retrying"); + } + + ScheduleDelayed(100_ms); } break; case STATE::FIFO_READ: { - hrt_abstime timestamp_sample = 0; - if (_data_ready_interrupt_enabled) { - // re-schedule as watchdog timeout - ScheduleDelayed(10_ms); - } - - if (_data_ready_interrupt_enabled && (hrt_elapsed_time(×tamp_sample) < (_fifo_empty_interval_us / 2))) { - // use timestamp from data ready interrupt if enabled and seems valid - timestamp_sample = _fifo_watermark_interrupt_timestamp; - - } else { - // use the time now roughly corresponding with the last sample we'll pull from the FIFO - timestamp_sample = hrt_absolute_time(); - } - - const uint16_t fifo_count = FIFOReadCount(); - const uint8_t samples = (fifo_count / sizeof(FIFO::DATA) / SAMPLES_PER_TRANSFER) * - SAMPLES_PER_TRANSFER; // round down to nearest - - bool failure = false; - - if (samples > FIFO_MAX_SAMPLES) { - // not technically an overflow, but more samples than we expected or can publish - perf_count(_fifo_overflow_perf); - failure = true; - FIFOReset(); - - } else if (samples >= SAMPLES_PER_TRANSFER) { - // require at least SAMPLES_PER_TRANSFER (we want at least 1 new accel sample per transfer) - if (!FIFORead(timestamp_sample, samples)) { - failure = true; - _px4_accel.increase_error_count(); - _px4_gyro.increase_error_count(); + // scheduled from interrupt if _drdy_fifo_read_samples was set + if (_drdy_fifo_read_samples.fetch_and(0) != _fifo_gyro_samples) { + perf_count(_drdy_missed_perf); } - } else if (samples == 0) { - failure = true; - perf_count(_fifo_empty_perf); + // push backup schedule back + ScheduleDelayed(_fifo_empty_interval_us * 2); } - if (failure || hrt_elapsed_time(&_last_config_check_timestamp) > 10_ms) { - // check registers incrementally - if (RegisterCheck(_register_cfg[_checked_register], true)) { - _last_config_check_timestamp = timestamp_sample; + // always check current FIFO count + bool success = false; + const uint16_t fifo_count = FIFOReadCount(); + + if (fifo_count >= FIFO::SIZE) { + FIFOReset(); + perf_count(_fifo_overflow_perf); + + } else if (fifo_count == 0) { + perf_count(_fifo_empty_perf); + + } else { + // FIFO count (size in bytes) should be a multiple of the FIFO::DATA structure + const uint8_t samples = (fifo_count / sizeof(FIFO::DATA) / SAMPLES_PER_TRANSFER) * + SAMPLES_PER_TRANSFER; // round down to nearest + + if (samples > FIFO_MAX_SAMPLES) { + // not technically an overflow, but more samples than we expected or can publish + FIFOReset(); + perf_count(_fifo_overflow_perf); + + } else if (samples >= 1) { + if (FIFORead(now, samples)) { + success = true; + + if (_failure_count > 0) { + _failure_count--; + } + } + } + } + + if (!success) { + _failure_count++; + + // full reset if things are failing consistently + if (_failure_count > 10) { + Reset(); + return; + } + } + + if (!success || hrt_elapsed_time(&_last_config_check_timestamp) > 100_ms) { + // check configuration registers periodically or immediately following any failure + if (RegisterCheck(_register_cfg[_checked_register])) { + _last_config_check_timestamp = now; _checked_register = (_checked_register + 1) % size_register_cfg; } else { - // register check failed, force reconfigure - PX4_DEBUG("Health check failed, reconfiguring"); - _state = STATE::CONFIGURE; - ScheduleNow(); + // register check failed, force reset + perf_count(_bad_register_perf); + Reset(); } } else { - // periodically update temperature (1 Hz) - if (hrt_elapsed_time(&_temperature_update_timestamp) > 1_s) { + // periodically update temperature (~1 Hz) + if (hrt_elapsed_time(&_temperature_update_timestamp) >= 1_s) { UpdateTemperature(); - _temperature_update_timestamp = timestamp_sample; + _temperature_update_timestamp = now; } } } @@ -255,23 +280,23 @@ void MPU6500::ConfigureAccel() switch (ACCEL_FS_SEL) { case ACCEL_FS_SEL_2G: - _px4_accel.set_scale(CONSTANTS_ONE_G / 16384); - _px4_accel.set_range(2 * CONSTANTS_ONE_G); + _px4_accel.set_scale(CONSTANTS_ONE_G / 16384.f); + _px4_accel.set_range(2.f * CONSTANTS_ONE_G); break; case ACCEL_FS_SEL_4G: - _px4_accel.set_scale(CONSTANTS_ONE_G / 8192); - _px4_accel.set_range(4 * CONSTANTS_ONE_G); + _px4_accel.set_scale(CONSTANTS_ONE_G / 8192.f); + _px4_accel.set_range(4.f * CONSTANTS_ONE_G); break; case ACCEL_FS_SEL_8G: - _px4_accel.set_scale(CONSTANTS_ONE_G / 4096); - _px4_accel.set_range(8 * CONSTANTS_ONE_G); + _px4_accel.set_scale(CONSTANTS_ONE_G / 4096.f); + _px4_accel.set_range(8.f * CONSTANTS_ONE_G); break; case ACCEL_FS_SEL_16G: - _px4_accel.set_scale(CONSTANTS_ONE_G / 2048); - _px4_accel.set_range(16 * CONSTANTS_ONE_G); + _px4_accel.set_scale(CONSTANTS_ONE_G / 2048.f); + _px4_accel.set_range(16.f * CONSTANTS_ONE_G); break; } } @@ -311,23 +336,27 @@ void MPU6500::ConfigureSampleRate(int sample_rate) } // round down to nearest FIFO sample dt * SAMPLES_PER_TRANSFER - const float min_interval = SAMPLES_PER_TRANSFER * FIFO_SAMPLE_DT; + const float min_interval = FIFO_SAMPLE_DT * SAMPLES_PER_TRANSFER; _fifo_empty_interval_us = math::max(roundf((1e6f / (float)sample_rate) / min_interval) * min_interval, min_interval); - _fifo_gyro_samples = math::min((float)_fifo_empty_interval_us / (1e6f / GYRO_RATE), (float)FIFO_MAX_SAMPLES); + _fifo_gyro_samples = roundf(math::min((float)_fifo_empty_interval_us / (1e6f / GYRO_RATE), (float)FIFO_MAX_SAMPLES)); // recompute FIFO empty interval (us) with actual gyro sample limit _fifo_empty_interval_us = _fifo_gyro_samples * (1e6f / GYRO_RATE); - - _fifo_accel_samples = math::min(_fifo_empty_interval_us / (1e6f / ACCEL_RATE), (float)FIFO_MAX_SAMPLES); } bool MPU6500::Configure() { + // first set and clear all configured register bits + for (const auto ®_cfg : _register_cfg) { + RegisterSetAndClearBits(reg_cfg.reg, reg_cfg.set_bits, reg_cfg.clear_bits); + } + + // now check that all are configured bool success = true; - for (const auto ® : _register_cfg) { - if (!RegisterCheck(reg)) { + for (const auto ®_cfg : _register_cfg) { + if (!RegisterCheck(reg_cfg)) { success = false; } } @@ -346,12 +375,13 @@ int MPU6500::DataReadyInterruptCallback(int irq, void *context, void *arg) void MPU6500::DataReady() { - perf_count(_drdy_interval_perf); + uint32_t expected = 0; - if (_data_ready_count.fetch_add(1) >= (_fifo_gyro_samples - 1)) { - _data_ready_count.store(0); - _fifo_watermark_interrupt_timestamp = hrt_absolute_time(); - _fifo_read_samples.store(_fifo_gyro_samples); + // at least the required number of samples in the FIFO + if (((_drdy_count.fetch_add(1) + 1) >= _fifo_gyro_samples) + && _drdy_fifo_read_samples.compare_exchange(&expected, _fifo_gyro_samples)) { + + _drdy_count.store(0); ScheduleNow(); } } @@ -363,7 +393,7 @@ bool MPU6500::DataReadyInterruptConfigure() } // Setup data ready on falling edge - return px4_arch_gpiosetevent(_drdy_gpio, false, true, true, &MPU6500::DataReadyInterruptCallback, this) == 0; + return px4_arch_gpiosetevent(_drdy_gpio, false, true, true, &DataReadyInterruptCallback, this) == 0; } bool MPU6500::DataReadyInterruptDisable() @@ -375,7 +405,7 @@ bool MPU6500::DataReadyInterruptDisable() return px4_arch_gpiosetevent(_drdy_gpio, false, false, false, nullptr, nullptr) == 0; } -bool MPU6500::RegisterCheck(const register_config_t ®_cfg, bool notify) +bool MPU6500::RegisterCheck(const register_config_t ®_cfg) { bool success = true; @@ -391,16 +421,6 @@ bool MPU6500::RegisterCheck(const register_config_t ®_cfg, bool notify) success = false; } - if (!success) { - RegisterSetAndClearBits(reg_cfg.reg, reg_cfg.set_bits, reg_cfg.clear_bits); - - if (notify) { - perf_count(_bad_register_perf); - _px4_accel.increase_error_count(); - _px4_gyro.increase_error_count(); - } - } - return success; } @@ -423,17 +443,12 @@ void MPU6500::RegisterWrite(Register reg, uint8_t value) void MPU6500::RegisterSetAndClearBits(Register reg, uint8_t setbits, uint8_t clearbits) { const uint8_t orig_val = RegisterRead(reg); - uint8_t val = orig_val; - if (setbits) { - val |= setbits; + uint8_t val = (orig_val & ~clearbits) | setbits; + + if (orig_val != val) { + RegisterWrite(reg, val); } - - if (clearbits) { - val &= ~clearbits; - } - - RegisterWrite(reg, val); } uint16_t MPU6500::FIFOReadCount() @@ -451,9 +466,8 @@ uint16_t MPU6500::FIFOReadCount() return combine(fifo_count_buf[1], fifo_count_buf[2]); } -bool MPU6500::FIFORead(const hrt_abstime ×tamp_sample, uint16_t samples) +bool MPU6500::FIFORead(const hrt_abstime ×tamp_sample, uint8_t samples) { - FIFOTransferBuffer buffer{}; const size_t transfer_size = math::min(samples * sizeof(FIFO::DATA) + 1, FIFO::SIZE); set_frequency(SPI_SPEED_SENSOR); @@ -464,8 +478,8 @@ bool MPU6500::FIFORead(const hrt_abstime ×tamp_sample, uint16_t samples) } - ProcessGyro(timestamp_sample, buffer, samples); - return ProcessAccel(timestamp_sample, buffer, samples); + ProcessGyro(timestamp_sample, buffer.f, samples); + return ProcessAccel(timestamp_sample, buffer.f, samples); } void MPU6500::FIFOReset() @@ -479,9 +493,8 @@ void MPU6500::FIFOReset() RegisterSetAndClearBits(Register::USER_CTRL, USER_CTRL_BIT::FIFO_RST, USER_CTRL_BIT::FIFO_EN); // reset while FIFO is disabled - _data_ready_count.store(0); - _fifo_watermark_interrupt_timestamp = 0; - _fifo_read_samples.store(0); + _drdy_count.store(0); + _drdy_fifo_read_samples.store(0); // FIFO_EN: enable both gyro and accel // USER_CTRL: re-enable FIFO @@ -497,11 +510,12 @@ static bool fifo_accel_equal(const FIFO::DATA &f0, const FIFO::DATA &f1) return (memcmp(&f0.ACCEL_XOUT_H, &f1.ACCEL_XOUT_H, 6) == 0); } -bool MPU6500::ProcessAccel(const hrt_abstime ×tamp_sample, const FIFOTransferBuffer &buffer, const uint8_t samples) +bool MPU6500::ProcessAccel(const hrt_abstime ×tamp_sample, const FIFO::DATA fifo[], const uint8_t samples) { sensor_accel_fifo_s accel{}; accel.timestamp_sample = timestamp_sample; - accel.dt = _fifo_empty_interval_us / _fifo_accel_samples; + accel.samples = 0; + accel.dt = FIFO_SAMPLE_DT * SAMPLES_PER_TRANSFER; bool bad_data = false; @@ -509,58 +523,57 @@ bool MPU6500::ProcessAccel(const hrt_abstime ×tamp_sample, const FIFOTransf int accel_first_sample = 1; if (samples >= 4) { - if (fifo_accel_equal(buffer.f[0], buffer.f[1]) && fifo_accel_equal(buffer.f[2], buffer.f[3])) { + if (fifo_accel_equal(fifo[0], fifo[1]) && fifo_accel_equal(fifo[2], fifo[3])) { // [A0, A1, A2, A3] // A0==A1, A2==A3 accel_first_sample = 1; - } else if (fifo_accel_equal(buffer.f[1], buffer.f[2])) { + } else if (fifo_accel_equal(fifo[1], fifo[2])) { // [A0, A1, A2, A3] // A0, A1==A2, A3 accel_first_sample = 0; } else { - perf_count(_bad_transfer_perf); + // no matching accel samples is an error bad_data = true; + perf_count(_bad_transfer_perf); } } - int accel_samples = 0; - - for (int i = accel_first_sample; i < samples; i = i + 2) { - const FIFO::DATA &fifo_sample = buffer.f[i]; - int16_t accel_x = combine(fifo_sample.ACCEL_XOUT_H, fifo_sample.ACCEL_XOUT_L); - int16_t accel_y = combine(fifo_sample.ACCEL_YOUT_H, fifo_sample.ACCEL_YOUT_L); - int16_t accel_z = combine(fifo_sample.ACCEL_ZOUT_H, fifo_sample.ACCEL_ZOUT_L); + for (int i = accel_first_sample; i < samples; i = i + SAMPLES_PER_TRANSFER) { + int16_t accel_x = combine(fifo[i].ACCEL_XOUT_H, fifo[i].ACCEL_XOUT_L); + int16_t accel_y = combine(fifo[i].ACCEL_YOUT_H, fifo[i].ACCEL_YOUT_L); + int16_t accel_z = combine(fifo[i].ACCEL_ZOUT_H, fifo[i].ACCEL_ZOUT_L); // sensor's frame is +x forward, +y left, +z up // flip y & z to publish right handed with z down (x forward, y right, z down) - accel.x[accel_samples] = accel_x; - accel.y[accel_samples] = (accel_y == INT16_MIN) ? INT16_MAX : -accel_y; - accel.z[accel_samples] = (accel_z == INT16_MIN) ? INT16_MAX : -accel_z; - accel_samples++; + accel.x[accel.samples] = accel_x; + accel.y[accel.samples] = (accel_y == INT16_MIN) ? INT16_MAX : -accel_y; + accel.z[accel.samples] = (accel_z == INT16_MIN) ? INT16_MAX : -accel_z; + accel.samples++; } - accel.samples = accel_samples; + _px4_accel.set_error_count(perf_event_count(_bad_register_perf) + perf_event_count(_bad_transfer_perf) + + perf_event_count(_fifo_empty_perf) + perf_event_count(_fifo_overflow_perf)); - _px4_accel.updateFIFO(accel); + if (accel.samples > 0) { + _px4_accel.updateFIFO(accel); + } return !bad_data; } -void MPU6500::ProcessGyro(const hrt_abstime ×tamp_sample, const FIFOTransferBuffer &buffer, const uint8_t samples) +void MPU6500::ProcessGyro(const hrt_abstime ×tamp_sample, const FIFO::DATA fifo[], const uint8_t samples) { sensor_gyro_fifo_s gyro{}; gyro.timestamp_sample = timestamp_sample; gyro.samples = samples; - gyro.dt = _fifo_empty_interval_us / _fifo_gyro_samples; + gyro.dt = FIFO_SAMPLE_DT; for (int i = 0; i < samples; i++) { - const FIFO::DATA &fifo_sample = buffer.f[i]; - - const int16_t gyro_x = combine(fifo_sample.GYRO_XOUT_H, fifo_sample.GYRO_XOUT_L); - const int16_t gyro_y = combine(fifo_sample.GYRO_YOUT_H, fifo_sample.GYRO_YOUT_L); - const int16_t gyro_z = combine(fifo_sample.GYRO_ZOUT_H, fifo_sample.GYRO_ZOUT_L); + const int16_t gyro_x = combine(fifo[i].GYRO_XOUT_H, fifo[i].GYRO_XOUT_L); + const int16_t gyro_y = combine(fifo[i].GYRO_YOUT_H, fifo[i].GYRO_YOUT_L); + const int16_t gyro_z = combine(fifo[i].GYRO_ZOUT_H, fifo[i].GYRO_ZOUT_L); // sensor's frame is +x forward, +y left, +z up // flip y & z to publish right handed with z down (x forward, y right, z down) @@ -569,6 +582,9 @@ void MPU6500::ProcessGyro(const hrt_abstime ×tamp_sample, const FIFOTransfe gyro.z[i] = (gyro_z == INT16_MIN) ? INT16_MAX : -gyro_z; } + _px4_gyro.set_error_count(perf_event_count(_bad_register_perf) + perf_event_count(_bad_transfer_perf) + + perf_event_count(_fifo_empty_perf) + perf_event_count(_fifo_overflow_perf)); + _px4_gyro.updateFIFO(gyro); } diff --git a/src/drivers/imu/invensense/mpu6500/MPU6500.hpp b/src/drivers/imu/invensense/mpu6500/MPU6500.hpp index 237b2fbc96..671d19165a 100644 --- a/src/drivers/imu/invensense/mpu6500/MPU6500.hpp +++ b/src/drivers/imu/invensense/mpu6500/MPU6500.hpp @@ -73,10 +73,10 @@ private: void exit_and_cleanup() override; // Sensor Configuration - static constexpr float FIFO_SAMPLE_DT{125.f}; - static constexpr uint32_t SAMPLES_PER_TRANSFER{2}; // ensure at least 1 new accel sample per transfer - static constexpr float GYRO_RATE{1e6f / FIFO_SAMPLE_DT}; // 8 kHz gyro - static constexpr float ACCEL_RATE{GYRO_RATE / 2.f}; // 4 kHz accel + static constexpr float FIFO_SAMPLE_DT{1e6f / 8000.f}; + static constexpr uint32_t SAMPLES_PER_TRANSFER{2}; // ensure at least 1 new accel sample per transfer + static constexpr float GYRO_RATE{1e6f / FIFO_SAMPLE_DT}; // 8000 Hz gyro + static constexpr float ACCEL_RATE{GYRO_RATE / SAMPLES_PER_TRANSFER}; // 4000 Hz accel // maximum FIFO samples per transfer is limited to the size of sensor_accel_fifo/sensor_gyro_fifo static constexpr uint32_t FIFO_MAX_SAMPLES{math::min(math::min(FIFO::SIZE / sizeof(FIFO::DATA), sizeof(sensor_gyro_fifo_s::x) / sizeof(sensor_gyro_fifo_s::x[0])), sizeof(sensor_accel_fifo_s::x) / sizeof(sensor_accel_fifo_s::x[0]) * (int)(GYRO_RATE / ACCEL_RATE))}; @@ -109,20 +109,18 @@ private: bool DataReadyInterruptConfigure(); bool DataReadyInterruptDisable(); - bool RegisterCheck(const register_config_t ®_cfg, bool notify = false); + bool RegisterCheck(const register_config_t ®_cfg); uint8_t RegisterRead(Register reg); void RegisterWrite(Register reg, uint8_t value); void RegisterSetAndClearBits(Register reg, uint8_t setbits, uint8_t clearbits); - void RegisterSetBits(Register reg, uint8_t setbits) { RegisterSetAndClearBits(reg, setbits, 0); } - void RegisterClearBits(Register reg, uint8_t clearbits) { RegisterSetAndClearBits(reg, 0, clearbits); } uint16_t FIFOReadCount(); - bool FIFORead(const hrt_abstime ×tamp_sample, uint16_t samples); + bool FIFORead(const hrt_abstime ×tamp_sample, uint8_t samples); void FIFOReset(); - bool ProcessAccel(const hrt_abstime ×tamp_sample, const FIFOTransferBuffer &buffer, const uint8_t samples); - void ProcessGyro(const hrt_abstime ×tamp_sample, const FIFOTransferBuffer &buffer, const uint8_t samples); + bool ProcessAccel(const hrt_abstime ×tamp_sample, const FIFO::DATA fifo[], const uint8_t samples); + void ProcessGyro(const hrt_abstime ×tamp_sample, const FIFO::DATA fifo[], const uint8_t samples); void UpdateTemperature(); const spi_drdy_gpio_t _drdy_gpio; @@ -135,15 +133,15 @@ private: perf_counter_t _fifo_empty_perf{perf_alloc(PC_COUNT, MODULE_NAME": FIFO empty")}; perf_counter_t _fifo_overflow_perf{perf_alloc(PC_COUNT, MODULE_NAME": FIFO overflow")}; perf_counter_t _fifo_reset_perf{perf_alloc(PC_COUNT, MODULE_NAME": FIFO reset")}; - perf_counter_t _drdy_interval_perf{perf_alloc(PC_INTERVAL, MODULE_NAME": DRDY interval")}; + perf_counter_t _drdy_missed_perf{nullptr}; hrt_abstime _reset_timestamp{0}; hrt_abstime _last_config_check_timestamp{0}; - hrt_abstime _fifo_watermark_interrupt_timestamp{0}; hrt_abstime _temperature_update_timestamp{0}; + int _failure_count{0}; - px4::atomic _data_ready_count{0}; - px4::atomic _fifo_read_samples{0}; + px4::atomic _drdy_fifo_read_samples{0}; + px4::atomic _drdy_count{0}; bool _data_ready_interrupt_enabled{false}; enum class STATE : uint8_t { @@ -156,21 +154,20 @@ private: STATE _state{STATE::RESET}; uint16_t _fifo_empty_interval_us{1250}; // default 1250 us / 800 Hz transfer interval - uint8_t _fifo_gyro_samples{static_cast(_fifo_empty_interval_us / (1000000 / GYRO_RATE))}; - uint8_t _fifo_accel_samples{static_cast(_fifo_empty_interval_us / (1000000 / ACCEL_RATE))}; + uint32_t _fifo_gyro_samples{static_cast(_fifo_empty_interval_us / (1000000 / GYRO_RATE))}; uint8_t _checked_register{0}; static constexpr uint8_t size_register_cfg{9}; register_config_t _register_cfg[size_register_cfg] { // Register | Set bits, Clear bits - { Register::PWR_MGMT_1, PWR_MGMT_1_BIT::CLKSEL_0, PWR_MGMT_1_BIT::H_RESET | PWR_MGMT_1_BIT::SLEEP }, + { Register::CONFIG, CONFIG_BIT::FIFO_MODE | CONFIG_BIT::DLPF_CFG_BYPASS_DLPF_8KHZ, 0 }, + { Register::GYRO_CONFIG, GYRO_CONFIG_BIT::GYRO_FS_SEL_2000_DPS, GYRO_CONFIG_BIT::FCHOICE_B_8KHZ_BYPASS_DLPF }, { Register::ACCEL_CONFIG, ACCEL_CONFIG_BIT::ACCEL_FS_SEL_16G, 0 }, { Register::ACCEL_CONFIG2, ACCEL_CONFIG2_BIT::ACCEL_FCHOICE_B_BYPASS_DLPF, 0 }, - { Register::GYRO_CONFIG, GYRO_CONFIG_BIT::GYRO_FS_SEL_2000_DPS, GYRO_CONFIG_BIT::FCHOICE_B_8KHZ_BYPASS_DLPF }, - { Register::CONFIG, CONFIG_BIT::FIFO_MODE | CONFIG_BIT::DLPF_CFG_BYPASS_DLPF_8KHZ, 0 }, - { Register::USER_CTRL, USER_CTRL_BIT::FIFO_EN, 0 }, { Register::FIFO_EN, FIFO_EN_BIT::GYRO_XOUT | FIFO_EN_BIT::GYRO_YOUT | FIFO_EN_BIT::GYRO_ZOUT | FIFO_EN_BIT::ACCEL, 0 }, { Register::INT_PIN_CFG, INT_PIN_CFG_BIT::ACTL, 0 }, - { Register::INT_ENABLE, INT_ENABLE_BIT::RAW_RDY_EN, 0 } + { Register::INT_ENABLE, INT_ENABLE_BIT::RAW_RDY_EN, 0 }, + { Register::USER_CTRL, USER_CTRL_BIT::FIFO_EN, USER_CTRL_BIT::I2C_IF_DIS }, + { Register::PWR_MGMT_1, PWR_MGMT_1_BIT::CLKSEL_0, PWR_MGMT_1_BIT::SLEEP }, }; };