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drivers iim42652 and iim42653 disable AFSR

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This commit is contained in:
alexklimaj 2023-10-23 17:35:52 -05:00 committed by Daniel Agar
parent d882ae05c1
commit 6a849163db
6 changed files with 10 additions and 7 deletions
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2
src/drivers/imu/invensense/iim42652/IIM42652.cpp
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@ -353,7 +353,7 @@ void IIM42652::ConfigureCLKIN()
{
for (auto &r0 : _register_bank0_cfg) {
if (r0.reg == Register::BANK_0::INTF_CONFIG1) {
r0.set_bits = INTF_CONFIG1_BIT::RTC_MODE;
r0.set_bits = r0.set_bits | INTF_CONFIG1_BIT::RTC_MODE;
}
}

2
src/drivers/imu/invensense/iim42652/IIM42652.hpp
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@ -184,7 +184,7 @@ private:
// Register | Set bits, Clear bits
{ Register::BANK_0::INT_CONFIG, INT_CONFIG_BIT::INT1_MODE | INT_CONFIG_BIT::INT1_DRIVE_CIRCUIT, INT_CONFIG_BIT::INT1_POLARITY },
{ Register::BANK_0::FIFO_CONFIG, FIFO_CONFIG_BIT::FIFO_MODE_STOP_ON_FULL, 0 },
{ Register::BANK_0::INTF_CONFIG1, 0, 0}, // RTC_MODE[2] set at runtime
{ Register::BANK_0::INTF_CONFIG1, INTF_CONFIG1_BIT::AFSR_SET, INTF_CONFIG1_BIT::AFSR_CLEAR}, // RTC_MODE[2] set at runtime
{ Register::BANK_0::PWR_MGMT0, PWR_MGMT0_BIT::GYRO_MODE_LOW_NOISE | PWR_MGMT0_BIT::ACCEL_MODE_LOW_NOISE, 0 },
{ Register::BANK_0::GYRO_CONFIG0, GYRO_CONFIG0_BIT::GYRO_FS_SEL_2000_DPS | GYRO_CONFIG0_BIT::GYRO_ODR_8KHZ_SET, GYRO_CONFIG0_BIT::GYRO_ODR_8KHZ_CLEAR },
{ Register::BANK_0::ACCEL_CONFIG0, ACCEL_CONFIG0_BIT::ACCEL_FS_SEL_16G | ACCEL_CONFIG0_BIT::ACCEL_ODR_8KHZ_SET, ACCEL_CONFIG0_BIT::ACCEL_ODR_8KHZ_CLEAR },

4
src/drivers/imu/invensense/iim42652/InvenSense_IIM42652_registers.hpp
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@ -1,6 +1,6 @@
/****************************************************************************
*
* Copyright (c) 2022 PX4 Development Team. All rights reserved.
* Copyright (c) 2023 PX4 Development Team. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -159,6 +159,8 @@ enum SIGNAL_PATH_RESET_BIT : uint8_t {
};
enum INTF_CONFIG1_BIT : uint8_t {
AFSR_CLEAR = Bit7, // 10: adaptive full scale range on by default, 01: off
AFSR_SET = Bit6,
RTC_MODE = Bit2, // 0: No input RTC clock is required, 1: RTC clock input is required
CLKSEL = Bit0,
CLKSEL_CLEAR = Bit1,

5
src/drivers/imu/invensense/iim42653/IIM42653.cpp
View File

@ -353,9 +353,8 @@ void IIM42653::ConfigureCLKIN()
{
for (auto &r0 : _register_bank0_cfg) {
if (r0.reg == Register::BANK_0::INTF_CONFIG1) {
r0.set_bits = INTF_CONFIG1_BIT::RTC_MODE;
r0.set_bits = INTF_CONFIG1_BIT::CLKSEL;
r0.clear_bits = INTF_CONFIG1_BIT::CLKSEL_CLEAR;
r0.set_bits = r0.set_bits | INTF_CONFIG1_BIT::RTC_MODE | INTF_CONFIG1_BIT::CLKSEL;
r0.clear_bits = r0.clear_bits | INTF_CONFIG1_BIT::CLKSEL_CLEAR;
}
}

2
src/drivers/imu/invensense/iim42653/IIM42653.hpp
View File

@ -184,7 +184,7 @@ private:
// Register | Set bits, Clear bits
{ Register::BANK_0::INT_CONFIG, INT_CONFIG_BIT::INT1_MODE | INT_CONFIG_BIT::INT1_DRIVE_CIRCUIT, INT_CONFIG_BIT::INT1_POLARITY },
{ Register::BANK_0::FIFO_CONFIG, FIFO_CONFIG_BIT::FIFO_MODE_STOP_ON_FULL, 0 },
{ Register::BANK_0::INTF_CONFIG1, 0, 0}, // RTC_MODE[2] set at runtime
{ Register::BANK_0::INTF_CONFIG1, INTF_CONFIG1_BIT::AFSR_SET, INTF_CONFIG1_BIT::AFSR_CLEAR}, // RTC_MODE[2] set at runtime
{ Register::BANK_0::PWR_MGMT0, PWR_MGMT0_BIT::GYRO_MODE_LOW_NOISE | PWR_MGMT0_BIT::ACCEL_MODE_LOW_NOISE, 0 },
{ Register::BANK_0::GYRO_CONFIG0, GYRO_CONFIG0_BIT::GYRO_FS_SEL_4000_DPS | GYRO_CONFIG0_BIT::GYRO_ODR_8KHZ_SET, GYRO_CONFIG0_BIT::GYRO_ODR_8KHZ_CLEAR },
{ Register::BANK_0::ACCEL_CONFIG0, ACCEL_CONFIG0_BIT::ACCEL_FS_SEL_32G | ACCEL_CONFIG0_BIT::ACCEL_ODR_8KHZ_SET, ACCEL_CONFIG0_BIT::ACCEL_ODR_8KHZ_CLEAR },

2
src/drivers/imu/invensense/iim42653/InvenSense_IIM42653_registers.hpp
View File

@ -165,6 +165,8 @@ enum SIGNAL_PATH_RESET_BIT : uint8_t {
};
enum INTF_CONFIG1_BIT : uint8_t {
AFSR_CLEAR = Bit7, // 10: adaptive full scale range on by default, 01: off
AFSR_SET = Bit6,
RTC_MODE = Bit2, // 0: No input RTC clock is required, 1: RTC clock input is required
CLKSEL = Bit0,
CLKSEL_CLEAR = Bit1,