From 67437396f16f5b9aebf3798e5b984b59f57008ac Mon Sep 17 00:00:00 2001 From: Daniel Agar Date: Tue, 2 Nov 2021 19:50:54 -0400 Subject: [PATCH] mpu6000: add USER_CTRL I2C_MST_EN bit to checked registers --- .../imu/invensense/mpu6000/InvenSense_MPU6000_registers.hpp | 1 + src/drivers/imu/invensense/mpu6000/MPU6000.hpp | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/drivers/imu/invensense/mpu6000/InvenSense_MPU6000_registers.hpp b/src/drivers/imu/invensense/mpu6000/InvenSense_MPU6000_registers.hpp index 52a5a17560..768f4a3de9 100644 --- a/src/drivers/imu/invensense/mpu6000/InvenSense_MPU6000_registers.hpp +++ b/src/drivers/imu/invensense/mpu6000/InvenSense_MPU6000_registers.hpp @@ -147,6 +147,7 @@ enum SIGNAL_PATH_RESET_BIT : uint8_t { // USER_CTRL enum USER_CTRL_BIT : uint8_t { FIFO_EN = Bit6, + I2C_MST_EN = Bit5, I2C_IF_DIS = Bit4, FIFO_RESET = Bit2, SIG_COND_RESET = Bit0, diff --git a/src/drivers/imu/invensense/mpu6000/MPU6000.hpp b/src/drivers/imu/invensense/mpu6000/MPU6000.hpp index ac54452e25..c64bf47d60 100644 --- a/src/drivers/imu/invensense/mpu6000/MPU6000.hpp +++ b/src/drivers/imu/invensense/mpu6000/MPU6000.hpp @@ -163,7 +163,7 @@ private: { Register::FIFO_EN, FIFO_EN_BIT::XG_FIFO_EN | FIFO_EN_BIT::YG_FIFO_EN | FIFO_EN_BIT::ZG_FIFO_EN | FIFO_EN_BIT::ACCEL_FIFO_EN, FIFO_EN_BIT::TEMP_FIFO_EN }, { Register::INT_PIN_CFG, INT_PIN_CFG_BIT::INT_LEVEL, 0 }, { Register::INT_ENABLE, INT_ENABLE_BIT::DATA_RDY_INT_EN, 0 }, - { Register::USER_CTRL, USER_CTRL_BIT::FIFO_EN | USER_CTRL_BIT::I2C_IF_DIS, 0 }, + { Register::USER_CTRL, USER_CTRL_BIT::FIFO_EN | USER_CTRL_BIT::I2C_IF_DIS, USER_CTRL_BIT::I2C_MST_EN }, { Register::PWR_MGMT_1, PWR_MGMT_1_BIT::CLKSEL_0, PWR_MGMT_1_BIT::SLEEP }, }; };