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io timer: remove some fields from io_timers_t and split out channel indexes

Browse Source 
- reduces amount of board configuration required
- removes the cyclic dependency between io_timers_t and timer_io_channels_t

Fixes a bug in the fmuk66-v3 config: the 2. timer has 3 channels associated
not 2.
Fixes a bug in the modelai config: the 2. timer has 4 channels associated.
This commit is contained in:
Beat Küng
2020-02-13 03:49:16 -08:00
committed by David Sidrane
parent 8020e82c1c
commit 62b4f3487a
28 changed files with 581 additions and 301 deletions
Download Patch File Download Diff File Expand all files Collapse all files
boards/airmind/mindpx-v2/src/timer_config.c
+12 -6
View File
@@ -56,9 +56,6 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM1EN,
.clock_freq = STM32_APB2_TIM1_CLKIN,
.first_channel_index = 0,
.last_channel_index = 3,
.handler = io_timer_handler0,
.vectorno = STM32_IRQ_TIM1CC,
},
{
@@ -66,12 +63,21 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM4EN,
.clock_freq = STM32_APB1_TIM4_CLKIN,
.first_channel_index = 4,
.last_channel_index = 7,
.handler = io_timer_handler1,
.vectorno = STM32_IRQ_TIM4
}
};
__EXPORT const io_timers_channel_mapping_t io_timers_channel_mapping = {
.element = {
{
.first_channel_index = 0,
.channel_count = 4,
},
{
.first_channel_index = 4,
.channel_count = 4,
}
}
};
__EXPORT const timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
{
boards/av/x-v1/src/timer_config.c
+25 -18
View File
@@ -56,9 +56,6 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM1EN,
.clock_freq = STM32_APB2_TIM1_CLKIN,
.first_channel_index = 0,
.last_channel_index = 3,
.handler = io_timer_handler0,
.vectorno = STM32_IRQ_TIM1CC,
},
{
@@ -66,9 +63,6 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM2EN,
.clock_freq = STM32_APB1_TIM2_CLKIN,
.first_channel_index = 4,
.last_channel_index = 4,
.handler = io_timer_handler1,
.vectorno = STM32_IRQ_TIM2,
},
{
@@ -76,9 +70,6 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM8EN,
.clock_freq = STM32_APB2_TIM8_CLKIN,
.first_channel_index = 5,
.last_channel_index = 5,
.handler = io_timer_handler2,
.vectorno = STM32_IRQ_TIM8CC,
},
{
@@ -86,9 +77,6 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM11EN,
.clock_freq = STM32_APB2_TIM11_CLKIN,
.first_channel_index = 6,
.last_channel_index = 6,
.handler = io_timer_handler3,
.vectorno = STM32_IRQ_TIM11,
},
{
@@ -96,9 +84,6 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM10EN,
.clock_freq = STM32_APB2_TIM10_CLKIN,
.first_channel_index = 7,
.last_channel_index = 7,
.handler = io_timer_handler4,
.vectorno = STM32_IRQ_TIM10,
},
// {
@@ -106,13 +91,35 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
// .clock_register = STM32_RCC_APB1ENR,
// .clock_bit = RCC_APB1ENR_TIM4EN,
// .clock_freq = STM32_APB1_TIM4_CLKIN,
// .first_channel_index = 8,
// .last_channel_index = 8,
// .handler = io_timer_handler5,
// .vectorno = STM32_IRQ_TIM4,
// }
};
__EXPORT const io_timers_channel_mapping_t io_timers_channel_mapping = {
.element = {
{
.first_channel_index = 0,
.channel_count = 4,
},
{
.first_channel_index = 4,
.channel_count = 1,
},
{
.first_channel_index = 5,
.channel_count = 1,
},
{
.first_channel_index = 6,
.channel_count = 1,
},
{
.first_channel_index = 7,
.channel_count = 1,
},
}
};
__EXPORT const timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
{
.gpio_out = GPIO_TIM1_CH1OUT,
boards/bitcraze/crazyflie/src/timer_config.c
+12 -6
View File
@@ -65,9 +65,6 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM2EN,
.clock_freq = TIM2_CLKIN,
.first_channel_index = 0,
.last_channel_index = 2,
.handler = io_timer_handler0,
.vectorno = STM32_IRQ_TIM2,
},
{
@@ -75,12 +72,21 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM4EN,
.clock_freq = TIM4_CLKIN,
.first_channel_index = 3,
.last_channel_index = 3,
.handler = io_timer_handler1,
.vectorno = STM32_IRQ_TIM4,
}
};
__EXPORT const io_timers_channel_mapping_t io_timers_channel_mapping = {
.element = {
{
.first_channel_index = 0,
.channel_count = 3,
},
{
.first_channel_index = 3,
.channel_count = 1,
}
}
};
__EXPORT const timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
{
boards/holybro/durandal-v1/src/timer_config.c
+13 -10
View File
@@ -56,15 +56,10 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM1EN,
.clock_freq = STM32_APB2_TIM1_CLKIN,
.first_channel_index = 0,
.last_channel_index = 3,
.handler = io_timer_handler0,
.vectorno = STM32_IRQ_TIMCC,
.dshot = {
.dma_base = STM32_DMA1_BASE,
.dmamap = DMAMAP_DMA12_TIM1UP_0,
.start_ccr_register = TIM_DMABASE_CCR1,
.channels_number = 4u /* CCR1, CCR2, CCR3 and CCR4 */
}
},
{
@@ -72,19 +67,27 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1LENR,
.clock_bit = RCC_APB1LENR_TIM4EN,
.clock_freq = STM32_APB1_TIM4_CLKIN,
.first_channel_index = 4,
.last_channel_index = 4,
.handler = io_timer_handler1,
.vectorno = STM32_IRQ_TIM4,
.dshot = {
.dma_base = STM32_DMA1_BASE,
.dmamap = DMAMAP_DMA12_TIM4UP_0,
.start_ccr_register = TIM_DMABASE_CCR2,
.channels_number = 1u /* CCR2 */
}
},
};
__EXPORT const io_timers_channel_mapping_t io_timers_channel_mapping = {
.element = {
{
.first_channel_index = 0,
.channel_count = 4,
},
{
.first_channel_index = 4,
.channel_count = 1,
}
}
};
__EXPORT const timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
{
.gpio_out = GPIO_TIM1_CH4OUT,
boards/holybro/kakutef7/src/timer_config.c
+21 -20
View File
@@ -56,15 +56,10 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM3EN,
.clock_freq = STM32_APB1_TIM3_CLKIN,
.first_channel_index = 0,
.last_channel_index = 1,
.handler = io_timer_handler0,
.vectorno = STM32_IRQ_TIM3,
.dshot = {
.dma_base = STM32_DMA1_BASE,
.dmamap = DMAMAP_TIM3_UP,
.start_ccr_register = TIM_DMABASE_CCR3,
.channels_number = 2u /* CCR3 and CCR4 */
}
},
{
@@ -72,15 +67,10 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM1EN,
.clock_freq = STM32_APB2_TIM1_CLKIN,
.first_channel_index = 2,
.last_channel_index = 3,
.handler = io_timer_handler1,
.vectorno = STM32_IRQ_TIM1CC,
.dshot = {
.dma_base = STM32_DMA2_BASE,
.dmamap = DMAMAP_TIM1_UP,
.start_ccr_register = TIM_DMABASE_CCR1,
.channels_number = 2u /* CCR1 and CCR2 */
}
},
{
@@ -88,15 +78,10 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM8EN,
.clock_freq = STM32_APB2_TIM8_CLKIN,
.first_channel_index = 4,
.last_channel_index = 4,
.handler = io_timer_handler2,
.vectorno = STM32_IRQ_TIM8CC,
.dshot = {
.dma_base = STM32_DMA2_BASE,
.dmamap = DMAMAP_TIM8_UP,
.start_ccr_register = TIM_DMABASE_CCR4,
.channels_number = 1u /* CCR4 */
}
},
{
@@ -104,19 +89,35 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM5EN,
.clock_freq = STM32_APB1_TIM5_CLKIN,
.first_channel_index = 5,
.last_channel_index = 5,
.handler = io_timer_handler3,
.vectorno = STM32_IRQ_TIM5,
.dshot = {
.dma_base = STM32_DMA1_BASE,
.dmamap = DMAMAP_TIM5_UP_2,
.start_ccr_register = TIM_DMABASE_CCR4,
.channels_number = 1u /* CCR4 */
}
}
};
__EXPORT const io_timers_channel_mapping_t io_timers_channel_mapping = {
.element = {
{
.first_channel_index = 0,
.channel_count = 2,
},
{
.first_channel_index = 2,
.channel_count = 2,
},
{
.first_channel_index = 4,
.channel_count = 1,
},
{
.first_channel_index = 5,
.channel_count = 1,
},
}
};
__EXPORT const timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
{
.gpio_out = GPIO_TIM3_CH3OUT,
boards/intel/aerofc-v1/src/timer_config.c
+2
View File
@@ -58,6 +58,8 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = { };
// Invalidate all channels (timer_channel == 0): we don't have any
__EXPORT const timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = { };
__EXPORT const io_timers_channel_mapping_t io_timers_channel_mapping = { };
// Invalidate all timers (base == 0): we don't have any
__EXPORT const struct io_timers_t led_pwm_timers[MAX_LED_TIMERS] = { };
boards/modalai/fc-v1/src/timer_config.c
+13 -8
View File
@@ -71,15 +71,10 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM1EN,
.clock_freq = STM32_APB2_TIM1_CLKIN,
.first_channel_index = 0,
.last_channel_index = 3,
.handler = io_timer_handler0,
.vectorno = STM32_IRQ_TIM1CC,
.dshot = {
.dma_base = STM32_DMA2_BASE,
.dmamap = DMAMAP_TIM1_UP,
.start_ccr_register = TIM_DMABASE_CCR1,
.channels_number = 4u /* CCR1, CCR2, CCR3 and CCR4 */
}
},
{
@@ -87,13 +82,23 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM4EN,
.clock_freq = STM32_APB1_TIM4_CLKIN,
.first_channel_index = 4,
.last_channel_index = 5,
.handler = io_timer_handler1,
.vectorno = STM32_IRQ_TIM4,
}
};
__EXPORT const io_timers_channel_mapping_t io_timers_channel_mapping = {
.element = {
{
.first_channel_index = 0,
.channel_count = 4,
},
{
.first_channel_index = 4,
.channel_count = 4,
}
}
};
__EXPORT const timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
{
.gpio_out = GPIO_TIM1_CH4OUT,
boards/mro/ctrl-zero-f7/src/timer_config.c
+17 -9
View File
@@ -56,9 +56,6 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM1EN,
.clock_freq = STM32_APB2_TIM1_CLKIN,
.first_channel_index = 0,
.last_channel_index = 3,
.handler = io_timer_handler0,
.vectorno = STM32_IRQ_TIM1CC,
},
{
@@ -66,9 +63,6 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM4EN,
.clock_freq = STM32_APB1_TIM4_CLKIN,
.first_channel_index = 4,
.last_channel_index = 5,
.handler = io_timer_handler1,
.vectorno = STM32_IRQ_TIM4,
},
{
@@ -76,13 +70,27 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM8EN,
.clock_freq = STM32_APB2_TIM8_CLKIN,
.first_channel_index = 6,
.last_channel_index = 7,
.handler = io_timer_handler2,
.vectorno = STM32_IRQ_TIM8UP,
}
};
__EXPORT const io_timers_channel_mapping_t io_timers_channel_mapping = {
.element = {
{
.first_channel_index = 0,
.channel_count = 4,
},
{
.first_channel_index = 4,
.channel_count = 2,
},
{
.first_channel_index = 6,
.channel_count = 2,
},
}
};
__EXPORT const timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
{
.gpio_out = GPIO_TIM1_CH4OUT,
boards/mro/x21-777/src/timer_config.c
+13 -6
View File
@@ -56,9 +56,6 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM1EN,
.clock_freq = STM32_APB2_TIM1_CLKIN,
.first_channel_index = 0,
.last_channel_index = 3,
.handler = io_timer_handler0,
.vectorno = STM32_IRQ_TIM1CC,
},
{
@@ -66,13 +63,23 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM4EN,
.clock_freq = STM32_APB1_TIM4_CLKIN,
.first_channel_index = 4,
.last_channel_index = 5,
.handler = io_timer_handler1,
.vectorno = STM32_IRQ_TIM4
}
};
__EXPORT const io_timers_channel_mapping_t io_timers_channel_mapping = {
.element = {
{
.first_channel_index = 0,
.channel_count = 4,
},
{
.first_channel_index = 4,
.channel_count = 2,
}
}
};
__EXPORT const timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
{
.gpio_out = GPIO_TIM1_CH4OUT,
boards/mro/x21/src/timer_config.c
+13 -6
View File
@@ -56,9 +56,6 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM1EN,
.clock_freq = STM32_APB2_TIM1_CLKIN,
.first_channel_index = 0,
.last_channel_index = 3,
.handler = io_timer_handler0,
.vectorno = STM32_IRQ_TIM1CC,
},
@@ -67,13 +64,23 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM4EN,
.clock_freq = STM32_APB1_TIM4_CLKIN,
.first_channel_index = 4,
.last_channel_index = 5,
.handler = io_timer_handler1,
.vectorno = STM32_IRQ_TIM4
}
};
__EXPORT const io_timers_channel_mapping_t io_timers_channel_mapping = {
.element = {
{
.first_channel_index = 0,
.channel_count = 4,
},
{
.first_channel_index = 4,
.channel_count = 2,
}
}
};
__EXPORT const timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
{
.gpio_out = GPIO_TIM1_CH4OUT,
boards/nxp/fmuk66-v3/src/timer_config.c
+17 -11
View File
@@ -56,9 +56,6 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.base = KINETIS_FTM0_BASE,
.clock_register = KINETIS_SIM_SCGC6,
.clock_bit = SIM_SCGC6_FTM0,
.first_channel_index = 0,
.last_channel_index = 3,
.handler = io_timer_handler0,
.vectorno = KINETIS_IRQ_FTM0,
},
@@ -66,22 +63,33 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.base = KINETIS_FTM3_BASE,
.clock_register = KINETIS_SIM_SCGC3,
.clock_bit = SIM_SCGC3_FTM3,
.first_channel_index = 4,
.last_channel_index = 5,
.handler = io_timer_handler1,
.vectorno = KINETIS_IRQ_FTM3,
},
{
.base = KINETIS_FTM2_BASE,
.clock_register = KINETIS_SIM_SCGC3,
.clock_bit = SIM_SCGC3_FTM2,
.first_channel_index = 6,
.last_channel_index = 7,
.handler = io_timer_handler2,
.vectorno = KINETIS_IRQ_FTM2,
}
};
__EXPORT const io_timers_channel_mapping_t io_timers_channel_mapping = {
.element = {
{
.first_channel_index = 0,
.channel_count = 4,
},
{
.first_channel_index = 4,
.channel_count = 3,
},
{
.first_channel_index = 6,
.channel_count = 1,
}
}
};
__EXPORT const timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
{
.gpio_out = GPIO_FTM0_CH0OUT, // FMU_CH1
@@ -138,8 +146,6 @@ __EXPORT const struct io_timers_t led_pwm_timers[MAX_LED_TIMERS] = {
.base = KINETIS_FTM3_BASE,
.clock_register = KINETIS_SIM_SCGC3,
.clock_bit = SIM_SCGC3_FTM3,
.first_channel_index = 0,
.last_channel_index = 2,
.vectorno = 0,
},
};
boards/omnibus/f4sd/src/timer_config.c
+14 -10
View File
@@ -56,15 +56,10 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM2EN,
.clock_freq = STM32_APB1_TIM2_CLKIN,
.first_channel_index = 0,
.last_channel_index = 1,
.handler = io_timer_handler1,
.vectorno = STM32_IRQ_TIM2,
.dshot = {
.dma_base = STM32_DMA1_BASE,
.dmamap = DMAMAP_TIM2_UP_1,
.start_ccr_register = TIM_DMABASE_CCR3,
.channels_number = 2u /* CCR3 and CCR4 */
}
},
{
@@ -72,19 +67,28 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM3EN,
.clock_freq = STM32_APB1_TIM3_CLKIN,
.first_channel_index = 2,
.last_channel_index = 3,
.handler = io_timer_handler2,
.vectorno = STM32_IRQ_TIM3,
.dshot = {
.dma_base = STM32_DMA1_BASE,
.dmamap = DMAMAP_TIM3_UP,
.start_ccr_register = TIM_DMABASE_CCR3,
.channels_number = 2u /* CCR3 and CCR4 */
}
}
};
__EXPORT const io_timers_channel_mapping_t io_timers_channel_mapping = {
.element = {
{
.first_channel_index = 0,
.channel_count = 2,
},
{
.first_channel_index = 2,
.channel_count = 2,
}
}
};
/*
* OUTPUTS:
* M3 : PA3 : TIM2_CH3
boards/px4/fmu-v2/src/timer_config.c
+13 -10
View File
@@ -56,15 +56,10 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM1EN,
.clock_freq = STM32_APB2_TIM1_CLKIN,
.first_channel_index = 0,
.last_channel_index = 3,
.handler = io_timer_handler0,
.vectorno = STM32_IRQ_TIM1CC,
.dshot = {
.dma_base = STM32_DMA2_BASE,
.dmamap = DMAMAP_TIM1_UP,
.start_ccr_register = TIM_DMABASE_CCR1,
.channels_number = 4u /* CCR1, CCR2, CCR3 and CCR4 */
}
},
{
@@ -72,15 +67,23 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM4EN,
.clock_freq = STM32_APB1_TIM4_CLKIN,
.first_channel_index = 4,
.last_channel_index = 5,
.handler = io_timer_handler1,
.vectorno = STM32_IRQ_TIM4,
.dshot = {
.dma_base = STM32_DMA1_BASE,
.dmamap = DMAMAP_TIM4_UP,
.start_ccr_register = TIM_DMABASE_CCR2,
.channels_number = 2u /* CCR2 and CCR3 */
}
}
};
__EXPORT const io_timers_channel_mapping_t io_timers_channel_mapping = {
.element = {
{
.first_channel_index = 0,
.channel_count = 4,
},
{
.first_channel_index = 4,
.channel_count = 2,
}
}
};
boards/px4/fmu-v3/src/timer_config.c
+13 -10
View File
@@ -56,15 +56,10 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM1EN,
.clock_freq = STM32_APB2_TIM1_CLKIN,
.first_channel_index = 0,
.last_channel_index = 3,
.handler = io_timer_handler0,
.vectorno = STM32_IRQ_TIM1CC,
.dshot = {
.dma_base = STM32_DMA2_BASE,
.dmamap = DMAMAP_TIM1_UP,
.start_ccr_register = TIM_DMABASE_CCR1,
.channels_number = 4u /* CCR1, CCR2, CCR3 and CCR4 */
}
},
{
@@ -72,15 +67,23 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM4EN,
.clock_freq = STM32_APB1_TIM4_CLKIN,
.first_channel_index = 4,
.last_channel_index = 5,
.handler = io_timer_handler1,
.vectorno = STM32_IRQ_TIM4,
.dshot = {
.dma_base = STM32_DMA1_BASE,
.dmamap = DMAMAP_TIM4_UP,
.start_ccr_register = TIM_DMABASE_CCR2,
.channels_number = 2u /* CCR2 and CCR3 */
}
}
};
__EXPORT const io_timers_channel_mapping_t io_timers_channel_mapping = {
.element = {
{
.first_channel_index = 0,
.channel_count = 4,
},
{
.first_channel_index = 4,
.channel_count = 2,
}
}
};
boards/px4/fmu-v4/src/timer_config.c
+13 -10
View File
@@ -56,15 +56,10 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM1EN,
.clock_freq = STM32_APB2_TIM1_CLKIN,
.first_channel_index = 0,
.last_channel_index = 3,
.handler = io_timer_handler0,
.vectorno = STM32_IRQ_TIM1CC,
.dshot = {
.dma_base = STM32_DMA2_BASE,
.dmamap = DMAMAP_TIM1_UP,
.start_ccr_register = TIM_DMABASE_CCR1,
.channels_number = 4u /* CCR1, CCR2, CCR3 and CCR4 */
}
},
@@ -73,20 +68,28 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM4EN,
.clock_freq = STM32_APB1_TIM4_CLKIN,
.first_channel_index = 4,
.last_channel_index = 5,
.handler = io_timer_handler1,
.vectorno = STM32_IRQ_TIM4,
.dshot = {
.dma_base = STM32_DMA1_BASE,
.dmamap = DMAMAP_TIM4_UP,
.start_ccr_register = TIM_DMABASE_CCR2,
.channels_number = 2u // CCR2 and CCR3
}
}
};
__EXPORT const io_timers_channel_mapping_t io_timers_channel_mapping = {
.element = {
{
.first_channel_index = 0,
.channel_count = 4,
},
{
.first_channel_index = 4,
.channel_count = 2,
}
}
};
__EXPORT const timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
{
.gpio_out = GPIO_TIM1_CH4OUT,
boards/px4/fmu-v4pro/src/timer_config.c
+13 -6
View File
@@ -56,9 +56,6 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM1EN,
.clock_freq = STM32_APB2_TIM1_CLKIN,
.first_channel_index = 0,
.last_channel_index = 3,
.handler = io_timer_handler0,
.vectorno = STM32_IRQ_TIM1CC,
},
@@ -67,13 +64,23 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM4EN,
.clock_freq = STM32_APB1_TIM4_CLKIN,
.first_channel_index = 4,
.last_channel_index = 5,
.handler = io_timer_handler1,
.vectorno = STM32_IRQ_TIM4,
}
};
__EXPORT const io_timers_channel_mapping_t io_timers_channel_mapping = {
.element = {
{
.first_channel_index = 0,
.channel_count = 4,
},
{
.first_channel_index = 4,
.channel_count = 2,
}
}
};
__EXPORT const timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
{
.gpio_out = GPIO_TIM1_CH4OUT,
boards/px4/fmu-v5/src/timer_config.c
+25 -26
View File
@@ -56,15 +56,10 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM1EN,
.clock_freq = STM32_APB2_TIM1_CLKIN,
.first_channel_index = 0,
.last_channel_index = 3,
.handler = io_timer_handler0,
.vectorno = STM32_IRQ_TIM1CC,
.dshot = {
.dma_base = STM32_DMA2_BASE,
.dmamap = DMAMAP_TIM1_UP,
.start_ccr_register = TIM_DMABASE_CCR1,
.channels_number = 4u /* CCR1, CCR2, CCR3 and CCR4 */
}
},
{
@@ -72,9 +67,6 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM4EN,
.clock_freq = STM32_APB1_TIM4_CLKIN,
.first_channel_index = 4,
.last_channel_index = 5,
.handler = io_timer_handler1,
.vectorno = STM32_IRQ_TIM4,
},
{
@@ -82,9 +74,6 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM12EN,
.clock_freq = STM32_APB1_TIM12_CLKIN,
.first_channel_index = 6,
.last_channel_index = 7,
.handler = io_timer_handler2,
.vectorno = STM32_IRQ_TIM12,
},
{
@@ -92,9 +81,6 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM2EN,
.clock_freq = STM32_APB1_TIM2_CLKIN,
.first_channel_index = 8,
.last_channel_index = 10,
.handler = io_timer_handler3,
.vectorno = STM32_IRQ_TIM2,
},
{
@@ -102,13 +88,35 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM9EN,
.clock_freq = STM32_APB2_TIM9_CLKIN,
.first_channel_index = 11,
.last_channel_index = 11,
.handler = io_timer_handler4,
.vectorno = STM32_IRQ_TIM9,
}
};
__EXPORT const io_timers_channel_mapping_t io_timers_channel_mapping = {
.element = {
{
.first_channel_index = 0,
.channel_count = 4,
},
{
.first_channel_index = 4,
.channel_count = 2,
},
{
.first_channel_index = 6,
.channel_count = 2,
},
{
.first_channel_index = 8,
.channel_count = 3,
},
{
.first_channel_index = 11,
.channel_count = 1,
}
}
};
__EXPORT const timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
{
.gpio_out = GPIO_TIM1_CH4OUT,
@@ -185,8 +193,6 @@ __EXPORT const struct io_timers_t led_pwm_timers[MAX_LED_TIMERS] = {
.clock_bit = RCC_APB1ENR_TIM5EN,
.clock_freq = STM32_APB1_TIM5_CLKIN,
.vectorno = 0,
.first_channel_index = 0,
.last_channel_index = 2,
},
# endif
# if defined(BOARD_HAS_LED_PWM) && !defined(BOARD_HAS_CONTROL_STATUS_LEDS)
@@ -196,13 +202,6 @@ __EXPORT const struct io_timers_t led_pwm_timers[MAX_LED_TIMERS] = {
.clock_bit = RCC_APB1ENR_TIM3EN,
.clock_freq = STM32_APB1_TIM3_CLKIN,
.vectorno = 0,
# if defined(BOARD_HAS_UI_LED_PWM)
.first_channel_index = 3,
.last_channel_index = 5,
# else
.first_channel_index = 0,
.last_channel_index = 2,
# endif
},
# endif
};
boards/px4/fmu-v5x/src/timer_config.c
+25 -19
View File
@@ -79,15 +79,10 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM1EN,
.clock_freq = STM32_APB2_TIM1_CLKIN,
.first_channel_index = 0,
.last_channel_index = 3,
.handler = io_timer_handler0,
.vectorno = STM32_IRQ_TIM1CC,
.dshot = {
.dma_base = STM32_DMA2_BASE,
.dmamap = DMAMAP_TIM1_UP,
.start_ccr_register = TIM_DMABASE_CCR1,
.channels_number = 4u /* CCR1, CCR2, CCR3 and CCR4 */
}
},
{
@@ -95,15 +90,10 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM4EN,
.clock_freq = STM32_APB1_TIM4_CLKIN,
.first_channel_index = 4,
.last_channel_index = 5,
.handler = io_timer_handler1,
.vectorno = STM32_IRQ_TIM4,
.dshot = {
.dma_base = STM32_DMA1_BASE,
.dmamap = DMAMAP_TIM4_UP,
.start_ccr_register = TIM_DMABASE_CCR2,
.channels_number = 2u /* CCR2 and CCR3 */
}
},
{
@@ -111,9 +101,6 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM12EN,
.clock_freq = STM32_APB1_TIM12_CLKIN,
.first_channel_index = 6,
.last_channel_index = 7,
.handler = io_timer_handler2,
.vectorno = STM32_IRQ_TIM12,
},
{
@@ -121,9 +108,6 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM5EN,
.clock_freq = STM32_APB1_TIM5_CLKIN,
.first_channel_index = 8,
.last_channel_index = 10,
.handler = io_timer_handler3,
.vectorno = STM32_IRQ_TIM5,
},
{
@@ -131,13 +115,35 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM2EN,
.clock_freq = STM32_APB1_TIM2_CLKIN,
.first_channel_index = 11,
.last_channel_index = 11,
.handler = io_timer_handler4,
.vectorno = STM32_IRQ_TIM2,
},
};
__EXPORT const io_timers_channel_mapping_t io_timers_channel_mapping = {
.element = {
{
.first_channel_index = 0,
.channel_count = 4,
},
{
.first_channel_index = 4,
.channel_count = 2,
},
{
.first_channel_index = 6,
.channel_count = 2,
},
{
.first_channel_index = 8,
.channel_count = 3,
},
{
.first_channel_index = 11,
.channel_count = 1,
}
}
};
__EXPORT const timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
{
.gpio_out = GPIO_TIM1_CH4OUT,
boards/px4/io-v2/src/timer_config.c
+17 -9
View File
@@ -56,9 +56,6 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM2EN,
.clock_freq = STM32_APB1_TIM2_CLKIN,
.first_channel_index = 0,
.last_channel_index = 1,
.handler = io_timer_handler0,
.vectorno = STM32_IRQ_TIM2,
},
{
@@ -66,9 +63,6 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM3EN,
.clock_freq = STM32_APB1_TIM3_CLKIN,
.first_channel_index = 4,
.last_channel_index = 7,
.handler = io_timer_handler1,
.vectorno = STM32_IRQ_TIM3,
},
{
@@ -76,13 +70,27 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM4EN,
.clock_freq = STM32_APB1_TIM4_CLKIN,
.first_channel_index = 2,
.last_channel_index = 3,
.handler = io_timer_handler2,
.vectorno = STM32_IRQ_TIM4,
}
};
__EXPORT const io_timers_channel_mapping_t io_timers_channel_mapping = {
.element = {
{
.first_channel_index = 0,
.channel_count = 2,
},
{
.first_channel_index = 4,
.channel_count = 4,
},
{
.first_channel_index = 2,
.channel_count = 2,
}
}
};
__EXPORT const timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
{
.gpio_out = GPIO_TIM2_CH1OUT,
boards/uvify/core/src/timer_config.c
+13 -10
View File
@@ -56,15 +56,10 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB2ENR,
.clock_bit = RCC_APB2ENR_TIM1EN,
.clock_freq = STM32_APB2_TIM1_CLKIN,
.first_channel_index = 0,
.last_channel_index = 3,
.handler = io_timer_handler0,
.vectorno = STM32_IRQ_TIM1CC,
.dshot = {
.dma_base = STM32_DMA2_BASE,
.dmamap = DMAMAP_TIM1_UP,
.start_ccr_register = TIM_DMABASE_CCR1,
.channels_number = 4u /* CCR1, CCR2, CCR3 and CCR4 */
}
},
@@ -73,20 +68,28 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.clock_register = STM32_RCC_APB1ENR,
.clock_bit = RCC_APB1ENR_TIM4EN,
.clock_freq = STM32_APB1_TIM4_CLKIN,
.first_channel_index = 4,
.last_channel_index = 5,
.handler = io_timer_handler1,
.vectorno = STM32_IRQ_TIM4,
.dshot = {
.dma_base = STM32_DMA1_BASE,
.dmamap = DMAMAP_TIM4_UP,
.start_ccr_register = TIM_DMABASE_CCR2,
.channels_number = 2u // CCR2 and CCR3
}
}
};
__EXPORT const io_timers_channel_mapping_t io_timers_channel_mapping = {
.element = {
{
.first_channel_index = 0,
.channel_count = 4,
},
{
.first_channel_index = 4,
.channel_count = 2,
}
}
};
__EXPORT const timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
{
.gpio_out = GPIO_TIM1_CH4OUT,