diff --git a/apps/ChangeLog.txt b/apps/ChangeLog.txt index e098099155..d24494f54a 100644 --- a/apps/ChangeLog.txt +++ b/apps/ChangeLog.txt @@ -336,3 +336,12 @@ can now be used to limit the server to a single thread. Option CONFIG_NETUTILS_HTTPD_TIMEOUT can be used to generate HTTP 408 errors. Both from Kate. + * apps/netutils/webserver/httpd.c: Improvements to HTTP parser from + Kate. + * apps/netutils/webserver/httpd.c: Add support for Keep-alive connections + (from Kate). + * apps/NxWidget/Kconfig: This is a kludge. I created this NxWidgets + directory that ONLY contains Kconfig. NxWidgets does not like in + either the nuttx/ or the apps/ source trees. This kludge makes it + possible to configure NxWidgets/NxWM without too much trouble (with + the tradeoff being a kind ugly structure and some maintenance issues). diff --git a/apps/Kconfig b/apps/Kconfig index 1f38c58baf..5543ba72dd 100644 --- a/apps/Kconfig +++ b/apps/Kconfig @@ -27,6 +27,10 @@ menu "NSH Library" source "$APPSDIR/nshlib/Kconfig" endmenu +menu "NxWidgets/NxWM" +source "$APPSDIR/NxWidgets/Kconfig" +endmenu + menu "System NSH Add-Ons" source "$APPSDIR/system/Kconfig" endmenu diff --git a/nuttx/ChangeLog b/nuttx/ChangeLog index 7ad830d890..adb52afce7 100644 --- a/nuttx/ChangeLog +++ b/nuttx/ChangeLog @@ -3377,3 +3377,46 @@ commands used in the build (Contributed by Richard Cochran). * drivers/net/enc28j60.c: The ENC28J60 Ethernet driver is now functional. + * configs/fire-stm32v2: Add support or the fire-stm32v3 board as + well (untested because I do not have a v3 board). + * lib/stdio/lib_sscanf.c: Add %n psuedo-format (from Kate). + * lib/stdio/lib_sscanf.c: There is an issue of handling input + when (1) no fieldwidth is provided and (2) there is no space + seperating the input values. No solutions is in place for this + case now (either space or a fieldwidth must be provided). But + at least some of the bad logic that attempted to handle this + case has been removed (noted by Kate). + * arch/arm/src/stm32/stm32_eth.c: DMA buffer sizes must be an + even multiple of 4, 8, or 16 bytes. + * arch/arm/src/stm32/stm32_idle.c: Fixes STM32F107 DMA issues: + We cannot go into sleep mode while Ethernet is actively DMAing. + * configs/shenzhou/src/up_ssd1289.c: Add infrastructure to support + SSD1289 LCD. Initial checkin is just a clone of the + STM32F4Discovery's FSMC-based LCD interface. The Shenzhou + will need a completely need bit-banging interface; this + initial check-in is only for the framework. + * configs/shenzhou/src/up_ssd1289.c: Bit-banging driver is + code complete. + * configs/shenzhou/src/up_lcd.c: Oops. Shenzhou LCD does not + have an SSD1289 controller. Its an ILI93xx. Ported the + STM3240G-EVAL ILI93xx driver to work on the Shenzhou board. + * configs/shenzhou/nxwm: Added an NxWM configuratino for the + Shenzhou board. This is untested on initial check-in. It will + be used to verify the Shenzhou LCD driver (and eventually the + touchscreen driver). + * configs/shenzhou/src/up_touchscreen.c: Add ADS7843E touchscreen + support for the Shenzhou board. The initial check-in is untested + and basically a clone of the the touchscreen support fro the SAM-3U. + * tools/cfgparser.c: There are some NxWidget configuration + settings that must be de-quoted. + * arch/arm/src/stm32/Kconfig: There is no SPI4. Some platforms + SPI3 and some do not (still not clear). + * nuttx/configs/shenzhou: Various fixes to build new NxWM + configuration. + * configs/shenzhou: Oops. The Shenzhou LCD is and SSD1289, + not an ILI93xx. + * configs/shenzhou/src/up_ssd1289.c: The LCD is basically functional + on the Shenzhou board. + * graphics/nxmu: Correct some bad parameter checking that caused + failures when DEBUG was enabled. + diff --git a/nuttx/Kconfig b/nuttx/Kconfig index f920e4984d..0fe6eb0f7c 100644 --- a/nuttx/Kconfig +++ b/nuttx/Kconfig @@ -216,7 +216,7 @@ endmenu menu "Debug Options" config DEBUG - bool "Enable debug features" + bool "Enable Debug Features" default n ---help--- Enables built-in debug features. Selecting this option will (1) Enable @@ -227,87 +227,115 @@ config DEBUG if DEBUG config DEBUG_VERBOSE - bool "Enable debug verbose output" + bool "Enable Debug Verbose Output" default n ---help--- - Enables verbose debug output (assuming debug output is enabled) + Enables verbose debug output (assuming debug output is enabled). As a + general rule, when DEBUG is enabled only errors will be reported in the debug + output. But if you also enable DEBUG_VERBOSE, then very chatty (and + often annoying) output will be generated. This means there are two levels + of debug output: errors-only and everything. config DEBUG_ENABLE - bool "Enable debug controls" + bool "Enable Debug Controls" default n ---help--- Support an interface to dynamically enable or disable debug output. +comment "Subsystem Debug Options" + config DEBUG_SCHED - bool "Enable scheduler debug output" + bool "Enable Scheduler Debug Output" default n ---help--- Enable OS debug output (disabled by default) config DEBUG_MM - bool "Enable memory manager debug output" + bool "Enable Memory Manager Debug Output" default n ---help--- Enable memory management debug output (disabled by default) config DEBUG_NET - bool "Enable network debug output" + bool "Enable Network Debug Output" default n + depends on NET ---help--- Enable network debug output (disabled by default) config DEBUG_USB - bool "Enable USB debug output" + bool "Enable USB Debug Output" default n + depends on USBDEV || USBHOST ---help--- Enable usb debug output (disabled by default) config DEBUG_FS - bool "Enable file system debug output" + bool "Enable File System Debug Output" default n ---help--- Enable file system debug output (disabled by default) config DEBUG_LIB - bool "Enable C library debug output" + bool "Enable C Library Debug Output" default n ---help--- Enable C library debug output (disabled by default) config DEBUG_BINFMT - bool "Enable binary loader debug output" + bool "Enable Binary Loader Debug Output" default n ---help--- Enable binary loader debug output (disabled by default) config DEBUG_GRAPHICS - bool "Enable graphics debug output" + bool "Enable Graphics Debug Output" default n ---help--- Enable NX graphics debug output (disabled by default) -config DEBUG_I2C - bool "Enable I2C debug output" +comment "Driver Debug Options" + +config DEBUG_LCD + bool "Enable Low-level LCD Debug Output" default n + depends on LCD + ---help--- + Enable low level debug output from the LCD driver (disabled by default) + +config DEBUG_INPUT + bool "Enable Input Device Debug Output" + default n + depends on INPUT + ---help--- + Enable low level debug output from the input device drivers such as + mice and touchscreens (disabled by default) + +config DEBUG_I2C + bool "Enable I2C Debug Output" + default n + depends on I2C ---help--- Enable I2C driver debug output (disabled by default) config DEBUG_SPI - bool "Enable SPI debug output" + bool "Enable SPI Debug Output" default n + depends on SPI ---help--- Enable I2C driver debug output (disabled by default) config DEBUG_WATCHDOG - bool "Enable watchdog timer debug output" + bool "Enable Watchdog Timer Debug Output" default n + depends on WATCHDOG ---help--- Enable watchdog timer debug output (disabled by default) endif config DEBUG_SYMBOLS - bool "Enable debug symbols" + bool "Enable Debug Symbols" default n ---help--- Build without optimization and with debug symbols (needed @@ -339,6 +367,10 @@ menu "File Systems" source fs/Kconfig endmenu +menu "Graphics Support" +source graphics/Kconfig +endmenu + menu "Memory Management" source mm/Kconfig endmenu diff --git a/nuttx/Makefile b/nuttx/Makefile index 3c6e9c1985..7a058d88e9 100644 --- a/nuttx/Makefile +++ b/nuttx/Makefile @@ -38,7 +38,8 @@ TOPDIR := ${shell pwd | sed -e 's/ /\\ /g'} -include ${TOPDIR}/tools/Config.mk -include ${TOPDIR}/Make.defs -# Control build verbosity. +# Control build verbosity + ifeq ($(V),1) export Q := else diff --git a/nuttx/README.txt b/nuttx/README.txt index 5c330aa683..7477e0a245 100644 --- a/nuttx/README.txt +++ b/nuttx/README.txt @@ -848,6 +848,8 @@ apps | `- README.txt |- nshlib/ | `- README.txt + |- NxWidgets/ + | `- README.txt |- system/ | |- i2c/README.txt | |- free/README.txt diff --git a/nuttx/arch/arm/src/stm32/Kconfig b/nuttx/arch/arm/src/stm32/Kconfig index 8b0cea32e4..8d93fb104c 100644 --- a/nuttx/arch/arm/src/stm32/Kconfig +++ b/nuttx/arch/arm/src/stm32/Kconfig @@ -340,14 +340,7 @@ config STM32_SPI2 config STM32_SPI3 bool "SPI3" default n - depends on STM32_STM32F20XX || STM32_STM32F40XX - select SPI - select STM32_SPI - -config STM32_SPI4 - bool "SPI4" - default n - depends on STM32_STM32F10XX + depends on STM32_CONNECTIVITYLINE || STM32_STM32F20XX || STM32_STM32F40XX select SPI select STM32_SPI @@ -1623,12 +1616,12 @@ config STM32_I2C_DYNTIMEO config STM32_I2C_DYNTIMEO_USECPERBYTE int "Timeout Microseconds per Byte" - default 0 + default 500 depends on STM32_I2C_DYNTIMEO config STM32_I2C_DYNTIMEO_STARTSTOP int "Timeout for Start/Stop (Milliseconds)" - default 5000 + default 1000 depends on STM32_I2C_DYNTIMEO config STM32_I2CTIMEOSEC @@ -1684,6 +1677,7 @@ config SDIO_WIDTH_D1_ONLY endmenu +if STM32_ETHMAC menu "Ethernet MAC configuration" config STM32_PHYADDR @@ -1695,7 +1689,6 @@ config STM32_PHYADDR config STM32_MII bool "Use MII interface" default n - depends on STM32_ETHMAC ---help--- Support Ethernet MII interface. @@ -1732,16 +1725,15 @@ config STM32_MII_EXTCLK endchoice config STM32_AUTONEG - bool "Use autonegtiation" + bool "Use autonegotiation" default y - depends on STM32_ETHMAC ---help--- - Use PHY autonegotion to determine speed and mode + Use PHY autonegotiation to determine speed and mode config STM32_ETHFD bool "Full duplex" default n - depends on STM32_ETHMAC && !STM32_AUTONEG + depends on !STM32_AUTONEG ---help--- If STM32_AUTONEG is not defined, then this may be defined to select full duplex mode. Default: half-duplex @@ -1749,61 +1741,104 @@ config STM32_ETHFD config STM32_ETH100MBPS bool "100 Mbps" default n - depends on STM32_ETHMAC && !STM32_AUTONEG + depends on !STM32_AUTONEG ---help--- If STM32_AUTONEG is not defined, then this may be defined to select 100 MBps speed. Default: 10 Mbps config STM32_PHYSR - hex "PHY status register address" + int "PHY Status Register Address (decimal)" depends on STM32_AUTONEG ---help--- This must be provided if STM32_AUTONEG is defined. The PHY status register address may diff from PHY to PHY. This configuration sets the address of the PHY status register. -config STM32_PHYSR_SPEED - hex "PHY speed mask" +config STM32_PHYSR_ALTCONFIG + bool "PHY Status Alternate Bit Layout" + default n depends on STM32_AUTONEG + ---help--- + Different PHYs present speed and mode information in different ways. Some + will present separate information for speed and mode (this is the default). + Those PHYs, for example, may provide a 10/100 Mbps indication and a separate + full/half duplex indication. This options selects an alternative representation + where speed and mode information are combined. This might mean, for example, + separate bits for 10HD, 100HD, 10FD and 100FD. + +config STM32_PHYSR_SPEED + hex "PHY Speed Mask" + depends on STM32_AUTONEG && !STM32_PHYSR_ALTCONFIG ---help--- This must be provided if STM32_AUTONEG is defined. This provides bit mask - indicating 10 or 100MBps speed. + for isolating the 10 or 100MBps speed indication. config STM32_PHYSR_100MBPS - hex "PHY 100Mbps speed value" - depends on STM32_AUTONEG + hex "PHY 100Mbps Speed Value" + depends on STM32_AUTONEG && !STM32_PHYSR_ALTCONFIG ---help--- This must be provided if STM32_AUTONEG is defined. This provides the value of the speed bit(s) indicating 100MBps speed. config STM32_PHYSR_MODE - hex "PHY mode mask" - depends on STM32_AUTONEG + hex "PHY Mode Mask" + depends on STM32_AUTONEG && !STM32_PHYSR_ALTCONFIG ---help--- This must be provided if STM32_AUTONEG is defined. This provide bit mask - indicating full or half duplex modes. + for isolating the full or half duplex mode bits. config STM32_PHYSR_FULLDUPLEX - hex "PHY full duplex mode value" - depends on STM32_AUTONEG + hex "PHY Full Duplex Mode Value" + depends on STM32_AUTONEG && !STM32_PHYSR_ALTCONFIG ---help--- This must be provided if STM32_AUTONEG is defined. This provides the value of the mode bits indicating full duplex mode. +config STM32_PHYSR_ALTMODE + hex "PHY Mode Mask" + depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG + ---help--- + This must be provided if STM32_AUTONEG is defined. This provide bit mask + for isolating the speed and full/half duplex mode bits. + +config STM32_PHYSR_10HD + hex "10MHz/Half Duplex Value" + depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 10Mbps, half duplex setting. + +config STM32_PHYSR_100HD + hex "100MHz/Half Duplex Value" + depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 100Mbps, half duplex setting. + +config STM32_PHYSR_10FD + hex "10MHz/Full Duplex Value" + depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 10Mbps, full duplex setting. + +config STM32_PHYSR_100FD + hex "100MHz/Full Duplex Value" + depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 100Mbps, full duplex setting. + config STM32_ETH_PTP bool "Precision Time Protocol (PTP)" default n - depends on STM32_ETHMAC ---help--- Precision Time Protocol (PTP). Not supported but some hooks are indicated with this condition. -endmenu - config STM32_RMII bool default y if !STM32_MII - depends on STM32_ETHMAC choice prompt "RMII clock configuration" @@ -1837,6 +1872,16 @@ config STM32_RMII_EXTCLK endchoice +config STM32_ETHMAC_REGDEBUG + bool "Register-Level Debug" + default n + depends on DEBUG + ---help--- + Enable very low-level register access debug. Depends on DEBUG. + +endmenu +endif + menu "USB Host Configuration" config STM32_OTGFS_RXFIFO_SIZE diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_eth.h b/nuttx/arch/arm/src/stm32/chip/stm32_eth.h index 431144009e..a4a109d016 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32_eth.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32_eth.h @@ -62,7 +62,9 @@ #define STM32_ETH_MACVLANTR_OFFSET 0x001c /* Ethernet MAC VLAN tag register */ #define STM32_ETH_MACRWUFFR_OFFSET 0x0028 /* Ethernet MAC remote wakeup frame filter reg */ #define STM32_ETH_MACPMTCSR_OFFSET 0x002c /* Ethernet MAC PMT control and status register */ -#define STM32_ETH_MACDBGR_OFFSET 0x0034 /* Ethernet MAC debug register */ +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +# define STM32_ETH_MACDBGR_OFFSET 0x0034 /* Ethernet MAC debug register */ +#endif #define STM32_ETH_MACSR_OFFSET 0x0038 /* Ethernet MAC interrupt status register */ #define STM32_ETH_MACIMR_OFFSET 0x003c /* Ethernet MAC interrupt mask register */ #define STM32_ETH_MACA0HR_OFFSET 0x0040 /* Ethernet MAC address 0 high register */ @@ -132,7 +134,9 @@ #define STM32_ETH_MACVLANTR (STM32_ETHERNET_BASE+STM32_ETH_MACVLANTR_OFFSET) #define STM32_ETH_MACRWUFFR (STM32_ETHERNET_BASE+STM32_ETH_MACRWUFFR_OFFSET) #define STM32_ETH_MACPMTCSR (STM32_ETHERNET_BASE+STM32_ETH_MACPMTCSR_OFFSET) -#define STM32_ETH_MACDBGR (STM32_ETHERNET_BASE+STM32_ETH_MACDBGR_OFFSET) +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +# define STM32_ETH_MACDBGR (STM32_ETHERNET_BASE+STM32_ETH_MACDBGR_OFFSET) +#endif #define STM32_ETH_MACSR (STM32_ETHERNET_BASE+STM32_ETH_MACSR_OFFSET) #define STM32_ETH_MACIMR (STM32_ETHERNET_BASE+STM32_ETH_MACIMR_OFFSET) #define STM32_ETH_MACA0HR (STM32_ETHERNET_BASE+STM32_ETH_MACA0HR_OFFSET) @@ -216,7 +220,9 @@ # define ETH_MACCR_IFG(n) ((12-((n) >> 3)) << ETH_MACCR_IFG_SHIFT) /* n bit times, n=40,48,..96 */ #define ETH_MACCR_JD (1 << 22) /* Bit 22: Jabber disable */ #define ETH_MACCR_WD (1 << 23) /* Bit 23: Watchdog disable */ -#define ETH_MACCR_CSTF (1 << 25) /* Bits 25: CRC stripping for Type frames */ +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +# define ETH_MACCR_CSTF (1 << 25) /* Bits 25: CRC stripping for Type frames */ +#endif /* Ethernet MAC frame filter register */ @@ -303,6 +309,8 @@ /* Ethernet MAC debug register */ +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) + #define ETH_MACDBGR_MMRPEA (1 << 0) /* Bit 0: MAC MII receive protocol engine active */ #define ETH_MACDBGR_MSFRWCS_SHIFT (1) /* Bits 1-2: MAC small FIFO read / write controllers status */ #define ETH_MACDBGR_MSFRWCS_MASK (3 << ETH_MACDBGR_MSFRWCS_SHIFT) @@ -337,6 +345,8 @@ #define ETH_MACDBGR_TFNE (1 << 24) /* Bit 24: Tx FIFO not empty */ #define ETH_MACDBGR_TFF (1 << 25) /* Bit 25: Tx FIFO full */ +#endif + /* Ethernet MAC interrupt status register */ #define ETH_MACSR_PMTS (1 << 3) /* Bit 3: PMT status */ @@ -419,7 +429,9 @@ #define ETH_MMCCR_ROR (1 << 2) /* Bit 2: Reset on read */ #define ETH_MMCCR_MCF (1 << 3) /* Bit 3: MMC counter freeze */ #define ETH_MMCCR_MCP (1 << 4) /* Bit 4: MMC counter preset */ -#define ETH_MMCCR_MCFHP (1 << 5) /* Bit 5: MMC counter Full-Half preset */ +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +# define ETH_MMCCR_MCFHP (1 << 5) /* Bit 5: MMC counter Full-Half preset */ +#endif /* Ethernet MMC receive interrupt and interrupt mask registers */ @@ -453,6 +465,8 @@ #define ETH_PTPTSCR_TSSTU (1 << 3) /* Bit 3: Time stamp system time update */ #define ETH_PTPTSCR_TSITE (1 << 4) /* Bit 4: Time stamp interrupt trigger enable */ #define ETH_PTPTSCR_TSARU (1 << 5) /* Bit 5: Time stamp addend register update */ + +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) #define ETH_PTPTSCR_TSSARFE (1 << 8) /* Bit 8: Time stamp snapshot for all received frames enable */ #define ETH_PTPTSCR_TSSSR (1 << 9) /* Bit 9: Time stamp subsecond rollover: digital or binary rollover control */ #define ETH_PTPTSCR_TSPTPPSV2E (1 << 10) /* Bit 10: Time stamp PTP packet snooping for version2 format enable */ @@ -468,6 +482,7 @@ # define ETH_PTPTSCR_TSCNT_E2E (2 << ETH_PTPTSCR_TSCNT_SHIFT) /* 10: End-to-end transparent clock */ # define ETH_PTPTSCR_TSCNT_P2P (3 << ETH_PTPTSCR_TSCNT_SHIFT) /* 11: Peer-to-peer transparent clock */ #define ETH_PTPTSCR_TSPFFMAE (1 << 18) /* Bit 18: Time stamp PTP frame filtering MAC address enable */ +#endif /* Ethernet PTP subsecond increment register */ @@ -543,7 +558,9 @@ #define ETH_DMABMR_USP (1 << 23) /* Bit 23: Use separate PBL */ #define ETH_DMABMR_FPM (1 << 24) /* Bit 24: 4xPBL mode */ #define ETH_DMABMR_AAB (1 << 25) /* Bit 25: Address-aligned beats */ -#define ETH_DMABMR_MB (1 << 26) /* Bit 26: Mixed burst */ +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +# define ETH_DMABMR_MB (1 << 26) /* Bit 26: Mixed burst */ +#endif /* Ethernet DMA transmit poll demand register (32-bit) */ /* Ethernet DMA receive poll demand register (32-bit) */ @@ -694,7 +711,9 @@ /* RDES0: Receive descriptor Word0 */ #define ETH_RDES0_PCE (1 << 0) /* Bit 0: Payload checksum error */ -#define ETH_RDES0_ESA (1 << 0) /* Bit 0: Extended status available */ +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) +# define ETH_RDES0_ESA (1 << 0) /* Bit 0: Extended status available */ +#endif #define ETH_RDES0_CE (1 << 1) /* Bit 1: CRC error */ #define ETH_RDES0_DBE (1 << 2) /* Bit 2: Dribble bit error */ #define ETH_RDES0_RE (1 << 3) /* Bit 3: Receive error */ @@ -718,8 +737,9 @@ /* RDES1: Receive descriptor Word1 */ -#define ETH_RDES1_RBS1_SHIFT (0) /* Bits 0-12: Receive buffer 1 size */ +#define ETH_RDES1_RBS1_SHIFT (0) /* Bits 0-12: Receive buffer 1 size */ #define ETH_RDES1_RBS1_MASK (0x1fff << ETH_RDES1_RBS1_SHIFT) + /* Bit 13: Reserved */ #define ETH_RDES1_RCH (1 << 14) /* Bit 14: Second address chained */ #define ETH_RDES1_RER (1 << 15) /* Bit 15: Receive end of ring */ #define ETH_RDES1_RBS2_SHIFT (16) /* Bits 16-28: Receive buffer 2 size */ diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_gpio.h b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_gpio.h index feeeda6dd2..a95d13100e 100644 --- a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_gpio.h +++ b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_gpio.h @@ -265,48 +265,58 @@ /* AF remap and debug I/O configuration register */ -#define AFIO_MAPR_SWJ_CFG_SHIFT (24) /* Bits 26-24: Serial Wire JTAG configuration*/ +#define AFIO_MAPR_SPI1_REMAP (1 << 0) /* Bit 0: SPI1 remapping */ +#define AFIO_MAPR_I2C1_REMAP (1 << 1) /* Bit 1: I2C1 remapping */ +#define AFIO_MAPR_USART1_REMAP (1 << 2) /* Bit 2: USART1 remapping */ +#define AFIO_MAPR_USART2_REMAP (1 << 3) /* Bit 3: USART2 remapping */ +#define AFIO_MAPR_USART3_REMAP_SHIFT (4) /* Bits 5-4: USART3 remapping */ +#define AFIO_MAPR_USART3_REMAP_MASK (3 << AFIO_MAPR_USART3_REMAP_SHIFT) +# define AFIO_MAPR_USART3_NOREMAP (0 << AFIO_MAPR_USART3_REMAP_SHIFT) /* 00: No remap */ +# define AFIO_MAPR_USART3_PARTREMAP (1 << AFIO_MAPR_USART3_REMAP_SHIFT) /* 01: Partial remap */ +# define AFIO_MAPR_USART3_FULLREMAP (3 << AFIO_MAPR_USART3_REMAP_SHIFT) /* 11: Full remap */ +#define AFIO_MAPR_TIM1_REMAP_SHIFT (6) /* Bits 7-6: TIM1 remapping */ +#define AFIO_MAPR_TIM1_REMAP_MASK (3 << AFIO_MAPR_TIM1_REMAP_SHIFT) +# define AFIO_MAPR_TIM1_NOREMAP (0 << AFIO_MAPR_TIM1_REMAP_SHIFT) /* 00: No remap */ +# define AFIO_MAPR_TIM1_PARTREMAP (1 << AFIO_MAPR_TIM1_REMAP_SHIFT) /* 01: Partial remap */ +# define AFIO_MAPR_TIM1_FULLREMAP (3 << AFIO_MAPR_TIM1_REMAP_SHIFT) /* 11: Full remap */ +#define AFIO_MAPR_TIM2_REMAP_SHIFT (8) /* Bits 9-8: TIM2 remapping */ +#define AFIO_MAPR_TIM2_REMAP_MASK (3 << AFIO_MAPR_TIM2_REMAP_SHIFT) +# define AFIO_MAPR_TIM2_NOREMAP (0 << AFIO_MAPR_TIM2_REMAP_SHIFT) /* 00: No remap */ +# define AFIO_MAPR_TIM2_PARTREMAP1 (1 << AFIO_MAPR_TIM2_REMAP_SHIFT) /* 01: Partial remap */ +# define AFIO_MAPR_TIM2_PARTREMAP2 (2 << AFIO_MAPR_TIM2_REMAP_SHIFT) /* 10: Partial remap */ +# define AFIO_MAPR_TIM2_FULLREMAP (3 << AFIO_MAPR_TIM2_REMAP_SHIFT) /* 11: Full remap */ +#define AFIO_MAPR_TIM3_REMAP_SHIFT (10) /* Bits 11-10: TIM3 remapping */ +#define AFIO_MAPR_TIM3_REMAP_MASK (3 << AFIO_MAPR_TIM3_REMAP_SHIFT) +# define AFIO_MAPR_TIM3_NOREMAP (0 << AFIO_MAPR_TIM3_REMAP_SHIFT) /* 00: No remap */ +# define AFIO_MAPR_TIM3_PARTREMAP (2 << AFIO_MAPR_TIM3_REMAP_SHIFT) /* 10: Partial remap */ +# define AFIO_MAPR_TIM3_FULLREMAP (3 << AFIO_MAPR_TIM3_REMAP_SHIFT) /* 11: Full remap */ +#define AFIO_MAPR_TIM4_REMAP (1 << 12) /* Bit 12: TIM4 remapping */ +#define AFIO_MAPR_CAN1_REMAP_SHIFT (13) /* Bits 14-13: CAN Alternate function remapping */ +#define AFIO_MAPR_CAN1_REMAP_MASK (3 << AFIO_MAPR_CAN1_REMAP_SHIFT) +# define AFIO_MAPR_PA1112 (0 << AFIO_MAPR_CAN1_REMAP_SHIFT) /* 00: CANRX mapped to PA11, CANTX mapped to PA12 */ +# define AFIO_MAPR_PB89 (2 << AFIO_MAPR_CAN1_REMAP_SHIFT) /* 10: CANRX mapped to PB8, CANTX mapped to PB9 */ +# define AFIO_MAPR_PD01 (3 << AFIO_MAPR_CAN1_REMAP_SHIFT) /* 11: CANRX mapped to PD0, CANTX mapped to PD1 */ +#define AFIO_MAPR_PD01_REMAP (1 << 15) /* Bit 15 : Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_MAPR_TIM5CH4_IREMAP (1 << 16) /* Bit 16: TIM5 channel4 internal remap */ + /* Bits 17-20: Reserved */ +#ifdef CONFIG_STM32_CONNECTIVITYLINE +# define AFIO_MAPR_ETH_REMAP (1 << 21) /* Bit 21: Ethernet MAC I/O remapping */ +# define AFIO_MAPR_CAN2_REMAP (1 << 22) /* Bit 22: CAN2 I/O remapping */ +# define AFIO_MAPR_MII_RMII_SEL (1 << 23) /* Bit 23: MII or RMII selection */ +#endif +#define AFIO_MAPR_SWJ_CFG_SHIFT (24) /* Bits 26-24: Serial Wire JTAG configuration */ #define AFIO_MAPR_SWJ_CFG_MASK (7 << AFIO_MAPR_SWJ_CFG_SHIFT) # define AFIO_MAPR_SWJRST (0 << AFIO_MAPR_SWJ_CFG_SHIFT) /* 000: Full SWJ (JTAG-DP + SW-DP): Reset State */ # define AFIO_MAPR_SWJ (1 << AFIO_MAPR_SWJ_CFG_SHIFT) /* 001: Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ # define AFIO_MAPR_SWDP (2 << AFIO_MAPR_SWJ_CFG_SHIFT) /* 010: JTAG-DP Disabled and SW-DP Enabled */ # define AFIO_MAPR_DISAB (4 << AFIO_MAPR_SWJ_CFG_SHIFT) /* 100: JTAG-DP Disabled and SW-DP Disabled */ + /* Bit 27: Reserved */ #ifdef CONFIG_STM32_CONNECTIVITYLINE -# define AFIO_MAPR_MII_RMII_SEL (1 << 23) /* MII or RMII selection */ +# define AFIO_MAPR_SPI3_REMAP (1 << 28) /* Bit 28: SPI3 remapping */ +# define AFIO_MAPR_TIM2ITR1_IREMAP (1 << 29) /* Bit 29: TIM2 internal trigger 1 remapping */ +# define AFIO_MAPR_PTP_PPS_REMAP (1 << 30) /* Bit 30: Ethernet PTP PPS remapping */ #endif -#define AFIO_MAPR_PD01_REMAP (1 << 15) /* Bit 15 : Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_MAPR_CAN_REMAP_SHIFT (13) /* Bits 14-13: CAN Alternate function remapping */ -#define AFIO_MAPR_CAN_REMAP_MASK (3 << AFIO_MAPR_CAN_REMAP_SHIFT) -# define AFIO_MAPR_PA1112 (0 << AFIO_MAPR_CAN_REMAP_SHIFT) /* 00: CANRX mapped to PA11, CANTX mapped to PA12 */ -# define AFIO_MAPR_PB89 (2 << AFIO_MAPR_CAN_REMAP_SHIFT) /* 10: CANRX mapped to PB8, CANTX mapped to PB9 */ -# define AFIO_MAPR_PD01 (3 << AFIO_MAPR_CAN_REMAP_SHIFT) /* 11: CANRX mapped to PD0, CANTX mapped to PD1 */ -#define AFIO_MAPR_TIM4_REMAP (1 << 12) /* Bit 12: TIM4 remapping */ -#define AFIO_MAPR_TIM3_REMAP_SHIFT (10) /* Bits 11-10: TIM3 remapping */ -#define AFIO_MAPR_TIM3_REMAP_MASK (3 << AFIO_MAPR_TIM3_REMAP_SHIFT) -# define AFIO_MAPR_TIM3_NOREMAP (0 << AFIO_MAPR_TIM3_REMAP_SHIFT) /* 00: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ -# define AFIO_MAPR_TIM3_PARTREMAP (2 << AFIO_MAPR_TIM3_REMAP_SHIFT) /* 10: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ -# define AFIO_MAPR_TIM3_FULLREMAP (3 << AFIO_MAPR_TIM3_REMAP_SHIFT) /* 11: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ -#define AFIO_MAPR_TIM2_REMAP_SHIFT (8) /* Bits 9-8: TIM2 remapping */ -#define AFIO_MAPR_TIM2_REMAP_MASK (3 << AFIO_MAPR_TIM2_REMAP_SHIFT) -# define AFIO_MAPR_TIM2_NOREMAP (0 << AFIO_MAPR_TIM2_REMAP_SHIFT) /* 00: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ -# define AFIO_MAPR_TIM2_PARTREMAP1 (1 << AFIO_MAPR_TIM2_REMAP_SHIFT) /* 01: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ -# define AFIO_MAPR_TIM2_PARTREMAP2 (2 << AFIO_MAPR_TIM2_REMAP_SHIFT) /* 10: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ -# define AFIO_MAPR_TIM2_FULLREMAP (3 << AFIO_MAPR_TIM2_REMAP_SHIFT) /* 11: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ -#define AFIO_MAPR_TIM1_REMAP_SHIFT (6) /* Bits 7-6: TIM1 remapping */ -#define AFIO_MAPR_TIM1_REMAP_MASK (3 << AFIO_MAPR_TIM1_REMAP_SHIFT) -# define AFIO_MAPR_TIM1_NOREMAP (0 << AFIO_MAPR_TIM1_REMAP_SHIFT) /* 00: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ -# define AFIO_MAPR_TIM1_PARTREMAP (1 << AFIO_MAPR_TIM1_REMAP_SHIFT) /* 01: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ -# define AFIO_MAPR_TIM1_FULLREMAP (3 << AFIO_MAPR_TIM1_REMAP_SHIFT) /* 11: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ -#define AFIO_MAPR_USART3_REMAP_SHIFT (6) /* Bits 5-4: USART3 remapping */ -#define AFIO_MAPR_USART3_REMAP_MASK (3 << AFIO_MAPR_USART3_REMAP_SHIFT) -# define AFIO_MAPR_USART3_NOREMAP (0 << AFIO_MAPR_USART3_REMAP_SHIFT) /* 00: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ -# define AFIO_MAPR_USART3_PARTREMAP (1 << AFIO_MAPR_USART3_REMAP_SHIFT) /* 01: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ -# define AFIO_MAPR_USART3_FULLREMAP (3 << AFIO_MAPR_USART3_REMAP_SHIFT) /* 11: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ -#define AFIO_MAPR_USART2_REMAP (1 << 3) /* Bit 3: USART2 remapping */ -#define AFIO_MAPR_USART1_REMAP (1 << 2) /* Bit 2: USART1 remapping */ -#define AFIO_MAPR_I2C1_REMAP (1 << 1) /* Bit 1: I2C1 remapping */ -#define AFIO_MAPR_SPI1_REMAP (1 << 0) /* Bit 0: SPI1 remapping */ - + /* Bit 31: Reserved */ /* External interrupt configuration register 1 */ #define AFIO_EXTICR_PORT_MASK (0x0f) diff --git a/nuttx/arch/arm/src/stm32/stm32_eth.c b/nuttx/arch/arm/src/stm32/stm32_eth.c index 59f3def7f6..2e892c9e54 100644 --- a/nuttx/arch/arm/src/stm32/stm32_eth.c +++ b/nuttx/arch/arm/src/stm32/stm32_eth.c @@ -135,17 +135,35 @@ # ifndef CONFIG_STM32_PHYSR # error "CONFIG_STM32_PHYSR must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32_PHYSR_SPEED -# error "CONFIG_STM32_PHYSR_SPEED must be defined in the NuttX configuration" -# endif -# ifndef CONFIG_STM32_PHYSR_100MBPS -# error "CONFIG_STM32_PHYSR_100MBPS must be defined in the NuttX configuration" -# endif -# ifndef CONFIG_STM32_PHYSR_MODE -# error "CONFIG_STM32_PHYSR_MODE must be defined in the NuttX configuration" -# endif -# ifndef CONFIG_STM32_PHYSR_FULLDUPLEX -# error "CONFIG_STM32_PHYSR_FULLDUPLEX must be defined in the NuttX configuration" +# ifdef CONFIG_STM32_PHYSR_ALTCONFIG +# ifndef CONFIG_STM32_PHYSR_ALTMODE +# error "CONFIG_STM32_PHYSR_ALTMODE must be defined in the NuttX configuration" +# endif +# ifndef CONFIG_STM32_PHYSR_10HD +# error "CONFIG_STM32_PHYSR_10HD must be defined in the NuttX configuration" +# endif +# ifndef CONFIG_STM32_PHYSR_100HD +# error "CONFIG_STM32_PHYSR_100HD must be defined in the NuttX configuration" +# endif +# ifndef CONFIG_STM32_PHYSR_10FD +# error "CONFIG_STM32_PHYSR_10FD must be defined in the NuttX configuration" +# endif +# ifndef CONFIG_STM32_PHYSR_100FD +# error "CONFIG_STM32_PHYSR_100FD must be defined in the NuttX configuration" +# endif +# else +# ifndef CONFIG_STM32_PHYSR_SPEED +# error "CONFIG_STM32_PHYSR_SPEED must be defined in the NuttX configuration" +# endif +# ifndef CONFIG_STM32_PHYSR_100MBPS +# error "CONFIG_STM32_PHYSR_100MBPS must be defined in the NuttX configuration" +# endif +# ifndef CONFIG_STM32_PHYSR_MODE +# error "CONFIG_STM32_PHYSR_MODE must be defined in the NuttX configuration" +# endif +# ifndef CONFIG_STM32_PHYSR_FULLDUPLEX +# error "CONFIG_STM32_PHYSR_FULLDUPLEX must be defined in the NuttX configuration" +# endif # endif #endif @@ -168,10 +186,12 @@ #endif /* Add 4 to the configured buffer size to account for the 2 byte checksum - * memory needed at the end of the maximum size packet. + * memory needed at the end of the maximum size packet. Buffer sizes must + * be an even multiple of 4, 8, or 16 bytes (depending on buswidth). We + * will use the 16-byte alignment in all cases. */ -#define OPTIMAL_ETH_BUFSIZE (CONFIG_NET_BUFSIZE+4) +#define OPTIMAL_ETH_BUFSIZE ((CONFIG_NET_BUFSIZE + 4 + 15) & ~15) #ifndef CONFIG_STM32_ETH_BUFSIZE # define CONFIG_STM32_ETH_BUFSIZE OPTIMAL_ETH_BUFSIZE @@ -181,6 +201,10 @@ # error "CONFIG_STM32_ETH_BUFSIZE is too large" #endif +#if (CONFIG_STM32_ETH_BUFSIZE & 15) != 0 +# error "CONFIG_STM32_ETH_BUFSIZE must be aligned" +#endif + #if CONFIG_STM32_ETH_BUFSIZE != OPTIMAL_ETH_BUFSIZE # warning "You using an incomplete/untested configuration" #endif @@ -265,14 +289,22 @@ * ETH_MACCR_IFG Bits 17-19: Interframe gap * ETH_MACCR_JD Bit 22: Jabber disable * ETH_MACCR_WD Bit 23: Watchdog disable - * ETH_MACCR_CSTF Bits 25: CRC stripping for Type frames + * ETH_MACCR_CSTF Bits 25: CRC stripping for Type frames (F2/F4 only) */ +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) #define MACCR_CLEAR_BITS \ - ( ETH_MACCR_RE | ETH_MACCR_TE | ETH_MACCR_DC | ETH_MACCR_BL_MASK | \ + (ETH_MACCR_RE | ETH_MACCR_TE | ETH_MACCR_DC | ETH_MACCR_BL_MASK | \ ETH_MACCR_APCS | ETH_MACCR_RD | ETH_MACCR_IPCO | ETH_MACCR_DM | \ ETH_MACCR_LM | ETH_MACCR_ROD | ETH_MACCR_FES | ETH_MACCR_CSD | \ - ETH_MACCR_IFG_MASK | ETH_MACCR_JD | ETH_MACCR_WD | ETH_MACCR_CSTF ) + ETH_MACCR_IFG_MASK | ETH_MACCR_JD | ETH_MACCR_WD | ETH_MACCR_CSTF) +#else +#define MACCR_CLEAR_BITS \ + (ETH_MACCR_RE | ETH_MACCR_TE | ETH_MACCR_DC | ETH_MACCR_BL_MASK | \ + ETH_MACCR_APCS | ETH_MACCR_RD | ETH_MACCR_IPCO | ETH_MACCR_DM | \ + ETH_MACCR_LM | ETH_MACCR_ROD | ETH_MACCR_FES | ETH_MACCR_CSD | \ + ETH_MACCR_IFG_MASK | ETH_MACCR_JD | ETH_MACCR_WD) +#endif /* The following bits are set or left zero unconditionally in all modes. * @@ -289,7 +321,7 @@ * ETH_MACCR_IFG Interframe gap 0 (96 bits) * ETH_MACCR_JD Jabber disable 0 (enabled) * ETH_MACCR_WD Watchdog disable 0 (enabled) - * ETH_MACCR_CSTF CRC stripping for Type frames 0 (disabled) + * ETH_MACCR_CSTF CRC stripping for Type frames 0 (disabled, F2/F4 only) * * The following are set conditioinally based on mode and speed. * @@ -444,13 +476,20 @@ * ETH_DMABMR_USP Bit 23: Use separate PBL * ETH_DMABMR_FPM Bit 24: 4xPBL mode * ETH_DMABMR_AAB Bit 25: Address-aligned beats - * ETH_DMABMR_MB Bit 26: Mixed burst + * ETH_DMABMR_MB Bit 26: Mixed burst (F2/F4 only) */ +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) #define DMABMR_CLEAR_MASK \ (ETH_DMABMR_SR | ETH_DMABMR_DA | ETH_DMABMR_DSL_MASK | ETH_DMABMR_EDFE | \ ETH_DMABMR_PBL_MASK | ETH_DMABMR_RTPR_MASK | ETH_DMABMR_FB | ETH_DMABMR_RDP_MASK | \ ETH_DMABMR_USP | ETH_DMABMR_FPM | ETH_DMABMR_AAB | ETH_DMABMR_MB) +#else +#define DMABMR_CLEAR_MASK \ + (ETH_DMABMR_SR | ETH_DMABMR_DA | ETH_DMABMR_DSL_MASK | ETH_DMABMR_EDFE | \ + ETH_DMABMR_PBL_MASK | ETH_DMABMR_RTPR_MASK | ETH_DMABMR_FB | ETH_DMABMR_RDP_MASK | \ + ETH_DMABMR_USP | ETH_DMABMR_FPM | ETH_DMABMR_AAB) +#endif /* The following bits are set or left zero unconditionally in all modes. * @@ -466,7 +505,7 @@ * ETH_DMABMR_USP Use separate PBL 1 (enabled) * ETH_DMABMR_FPM 4xPBL mode 0 (disabled) * ETH_DMABMR_AAB Address-aligned beats 1 (enabled) - * ETH_DMABMR_MB Mixed burst 0 (disabled) + * ETH_DMABMR_MB Mixed burst 0 (disabled, F2/F4 only) */ #ifdef CONFIG_STM32_ETH_ENHANCEDDESC @@ -1437,9 +1476,6 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv) { priv->segments++; - nllvdbg("rxhead: %p rxcurr: %p segments: %d\n", - priv->rxhead, priv->rxcurr, priv->segments); - /* Check if the there is only one segment in the frame */ if (priv->segments == 1) @@ -1451,6 +1487,9 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv) rxcurr = priv->rxcurr; } + nllvdbg("rxhead: %p rxcurr: %p segments: %d\n", + priv->rxhead, priv->rxcurr, priv->segments); + /* Check if any errors are reported in the frame */ if ((rxdesc->rdes0 & ETH_RDES0_ES) == 0) @@ -1983,7 +2022,7 @@ static int stm32_ifup(struct uip_driver_s *dev) ndbg("Bringing up: %d.%d.%d.%d\n", dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 ); + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); /* Configure the Ethernet interface for DMA operation. */ @@ -2224,7 +2263,7 @@ static void stm32_txdescinit(FAR struct stm32_ethmac_s *priv) /* Initialize the next descriptor with the Next Descriptor Polling Enable */ - if( i < (CONFIG_STM32_ETH_NTXDESC-1)) + if (i < (CONFIG_STM32_ETH_NTXDESC-1)) { /* Set next descriptor address register with next descriptor base * address @@ -2303,7 +2342,7 @@ static void stm32_rxdescinit(FAR struct stm32_ethmac_s *priv) /* Initialize the next descriptor with the Next Descriptor Polling Enable */ - if( i < (CONFIG_STM32_ETH_NRXDESC-1)) + if (i < (CONFIG_STM32_ETH_NRXDESC-1)) { /* Set next descriptor address register with next descriptor base * address @@ -2506,7 +2545,7 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv) if (timeout >= PHY_RETRY_TIMEOUT) { - ndbg("Timed out waiting for link status\n"); + ndbg("Timed out waiting for link status: %04x\n", phyval); return -ETIMEDOUT; } @@ -2552,6 +2591,46 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv) /* Remember the selected speed and duplex modes */ + nvdbg("PHYSR[%d]: %04x\n", CONFIG_STM32_PHYSR, phyval); + + /* Different PHYs present speed and mode information in different ways. IF + * This CONFIG_STM32_PHYSR_ALTCONFIG is selected, this indicates that the PHY + * represents speed and mode information are combined, for example, with + * separate bits for 10HD, 100HD, 10FD and 100FD. + */ + +#ifdef CONFIG_STM32_PHYSR_ALTCONFIG + switch (phyval & CONFIG_STM32_PHYSR_ALTMODE) + { + default: + case CONFIG_STM32_PHYSR_10HD: + priv->fduplex = 0; + priv->mbps100 = 0; + break; + + case CONFIG_STM32_PHYSR_100HD: + priv->fduplex = 0; + priv->mbps100 = 1; + break; + + case CONFIG_STM32_PHYSR_10FD: + priv->fduplex = 1; + priv->mbps100 = 0; + break; + + case CONFIG_STM32_PHYSR_100FD: + priv->fduplex = 1; + priv->mbps100 = 1; + break; + } + + /* Different PHYs present speed and mode information in different ways. Some + * will present separate information for speed and mode (this is the default). + * Those PHYs, for example, may provide a 10/100 Mbps indication and a separate + * full/half duplex indication. + */ + +#else if ((phyval & CONFIG_STM32_PHYSR_MODE) == CONFIG_STM32_PHYSR_FULLDUPLEX) { priv->fduplex = 1; @@ -2561,6 +2640,7 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv) { priv->mbps100 = 1; } +#endif #else /* Auto-negotion not selected */ @@ -2854,7 +2934,7 @@ static void stm32_ethreset(FAR struct stm32_ethmac_s *priv) * reset all the registers holds their reset values. */ - regval = stm32_getreg(STM32_ETH_DMABMR); + regval = stm32_getreg(STM32_ETH_DMABMR); regval |= ETH_DMABMR_SR; stm32_putreg(regval, STM32_ETH_DMABMR); diff --git a/nuttx/arch/arm/src/stm32/stm32_gpio.c b/nuttx/arch/arm/src/stm32/stm32_gpio.c index 143e48a2c8..4703e82089 100644 --- a/nuttx/arch/arm/src/stm32/stm32_gpio.c +++ b/nuttx/arch/arm/src/stm32/stm32_gpio.c @@ -124,14 +124,27 @@ static inline void stm32_gpioremap(void) uint32_t val = 0; -#ifdef CONFIG_STM32_JTAG_FULL_ENABLE - /* The reset default */ -#elif CONFIG_STM32_JTAG_NOJNTRST_ENABLE - val |= AFIO_MAPR_SWJ; /* enabled but without JNTRST */ -#elif CONFIG_STM32_JTAG_SW_ENABLE - val |= AFIO_MAPR_SWDP; /* set JTAG-DP disabled and SW-DP enabled */ -#else - val |= AFIO_MAPR_DISAB; /* set JTAG-DP and SW-DP Disabled */ +#ifdef CONFIG_STM32_SPI1_REMAP + val |= AFIO_MAPR_SPI1_REMAP; +#endif +#ifdef CONFIG_STM32_SPI3_REMAP +#endif + +#ifdef CONFIG_STM32_I2C1_REMAP + val |= AFIO_MAPR_I2C1_REMAP; +#endif + +#ifdef CONFIG_STM32_USART1_REMAP + val |= AFIO_MAPR_USART1_REMAP; +#endif +#ifdef CONFIG_STM32_USART2_REMAP + val |= AFIO_MAPR_USART2_REMAP; +#endif +#ifdef CONFIG_STM32_USART3_FULL_REMAP + val |= AFIO_MAPR_USART3_FULLREMAP; +#endif +#ifdef CONFIG_STM32_USART3_PARTIAL_REMAP + val |= AFIO_MAPR_USART3_PARTREMAP; #endif #ifdef CONFIG_STM32_TIM1_FULL_REMAP @@ -159,35 +172,29 @@ static inline void stm32_gpioremap(void) val |= AFIO_MAPR_TIM4_REMAP; #endif -#ifdef CONFIG_STM32_USART1_REMAP - val |= AFIO_MAPR_USART1_REMAP; -#endif -#ifdef CONFIG_STM32_USART2_REMAP - val |= AFIO_MAPR_USART2_REMAP; -#endif -#ifdef CONFIG_STM32_USART3_FULL_REMAP - val |= AFIO_MAPR_USART3_FULLREMAP; -#endif -#ifdef CONFIG_STM32_USART3_PARTIAL_REMAP - val |= AFIO_MAPR_USART3_PARTREMAP; -#endif - -#ifdef CONFIG_STM32_SPI1_REMAP - val |= AFIO_MAPR_SPI1_REMAP; -#endif -#ifdef CONFIG_STM32_SPI3_REMAP -#endif - -#ifdef CONFIG_STM32_I2C1_REMAP - val |= AFIO_MAPR_I2C1_REMAP; -#endif - #ifdef CONFIG_STM32_CAN1_REMAP1 val |= AFIO_MAPR_PB89; #endif #ifdef CONFIG_STM32_CAN1_REMAP2 val |= AFIO_MAPR_PD01; #endif +#ifdef CONFIG_STM32_CAN2_REMAP /* Connectivity line only */ + val |= AFIO_MAPR_CAN2_REMAP; +#endif + +#ifdef CONFIG_STM32_ETH_REMAP /* Connectivity line only */ + val |= AFIO_MAPR_ETH_REMAP; +#endif + +#ifdef CONFIG_STM32_JTAG_FULL_ENABLE + /* The reset default */ +#elif CONFIG_STM32_JTAG_NOJNTRST_ENABLE + val |= AFIO_MAPR_SWJ; /* enabled but without JNTRST */ +#elif CONFIG_STM32_JTAG_SW_ENABLE + val |= AFIO_MAPR_SWDP; /* set JTAG-DP disabled and SW-DP enabled */ +#else + val |= AFIO_MAPR_DISAB; /* set JTAG-DP and SW-DP Disabled */ +#endif putreg32(val, STM32_AFIO_MAPR); #endif diff --git a/nuttx/arch/arm/src/stm32/stm32_idle.c b/nuttx/arch/arm/src/stm32/stm32_idle.c index 791a79429c..83a6808c58 100644 --- a/nuttx/arch/arm/src/stm32/stm32_idle.c +++ b/nuttx/arch/arm/src/stm32/stm32_idle.c @@ -45,6 +45,7 @@ #include +#include "chip.h" #include "stm32_pm.h" #include "up_internal.h" @@ -178,11 +179,33 @@ void up_idle(void) up_idlepm(); - /* Sleep until an interrupt occurs to save power */ + /* Sleep until an interrupt occurs to save power. + * + * NOTE: There is an STM32F107 errata that is fixed by the following + * workaround: + * + * "2.17.11 Ethernet DMA not working after WFI/WFE instruction + * Description + * If a WFI/WFE instruction is executed to put the system in sleep mode + * while the Ethernet MAC master clock on the AHB bus matrix is ON and all + * remaining masters clocks are OFF, the Ethernet DMA will be not able to + * perform any AHB master accesses during sleep mode." + * + * Workaround + * Enable DMA1 or DMA2 clocks in the RCC_AHBENR register before + * executing the WFI/WFE instruction." + * + * Here the workaround is just to avoid SLEEP mode for the connectivity + * line parts if Ethernet is enabled. The errate recommends a more + * general solution: Enabling DMA1/2 clocking in stm32f10xx_rcc.c if the + * STM32107 Ethernet peripheral is enabled. + */ +#if !defined(CONFIG_STM32_CONNECTIVITYLINE) || !defined(CONFIG_STM32_ETHMAC) BEGIN_IDLE(); asm("WFI"); END_IDLE(); #endif +#endif } diff --git a/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c b/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c index 10b8572cf0..47ed5e016b 100644 --- a/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c +++ b/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c @@ -90,7 +90,7 @@ static inline void rcc_reset(void) regval = getreg32(STM32_RCC_CR); /* Reset HSEBYP bit */ regval &= ~RCC_CR_HSEBYP; putreg32(regval, STM32_RCC_CR); - + regval = getreg32(STM32_RCC_CFGR); /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */ regval &= ~(RCC_CFGR_PLLSRC|RCC_CFGR_PLLXTPRE|RCC_CFGR_PLLMUL_MASK|RCC_CFGR_USBPRE); putreg32(regval, STM32_RCC_CFGR); @@ -235,7 +235,7 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR_SPI2EN; #endif - + #ifdef CONFIG_STM32_SPI3 /* SPI 3 clock enable */ @@ -411,13 +411,128 @@ static inline void rcc_enableapb2(void) * Name: stm32_stdclockconfig * * Description: - * Called to change to new clock based on settings in board.h - * + * Called to change to new clock based on settings in board.h. This + * version is for the Connectivity Line parts. + * * NOTE: This logic would need to be extended if you need to select low- * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG +#if !defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) && defined(CONFIG_STM32_CONNECTIVITYLINE) +static void stm32_stdclockconfig(void) +{ + uint32_t regval; + + /* Enable HSE */ + + regval = getreg32(STM32_RCC_CR); + regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */ + regval |= RCC_CR_HSEON; /* Enable HSE */ + putreg32(regval, STM32_RCC_CR); + + /* Set flash wait states + * Sysclk runs with 72MHz -> 2 waitstates. + * 0WS from 0-24MHz + * 1WS from 24-48MHz + * 2WS from 48-72MHz + */ + + regval = getreg32(STM32_FLASH_ACR); + regval &= ~FLASH_ACR_LATENCY_MASK; + regval |= (FLASH_ACR_LATENCY_2|FLASH_ACR_PRTFBE); + putreg32(regval, STM32_FLASH_ACR); + + /* Set up PLL input scaling (with source = PLL2) */ + + regval = getreg32(STM32_RCC_CFGR2); + regval &= ~(RCC_CFGR2_PREDIV2_MASK | RCC_CFGR2_PLL2MUL_MASK | + RCC_CFGR2_PREDIV1SRC_MASK | RCC_CFGR2_PREDIV1_MASK); + regval |= (STM32_PLL_PREDIV2 | STM32_PLL_PLL2MUL | + RCC_CFGR2_PREDIV1SRC_PLL2 | STM32_PLL_PREDIV1); + putreg32(regval, STM32_RCC_CFGR2); + + /* Set the PCLK2 divider */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~(RCC_CFGR_PPRE2_MASK | RCC_CFGR_HPRE_MASK); + regval |= STM32_RCC_CFGR_PPRE2; + regval |= RCC_CFGR_HPRE_SYSCLK; + putreg32(regval, STM32_RCC_CFGR); + + /* Set the PCLK1 divider */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_PPRE1_MASK; + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); + + /* Enable PLL2 */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_PLL2ON; + putreg32(regval, STM32_RCC_CR); + + /* Wait for PLL2 ready */ + + while((getreg32(STM32_RCC_CR) & RCC_CR_PLL2RDY) == 0); + + /* Setup PLL3 for MII/RMII clock on MCO */ + +#if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO) + regval = getreg32(STM32_RCC_CFGR2); + regval &= ~(RCC_CFGR2_PLL3MUL_MASK); + regval |= STM32_PLL_PLL3MUL; + putreg32(regval, STM32_RCC_CFGR2); + + /* Switch PLL3 on */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_PLL3ON; + putreg32(regval, STM32_RCC_CR); + + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL3RDY) == 0); +#endif + + /* Set main PLL source and multiplier */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL_MASK); + regval |= (RCC_CFGR_PLLSRC | STM32_PLL_PLLMUL); + putreg32(regval, STM32_RCC_CFGR); + + /* Switch main PLL on */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_PLLON; + putreg32(regval, STM32_RCC_CR); + + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0); + + /* Select PLL as system clock source */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_SW_MASK; + regval |= RCC_CFGR_SW_PLL; + putreg32(regval, STM32_RCC_CFGR); + + /* Wait until PLL is used as the system clock source */ + + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_PLL) == 0); +} +#endif + +/**************************************************************************** + * Name: stm32_stdclockconfig + * + * Description: + * Called to change to new clock based on settings in board.h. This + * version is for the non-Connectivity Line parts. + * + * NOTE: This logic would need to be extended if you need to select low- + * power clocking modes! + ****************************************************************************/ + +#if !defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) && !defined(CONFIG_STM32_CONNECTIVITYLINE) static void stm32_stdclockconfig(void) { uint32_t regval; @@ -430,7 +545,7 @@ static void stm32_stdclockconfig(void) volatile int32_t timeout; /* Enable External High-Speed Clock (HSE) */ - + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */ regval |= RCC_CR_HSEON; /* Enable HSE */ diff --git a/nuttx/configs/README.txt b/nuttx/configs/README.txt index b5ada6ee5d..5bbec874f7 100644 --- a/nuttx/configs/README.txt +++ b/nuttx/configs/README.txt @@ -1570,7 +1570,8 @@ configs/ez80f0910200zco configs/fire-stm32v2 A configuration for the M3 Wildfire STM32 board. This board is based on the - STM32F103VET6 chip. See http://firestm32.taobao.com + STM32F103VET6 chip. See http://firestm32.taobao.com . Version 2 and 3 of + the boards are supported but only version 2 has been tested. configs/hymini-stm32v A configuration for the HY-Mini STM32v board. This board is based on the diff --git a/nuttx/drivers/Kconfig b/nuttx/drivers/Kconfig index 32d127aa43..ea218a5925 100644 --- a/nuttx/drivers/Kconfig +++ b/nuttx/drivers/Kconfig @@ -151,7 +151,7 @@ config SPI_EXCHANGE config SPI_CMDDATA bool "SPI CMD/DATA" - default y + default n ---help--- Devices on the SPI bus require out-of-band support to distinguish command transfers from data transfers. Such devices will often support either 9-bit diff --git a/nuttx/drivers/input/Kconfig b/nuttx/drivers/input/Kconfig index 1303cfbd0f..9fde35ff67 100644 --- a/nuttx/drivers/input/Kconfig +++ b/nuttx/drivers/input/Kconfig @@ -6,8 +6,15 @@ config INPUT_TSC2007 bool "TI TSC2007 touchscreen controller" default n select I2C + ---help--- + Enable support for the TI TSC2007 touchscreen controller + config INPUT_ADS7843E - bool "TI ADS7843E touchscreen controller" + bool "TI ADS7843/TSC2046 touchscreen controller" default n select SPI + ---help--- + Enable support for the TI/Burr-Brown ADS7842 touchscreen controller. I believe + that driver should be compatibile with the TI/Burr-Brown TSC2046 and XPT2046 + touchscreen controllers as well. diff --git a/nuttx/drivers/input/ads7843e.c b/nuttx/drivers/input/ads7843e.c index e08a7a7280..07e5e515df 100644 --- a/nuttx/drivers/input/ads7843e.c +++ b/nuttx/drivers/input/ads7843e.c @@ -9,6 +9,12 @@ * "Touch Screen Controller, ADS7843," Burr-Brown Products from Texas * Instruments, SBAS090B, September 2000, Revised May 2002" * + * See also: + * "Low Voltage I/O Touch Screen Controller, TSC2046," Burr-Brown Products + * from Texas Instruments, SBAS265F, October 2002, Revised August 2007. + * + * "XPT2046 Data Sheet," Shenzhen XPTek Technology Co., Ltd, 2007 + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: diff --git a/nuttx/drivers/input/ads7843e.h b/nuttx/drivers/input/ads7843e.h index 030d1cb332..43b79c7b7d 100644 --- a/nuttx/drivers/input/ads7843e.h +++ b/nuttx/drivers/input/ads7843e.h @@ -8,6 +8,12 @@ * "Touch Screen Controller, ADS7843," Burr-Brown Products from Texas * Instruments, SBAS090B, September 2000, Revised May 2002" * + * See also: + * "Low Voltage I/O Touch Screen Controller, TSC2046," Burr-Brown Products + * from Texas Instruments, SBAS265F, October 2002, Revised August 2007." + * + * "XPT2046 Data Sheet," Shenzhen XPTek Technology Co., Ltd, 2007 + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: diff --git a/nuttx/drivers/lcd/Kconfig b/nuttx/drivers/lcd/Kconfig index 081a79c89d..640239e637 100644 --- a/nuttx/drivers/lcd/Kconfig +++ b/nuttx/drivers/lcd/Kconfig @@ -2,6 +2,21 @@ # For a description of the syntax of this configuration file, # see misc/tools/kconfig-language.txt. # + +config LCD_NOGETRUN + bool "Write-only LCD" + default n + ---help--- + Many LCD hardware interfaces provide only minimal graphics capability. In + particulary, many simple LCD interfaces are write only. That is we, can + write graphics data to the LCD device memory, but we cannot read it back. + If the LCD hardware does not support reading the graphics memory, then + this option should be defined so that the NX layer can taking alternative + measures when the LCD is not readable. For example, if the LCD is not + readable, then NX will not attempt to support transparency. + + See also NX_WRITEONLY in the graphics support menu. + config LCD_MAXCONTRAST int "LCD maximum contrast" default 63 if NOKIA6100_S1D15G10 @@ -28,6 +43,7 @@ config LCD_P14201 p14201.c. Driver for RiT P14201 series display with SD1329 IC controller. This OLED is used with older versions of the TI/Luminary LM3S8962 Evaluation Kit. + if LCD_P14201 config P14201_NINTERFACES int "Number of physical P14201 devices" @@ -174,6 +190,33 @@ config LCD_UG9664HSWAG01 Technology Inc. Used with the LPC Xpresso and Embedded Artists base board. +config LCD_SSD1289 + bool "LCD Based on SSD1289 Controller" + default n + ---help--- + Enables generic support for any LCD based on the Solomon Systech, + Ltd, SSD1289 Controller. Use of this driver will usually require so + detailed customization of the LCD initialization code as necessary + for the specific LCD driven by the SSD1289 controller. + +if LCD_SSD1289 + +choice + prompt "SSD1289 Initialization Profile" + default SSD1289_PROFILE1 + +config SSD1289_PROFILE1 + bool "Profile 1" + +config SSD1289_PROFILE2 + bool "Profile 2" + +config SSD1289_PROFILE3 + bool "Profile 3" + +endchoice +endif + choice prompt "LCD Orientation" default LCD_LANDSCAPE diff --git a/nuttx/drivers/lcd/ssd1289.c b/nuttx/drivers/lcd/ssd1289.c index 58c6069682..3d5ba96d31 100644 --- a/nuttx/drivers/lcd/ssd1289.c +++ b/nuttx/drivers/lcd/ssd1289.c @@ -766,7 +766,7 @@ static int ssd1289_getvideoinfo(FAR struct lcd_dev_s *dev, { DEBUGASSERT(dev && vinfo); lcdvdbg("fmt: %d xres: %d yres: %d nplanes: 1\n", - SSD1289_COLORFMT, SSD1289_XRES, SSD1289_XRES); + SSD1289_COLORFMT, SSD1289_XRES, SSD1289_YRES); vinfo->fmt = SSD1289_COLORFMT; /* Color format: RGB16-565: RRRR RGGG GGGB BBBB */ vinfo->xres = SSD1289_XRES; /* Horizontal resolution in pixel columns */ @@ -925,6 +925,7 @@ static inline int ssd1289_hwinitialize(FAR struct ssd1289_dev_s *priv) #ifndef CONFIG_LCD_NOGETRUN uint16_t id; #endif + int ret; /* Select the LCD */ @@ -1168,19 +1169,20 @@ static inline int ssd1289_hwinitialize(FAR struct ssd1289_dev_s *priv) /* One driver has a 50 msec delay here */ /* up_mdelay(50); */ - return OK; + ret = OK; } #ifndef CONFIG_LCD_NOGETRUN else { lcddbg("Unsupported LCD type\n"); - return -ENODEV; + ret = -ENODEV; } #endif /* De-select the LCD */ lcd->deselect(lcd); + return ret; } /************************************************************************************* diff --git a/nuttx/drivers/net/enc28j60.h b/nuttx/drivers/net/enc28j60.h index 6f7f8f4652..6a0553a95d 100644 --- a/nuttx/drivers/net/enc28j60.h +++ b/nuttx/drivers/net/enc28j60.h @@ -78,7 +78,7 @@ * * The last five locations (0x1b to 0x1f) of all banks point to a common set * of registers: EIE, EIR, ESTAT, ECON2 and ECON1. These are key registers - * usedin controlling and monitoring the operation of the device. Their + * used in controlling and monitoring the operation of the device. Their * common mapping allows easy access without switching the bank. * * Control registers for the ENC28J60 are generically grouped as ETH, MAC and diff --git a/nuttx/graphics/Kconfig b/nuttx/graphics/Kconfig index ae2bf31307..18b1e1ab97 100644 --- a/nuttx/graphics/Kconfig +++ b/nuttx/graphics/Kconfig @@ -2,3 +2,436 @@ # For a description of the syntax of this configuration file, # see misc/tools/kconfig-language.txt. # + +config NX + bool "NX Graphics" + default n + ---help--- + Enables overall support for graphics library and NX + +if NX + +config NX_LCDDRIVER + bool "LCD driver" + default y + depends on LCD + ---help--- + By default, the NX graphics system uses the frame buffer driver interface + defined in include/nuttx/fb.h. However, if LCD is support is enabled, + this this option is provide to select, instead, the LCD driver interface + defined in include/nuttx/lcd/lcd.h. + +config NX_NPLANES + int "Number of Color Planes" + default 1 + ---help--- + Some YUV color formats requires support for multiple planes, one for each + color component. Unless you have such special hardware, this value should be + undefined or set to 1. + +config NX_WRITEONLY + bool "Write-only Graphics Device" + default y if NX_LCDDRIVER && LCD_NOGETRUN + default n if !NX_LCDDRIVER || !LCD_NOGETRUN + ---help--- + Define if the underlying graphics device does not support read operations. + Automatically defined if NX_LCDDRIVER and LCD_NOGETRUN are + defined. + +menu "Supported Pixel Depths" + +config NX_DISABLE_1BPP + bool "1 BPP" + default y + ---help--- + NX supports a variety of pixel depths. You can save some memory by disabling + support for unused color depths. The selection disables support for 1BPP + pixel depth. + +config NX_DISABLE_2BPP + bool "2 BPP" + default y + ---help--- + NX supports a variety of pixel depths. You can save some memory by disabling + support for unused color depths. The selection disables support for 2BPP + pixel depth. + +config NX_DISABLE_4BPP + bool "4 BPP" + default y + ---help--- + NX supports a variety of pixel depths. You can save some memory by disabling + support for unused color depths. The selection disables support for 4BPP + pixel depth. + +config NX_DISABLE_8BPP + bool "8 BPP" + default y + ---help--- + NX supports a variety of pixel depths. You can save some memory by disabling + support for unused color depths. The selection disables support for 8BPP + pixel depth. + +config NX_DISABLE_16BPP + bool "16 BPP" + default y + ---help--- + NX supports a variety of pixel depths. You can save some memory by disabling + support for unused color depths. The selection disables support for 16BPP + pixel depth. + +config NX_DISABLE_24BPP + bool "24 BPP" + default y + ---help--- + NX supports a variety of pixel depths. You can save some memory by disabling + support for unused color depths. The selection disables support for 24BPP + pixel depth. + +config NX_DISABLE_32BPP + bool "32 BPP" + default y + ---help--- + NX supports a variety of pixel depths. You can save some memory by disabling + support for unused color depths. The selection disables support for 32BPP + pixel depth. + +endmenu + +config NX_PACKEDMSFIRST + bool "Packed MS First" + default y + depends on NX_DISABLE_1BPP || NX_DISABLE_2BPP || NX_DISABLE_4BPP + ---help--- + If a pixel depth of less than 8-bits is used, then NX needs to know if the + pixels pack from the MS to LS or from LS to MS + +menu "Input Devices" + +config NX_MOUSE + bool "Mouse/Touchscreen Support" + default n + ---help--- + Build in support for mouse or touchscreeninput. + +config NX_KBD + bool "Keyboard Support" + default n + ---help--- + Build in support of keypad/keyboard input. + +endmenu + +menu "Framed Window Borders" + +config NXTK_BORDERWIDTH + int "Border Width" + default 4 + ---help--- + Specifies with with of the border (in pixels) used with framed windows. + The default is 4. + +config NXTK_BORDERCOLOR1 + hex "Border Color" + default 0 + ---help--- + Specify the colors of the border used with framed windows. + NXTL_BODERCOLOR is the "normal" color of the border. + NXTK_BORDERCOLOR2 is the shadow side color and so is normally darker. + NXTK_BORDERCOLOR3 is the shiny side color and so is normally brighter. + +config NXTK_BORDERCOLOR2 + hex "Darker Border Color" + default 0 + ---help--- + Specify the colors of the border used with framed windows. + NXTL_BODERCOLOR is the "normal" color of the border. + NXTK_BORDERCOLOR2 is the shadow side color and so is normally darker. + NXTK_BORDERCOLOR3 is the shiny side color and so is normally brighter. + +config NXTK_BORDERCOLOR3 + hex "Brighter Border Color" + default 0 + ---help--- + Specify the colors of the border used with framed windows. + NXTL_BODERCOLOR is the "normal" color of the border. + NXTK_BORDERCOLOR2 is the shadow side color and so is normally darker. + NXTK_BORDERCOLOR3 is the shiny side color and so is normally brighter. + +endmenu + +config NXTK_AUTORAISE + bool "Autoraise" + default n + ---help--- + If set, a window will be raised to the top if the mouse position is over a + visible portion of the window. Default: A mouse button must be clicked over + a visible portion of the window. + +menu "Font Selections" + +config NXFONTS_CHARBITS + int "Bits in Character Set" + default 7 + range 7 8 + ---help--- + The number of bits in the character set. Current options are only 7 and 8. + The default is 7. + +config NXFONT_SANS17X22 + bool "Sans 17x22" + default n + ---help--- + This option enables support for a tiny, 17x22 san serif font + (font ID FONTID_SANS17X22 == 14). + +config NXFONT_SANS20X26 + bool "Sans 20x26" + default n + ---help--- + This option enables support for a tiny, 20x26 san serif font + (font ID FONTID_SANS20X26 == 15). + +config NXFONT_SANS23X27 + bool "Sans 23x27" + default n + ---help--- + This option enables support for a tiny, 23x27 san serif font + (font ID FONTID_SANS23X27 == 1). + +config NXFONT_SANS22X29 + bool "Sans 22x29" + default n + ---help--- + This option enables support for a small, 22x29 san serif font + (font ID FONTID_SANS22X29 == 2). + +config NXFONT_SANS28X37 + bool "Sans 28x37" + default n + ---help--- + This option enables support for a medium, 28x37 san serif font + (font ID FONTID_SANS28X37 == 3). + +config NXFONT_SANS39X48 + bool "Sans 39x48" + default n + ---help--- + This option enables support for a large, 39x48 san serif font + (font ID FONTID_SANS39X48 == 4). + +config NXFONT_SANS17X23B + bool "Sans 17x23 Bold" + default n + ---help--- + This option enables support for a tiny, 17x23 san serif bold font + (font ID FONTID_SANS17X23B == 16). + +config NXFONT_SANS20X27B + bool "Sans 20x27 Bold" + default n + ---help--- + This option enables support for a tiny, 20x27 san serif bold font + (font ID FONTID_SANS20X27B == 17). + +config NXFONT_SANS22X29B + bool "Sans 22x29 Bold" + default n + ---help--- + This option enables support for a small, 22x29 san serif bold font + (font ID FONTID_SANS22X29B == 5). + +config NXFONT_SANS28X37B + bool "Sans 28x37 Bold" + default n + ---help--- + This option enables support for a medium, 28x37 san serif bold font + (font ID FONTID_SANS28X37B == 6). + +config NXFONT_SANS40X49B + bool "Sans 40x49 Bold" + default n + ---help--- + This option enables support for a large, 40x49 san serif bold font + (font ID FONTID_SANS40X49B == 7). + +config NXFONT_SERIF22X29 + bool "Serif 22x29" + default n + ---help--- + This option enables support for a small, 22x29 font (with serifs) + (font ID FONTID_SERIF22X29 == 8). + +config NXFONT_SERIF29X37 + bool "Serif 29x37" + default n + ---help--- + This option enables support for a medium, 29x37 font (with serifs) + (font ID FONTID_SERIF29X37 == 9). + +config NXFONT_SERIF38X48 + bool "Serif 38x48" + default n + ---help--- + This option enables support for a large, 38x48 font (with serifs) + (font ID FONTID_SERIF38X48 == 10). + +config NXFONT_SERIF22X28B + bool "Serif 22x28 Bold" + default n + ---help--- + This option enables support for a small, 27x38 bold font (with serifs) + (font ID FONTID_SERIF22X28B == 11). + +config NXFONT_SERIF27X38B + bool "Serif 27x38 Bold" + default n + ---help--- + This option enables support for a medium, 27x38 bold font (with serifs) + (font ID FONTID_SERIF27X38B == 12). + +config NXFONT_SERIF38X49B + bool "Serif 38x49 Bold" + default n + ---help--- + This option enables support for a large, 38x49 bold font (with serifs) + (font ID FONTID_SERIF38X49B == 13). + +endmenu + +menuconfig NXCONSOLE + bool "NxConsole" + default n + ---help--- + Enables building of the NxConsole driver. + +if NXCONSOLE + +comment "NxConsole Output Text/Graphics Options" + +config NXCONSOLE_BPP + int "NxConsole BPP" + default 1 if !NX_DISABLE_1BPP + default 2 if !NX_DISABLE_2BPP + default 4 if !NX_DISABLE_4BPP + default 8 if !NX_DISABLE_8BPP + default 16 if !NX_DISABLE_16BPP + default 24 if !NX_DISABLE_24BPP + default 32 if !NX_DISABLE_32BPP + ---help--- + Currently, NxConsole supports only a single pixel depth. This + configuration setting must be provided to support that single pixel depth. + Default: The smallest enabled pixel depth. (see NX_DISABLE_*BPP) + +config NXCONSOLE_CURSORCHAR + int "Character code to use as the cursor" + default 137 + ---help--- + The bitmap code to use as the cursor. Default '_' (137) + +config NXCONSOLE_MXCHARS + int "Max Characters on Display" + default 128 + ---help--- + NxConsole needs to remember every character written to the console so + that it can redraw the window. This setting determines the size of some + internal memory allocations used to hold the character data. Default: 128. + +config NXCONSOLE_CACHESIZE + int "Font Cache Size" + default 16 + ---help--- + NxConsole supports caching of rendered fonts. This font caching is required + for two reasons: (1) First, it improves text performance, but more + importantly (2) it preserves the font memory. Since the NX server runs on + a separate server thread, it requires that the rendered font memory persist + until the server has a chance to render the font. Unfortunately, the font + cache would be quite large if all fonts were saved. The NXCONSOLE_CACHESIZE + setting will control the size of the font cache (in number of glyphs). Only that + number of the most recently used glyphs will be retained. Default: 16. + NOTE: There can still be a race condition between the NxConsole driver and the + NX task. If you every see character corruption (especially when printing + a lot of data or scrolling), then increasing the value of NXCONSOLE_CACHESIZE + is something that you should try. Alternatively, you can reduce the size of + MQ_MAXMSGSIZE which will force NxConsole task to pace the server task. + NXCONSOLE_CACHESIZE should be larger than MQ_MAXMSGSIZE in any event. + +config NXCONSOLE_LINESEPARATION + int "Line Separation" + default 0 + ---help--- + This the space (in rows) between each row of test. Default: 0 + +config NXCONSOLE_NOWRAP + bool "No wrap" + default n + ---help--- + By default, lines will wrap when the test reaches the right hand side + of the window. This setting can be defining to change this behavior so + that the text is simply truncated until a new line is encountered. + +comment "NxConsole Input options" + +config NXCONSOLE_NXKBDIN + bool "NX KBD input" + default n + ---help--- + Take input from the NX keyboard input callback. By default, keyboard + input is taken from stdin (/dev/console). If this option is set, then + the interface nxcon_kdbin() is enabled. That interface may be driven + by window callback functions so that keyboard input *only* goes to the + top window. + +config NXCONSOLE_KBDBUFSIZE + int "Keyboard Input Buffer Size" + default 16 + ---help--- + If NXCONSOLE_NXKBDIN is enabled, then this value may be used to + define the size of the per-window keyboard input buffer. Default: 16 + +config NXCONSOLE_NPOLLWAITERS + int "Number of Poll Waiters" + default 4 + ---help--- + The number of threads that can be waiting for read data available. + Default: 4 + +endif + +comment "NX Multi-user only options" + +menuconfig NX_MULTIUSER + bool "Multi-user NX Server" + default n + ---help--- + Configures NX in multi-user mode + +if NX_MULTIUSER + +config NX_BLOCKING + bool "Blocking" + default n + ---help--- + Open the client message queues in blocking mode. In this case, + nx_eventhandler() will not return until a message is received and processed. + +config NX_MXSERVERMSGS + int "Max Server Messages" + default 32 + ---help--- + Specifies the maximum number of messages that can fit in the message queues. + No additional resources are allocated, but this can be set to prevent + flooding of the client or server with too many messages (PREALLOC_MQ_MSGS + controls how many messages are pre-allocated). + +config NX_MXCLIENTMSGS + int "Max Client Messages" + default 16 + ---help--- + Specifies the maximum number of messages that can fit in the message queues. + No additional resources are allocated, but this can be set to prevent + flooding of the client or server with too many messages (PREALLOC_MQ_MSGS + controls how many messages are pre-allocated). + +endif +endif diff --git a/nuttx/graphics/nxmu/nx_block.c b/nuttx/graphics/nxmu/nx_block.c index 2f069f0962..3a051f9d7d 100644 --- a/nuttx/graphics/nxmu/nx_block.c +++ b/nuttx/graphics/nxmu/nx_block.c @@ -111,8 +111,8 @@ int nx_block(NXWINDOW hwnd, FAR void *arg) #ifdef CONFIG_DEBUG if (!hwnd) { - errno = EINVAL; - return NULL; + set_errno(EINVAL); + return ERROR; } #endif diff --git a/nuttx/graphics/nxmu/nxmu_sendclient.c b/nuttx/graphics/nxmu/nxmu_sendclient.c index 8b7f121042..a59fa23634 100644 --- a/nuttx/graphics/nxmu/nxmu_sendclient.c +++ b/nuttx/graphics/nxmu/nxmu_sendclient.c @@ -93,9 +93,9 @@ int nxmu_sendclient(FAR struct nxfe_conn_s *conn, FAR const void *msg, /* Sanity checking */ #ifdef CONFIG_DEBUG - if (!conn || conn->swrmq) + if (!conn || !conn->swrmq) { - errno = EINVAL; + set_errno(EINVAL); return ERROR; } #endif diff --git a/nuttx/graphics/nxmu/nxmu_sendserver.c b/nuttx/graphics/nxmu/nxmu_sendserver.c index 7007b81da9..03ece4e7f7 100644 --- a/nuttx/graphics/nxmu/nxmu_sendserver.c +++ b/nuttx/graphics/nxmu/nxmu_sendserver.c @@ -93,9 +93,9 @@ int nxmu_sendserver(FAR struct nxfe_conn_s *conn, FAR const void *msg, /* Sanity checking */ #ifdef CONFIG_DEBUG - if (!conn || conn->cwrmq) + if (!conn || !conn->cwrmq) { - errno = EINVAL; + set_errno(EINVAL); return ERROR; } #endif diff --git a/nuttx/lib/stdio/lib_sscanf.c b/nuttx/lib/stdio/lib_sscanf.c index 01c96c21dd..7e1fae276d 100644 --- a/nuttx/lib/stdio/lib_sscanf.c +++ b/nuttx/lib/stdio/lib_sscanf.c @@ -1,7 +1,7 @@ /**************************************************************************** * lib/stdio/lib_sscanf.c * - * Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2007, 2008, 2011-2012 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -38,9 +38,11 @@ ****************************************************************************/ #include + #include #include #include +#include #include #include #include @@ -63,7 +65,7 @@ * Global Function Prototypes ****************************************************************************/ -int vsscanf(char *buf, const char *s, va_list ap); +int vsscanf(char *buf, const char *fmt, va_list ap); /************************************************************************** * Global Constant Data @@ -79,6 +81,64 @@ int vsscanf(char *buf, const char *s, va_list ap); static const char spaces[] = " \t\n\r\f\v"; +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: findwidth + * + * Description: + * Try to figure out the width of the input data. + * + ****************************************************************************/ + +static int findwidth(FAR const char *buf, FAR const char *fmt) +{ + FAR const char *next = fmt + 1; + + /* No... is there a space after the format? Or does the format string end + * here? + */ + + if (isspace(*next) || *next == 0) + { + /* Use the input up until the first white space is encountered. */ + + return strcspn(buf, spaces); + } + + /* No.. Another possibility is the the format character is followed by + * some recognizable delimiting value. + */ + + if (*next != '%') + { + /* If so we will say that the string ends there if we can find that + * delimiter in the input string. + */ + + FAR const char *ptr = strchr(buf, *next); + if (ptr) + { + return (int)(ptr - buf); + } + } + + /* No... the format has not delimiter and is back-to-back with the next + * formats (or no is following by a delimiter that does not exist in the + * input string). At this point we just bail and Use the input up until + * the first white space is encountered. + * + * NOTE: This means that values from the following format may be + * concatenated with the first. This is a bug. We have no generic way of + * determining the width of the data if there is no fieldwith, no space + * separating the input, and no usable delimiter character. + */ + + return strcspn(buf, spaces); +} + /**************************************************************************** * Private Variables ****************************************************************************/ @@ -109,67 +169,83 @@ int sscanf(FAR const char *buf, FAR const char *fmt, ...) * ANSI standard vsscanf implementation. * ****************************************************************************/ -int vsscanf(FAR char *buf, FAR const char *s, va_list ap) + +int vsscanf(FAR char *buf, FAR const char *fmt, va_list ap) { - int count; - int noassign; - int width; - int base = 10; - int lflag; + FAR char *bufstart; FAR char *tv; FAR const char *tc; + bool lflag; + bool noassign; + int count; + int width; + int base = 10; char tmp[MAXLN]; - lvdbg("vsscanf: buf=\"%s\" fmt=\"%s\"\n", buf, s); + lvdbg("vsscanf: buf=\"%s\" fmt=\"%s\"\n", buf, fmt); - count = noassign = width = lflag = 0; - while (*s && *buf) + /* Remember the start of the input buffer. We will need this for %n + * calculations. + */ + + bufstart = buf; + + /* Parse the format, extracting values from the input buffer as needed */ + + count = 0; + width = 0; + noassign = false; + lflag = false; + + while (*fmt && *buf) { /* Skip over white space */ - while (isspace(*s)) + while (isspace(*fmt)) { - s++; + fmt++; } /* Check for a conversion specifier */ - if (*s == '%') + if (*fmt == '%') { lvdbg("vsscanf: Specifier found\n"); /* Check for qualifiers on the conversion specifier */ - s++; - for (; *s; s++) + fmt++; + for (; *fmt; fmt++) { - lvdbg("vsscanf: Processing %c\n", *s); + lvdbg("vsscanf: Processing %c\n", *fmt); - if (strchr("dibouxcsefg%", *s)) + if (strchr("dibouxcsefgn%", *fmt)) { break; } - if (*s == '*') + if (*fmt == '*') { - noassign = 1; + noassign = true; } - else if (*s == 'l' || *s == 'L') + else if (*fmt == 'l' || *fmt == 'L') { - lflag = 1; + /* NOTE: Missing check for long long ('ll') */ + + lflag = true; } - else if (*s >= '1' && *s <= '9') + else if (*fmt >= '1' && *fmt <= '9') { - for (tc = s; isdigit(*s); s++); - strncpy(tmp, tc, s - tc); - tmp[s - tc] = '\0'; + for (tc = fmt; isdigit(*fmt); fmt++); + strncpy(tmp, tc, fmt - tc); + tmp[fmt - tc] = '\0'; width = atoi(tmp); - s--; + fmt--; } } /* Process %s: String conversion */ - if (*s == 's') + if (*fmt == 's') { lvdbg("vsscanf: Performing string conversion\n"); @@ -178,9 +254,13 @@ int vsscanf(FAR char *buf, FAR const char *s, va_list ap) buf++; } + /* Was a fieldwidth specified? */ + if (!width) { - width = strcspn(buf, spaces); + /* No... Guess a field width using some heuristics */ + + width = findwidth(buf, fmt); } if (!noassign) @@ -189,17 +269,22 @@ int vsscanf(FAR char *buf, FAR const char *s, va_list ap) strncpy(tv, buf, width); tv[width] = '\0'; } + buf += width; } /* Process %c: Character conversion */ - else if (*s == 'c') + else if (*fmt == 'c') { lvdbg("vsscanf: Performing character conversion\n"); + /* Was a fieldwidth specified? */ + if (!width) { + /* No, then width is this one single character */ + width = 1; } @@ -209,12 +294,13 @@ int vsscanf(FAR char *buf, FAR const char *s, va_list ap) strncpy(tv, buf, width); tv[width] = '\0'; } + buf += width; } /* Process %d, %o, %b, %x, %u: Various integer conversions */ - else if (strchr("dobxu", *s)) + else if (strchr("dobxu", *fmt)) { lvdbg("vsscanf: Performing integer conversion\n"); @@ -229,37 +315,34 @@ int vsscanf(FAR char *buf, FAR const char *s, va_list ap) * conversion specification. */ - if (*s == 'd' || *s == 'u') + if (*fmt == 'd' || *fmt == 'u') { base = 10; } - else if (*s == 'x') + else if (*fmt == 'x') { base = 16; } - else if (*s == 'o') + else if (*fmt == 'o') { base = 8; } - else if (*s == 'b') + else if (*fmt == 'b') { base = 2; } - /* Copy the integer string into a temporary working buffer. */ + /* Was a fieldwidth specified? */ if (!width) { - if (isspace(*(s + 1)) || *(s + 1) == 0) - { - width = strcspn(buf, spaces); - } - else - { - width = strchr(buf, *(s + 1)) - buf; - } + /* No... Guess a field width using some heuristics */ + + width = findwidth(buf, fmt); } + /* Copy the numeric string into a temporary working buffer. */ + strncpy(tmp, buf, width); tmp[width] = '\0'; @@ -270,21 +353,30 @@ int vsscanf(FAR char *buf, FAR const char *s, va_list ap) buf += width; if (!noassign) { - int *pint = va_arg(ap, int*); #ifdef SDCC char *endptr; - int tmpint = strtol(tmp, &endptr, base); + long tmplong = strtol(tmp, &endptr, base); #else - int tmpint = strtol(tmp, NULL, base); + long tmplong = strtol(tmp, NULL, base); #endif - lvdbg("vsscanf: Return %d to 0x%p\n", tmpint, pint); - *pint = tmpint; + if (lflag) + { + long *plong = va_arg(ap, long*); + lvdbg("vsscanf: Return %ld to 0x%p\n", tmplong, plong); + *plong = tmplong; + } + else + { + int *pint = va_arg(ap, int*); + lvdbg("vsscanf: Return %ld to 0x%p\n", tmplong, pint); + *pint = (int)tmplong; + } } } /* Process %f: Floating point conversion */ - else if (*s == 'f') + else if (*fmt == 'f') { #ifndef CONFIG_LIBC_FLOATINGPOINT /* No floating point conversions */ @@ -303,20 +395,17 @@ int vsscanf(FAR char *buf, FAR const char *s, va_list ap) buf++; } - /* Copy the real string into a temporary working buffer. */ + /* Was a fieldwidth specified? */ if (!width) { - if (isspace(*(s + 1)) || *(s + 1) == 0) - { - width = strcspn(buf, spaces); - } - else - { - width = strchr(buf, *(s + 1)) - buf; - } + /* No... Guess a field width using some heuristics */ + + width = findwidth(buf, fmt); } + /* Copy the real string into a temporary working buffer. */ + strncpy(tmp, buf, width); tmp[width] = '\0'; buf += width; @@ -356,13 +445,41 @@ int vsscanf(FAR char *buf, FAR const char *s, va_list ap) #endif } - if (!noassign) + /* Process %n: Character count */ + + else if (*fmt == 'n') + { + lvdbg("vsscanf: Performing character count\n"); + + if (!noassign) + { + size_t nchars = (size_t)(buf - bufstart); + + if (lflag) + { + long *plong = va_arg(ap, long*); + *plong = (long)nchars; + } + else + { + int *pint = va_arg(ap, int*); + *pint = (int)nchars; + } + } + } + + /* Note %n does not count as a conversion */ + + if (!noassign && *fmt != 'n') { count++; } - width = noassign = lflag = 0; - s++; + width = 0; + noassign = false; + lflag = false; + + fmt++; } /* Its is not a conversion specifier */ @@ -374,13 +491,13 @@ int vsscanf(FAR char *buf, FAR const char *s, va_list ap) buf++; } - if (*s != *buf) + if (*fmt != *buf) { break; } else { - s++; + fmt++; buf++; } } diff --git a/nuttx/tools/cfgparser.c b/nuttx/tools/cfgparser.c index e49b29d5e4..b1f189f6fb 100644 --- a/nuttx/tools/cfgparser.c +++ b/nuttx/tools/cfgparser.c @@ -56,13 +56,24 @@ char line[LINESIZE+1]; ****************************************************************************/ /* These are configuration variable name that are quoted by configuration tool - * but which must be unquoated when used in C code. + * but which must be unquoted when used in C code. */ static const char *dequote_list[] = { - "CONFIG_USER_ENTRYPOINT", - NULL + /* NuttX */ + + "CONFIG_USER_ENTRYPOINT", /* Name of entry point function */ + + /* NxWidgets/NxWM */ + + "CONFIG_NXWM_BACKGROUND_IMAGE", /* Name of bitmap image class */ + "CONFIG_NXWM_STARTWINDOW_ICON", /* Name of bitmap image class */ + "CONFIG_NXWM_NXCONSOLE_ICON", /* Name of bitmap image class */ + "CONFIG_NXWM_CALIBRATION_ICON", /* Name of bitmap image class */ + "CONFIG_NXWM_HEXCALCULATOR_ICON", /* Name of bitmap image class */ + + NULL /* Marks the end of the list */ }; /**************************************************************************** @@ -239,7 +250,7 @@ static char *dequote_value(const char *varname, char *varval) /* Handle the case where nothing is left after dequoting */ - if (len < 0) + if (len <= 0) { dqval = NULL; }