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same70 micro hal
This commit is contained in:
committed by
Daniel Agar
parent
c536bf95f0
commit
5f9b23b475
@@ -34,6 +34,7 @@
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/*
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* This file is a shim to bridge to nuttx_v3
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*/
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#ifdef __PX4_NUTTX
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__BEGIN_DECLS
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#include <nuttx/spi/spi.h>
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@@ -93,7 +94,7 @@ __BEGIN_DECLS
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/* The mfguid will be an array of bytes with
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* MSD @ index 0 - LSD @ index PX4_CPU_MFGUID_BYTE_LENGTH-1
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*
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* It wil be conferted to a string with the MSD on left and LSD on the right most position.
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* It will be converted to a string with the MSD on left and LSD on the right most position.
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*/
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# define PX4_CPU_MFGUID_BYTE_LENGTH PX4_CPU_UUID_BYTE_LENGTH
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@@ -165,7 +166,7 @@ __BEGIN_DECLS
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*/
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# define PX4_CPU_MFGUID_BYTE_LENGTH PX4_CPU_UUID_BYTE_LENGTH
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/* define common formating accross all commands */
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/* define common formating across all commands */
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# define PX4_CPU_UUID_WORD32_FORMAT "%08x"
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# define PX4_CPU_UUID_WORD32_SEPARATOR ":"
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@@ -196,6 +197,65 @@ __BEGIN_DECLS
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# define px4_arch_gpiowrite(pinset, value) kinetis_gpiowrite(pinset, value)
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# define px4_arch_gpiosetevent(pinset,r,f,e,fp) kinetis_gpiosetevent(pinset,r,f, e,fp)
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# endif
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# if defined(CONFIG_ARCH_CHIP_SAMV7)
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# include <sam_spi.h>
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# include <sam_twihs.h>
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# // Fixme: using ??
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# define PX4_BBSRAM_SIZE 2048
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# define PX4_BBSRAM_GETDESC_IOCTL 0
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//todo:define this for Atmel and add loader.
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/* Atmel defines the 128 bit UUID as
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* init8_t[8] that can be read as bytes using Start Read Unique Identifier
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*
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* PX4 uses the bytes in bigendian order MSB to LSB
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* word [0] [1] [2] [3]
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* bits 127:96 95-64 63-32, 31-00,
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*/
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# define PX4_CPU_UUID_BYTE_LENGTH 16
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# define PX4_CPU_UUID_WORD32_LENGTH (PX4_CPU_UUID_BYTE_LENGTH/sizeof(uint32_t))
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/* The mfguid will be an array of bytes with
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* MSD @ index 0 - LSD @ index PX4_CPU_MFGUID_BYTE_LENGTH-1
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*
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* It will be converted to a string with the MSD on left and LSD on the right most position.
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*/
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# define PX4_CPU_MFGUID_BYTE_LENGTH PX4_CPU_UUID_BYTE_LENGTH
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/* define common formating across all commands */
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# define PX4_CPU_UUID_WORD32_FORMAT "%08x"
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# define PX4_CPU_UUID_WORD32_SEPARATOR ":"
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# define PX4_CPU_UUID_WORD32_UNIQUE_H 3 /* Least significant digits change the most */
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# define PX4_CPU_UUID_WORD32_UNIQUE_M 2 /* Middle High significant digits */
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# define PX4_CPU_UUID_WORD32_UNIQUE_L 1 /* Middle Low significant digits */
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# define PX4_CPU_UUID_WORD32_UNIQUE_N 0 /* Most significant digits change the least */
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/* Separator nnn:nnn:nnnn 2 char per byte term */
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# define PX4_CPU_UUID_WORD32_FORMAT_SIZE (PX4_CPU_UUID_WORD32_LENGTH-1+(2*PX4_CPU_UUID_BYTE_LENGTH)+1)
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# define PX4_CPU_MFGUID_FORMAT_SIZE ((2*PX4_CPU_MFGUID_BYTE_LENGTH)+1)
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# define atmel_bbsram_savepanic(fileno, context, length) (0) // todo:Not implemented yet
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# define px4_savepanic(fileno, context, length) atmel_bbsram_savepanic(fileno, context, length)
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/* bus_num is zero based on same70 and must be translated from the legacy one based */
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# define px4_spibus_initialize(port_1based) sam_spibus_initialize(port_1based-1)
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# define px4_i2cbus_initialize(bus_num_1based) sam_i2cbus_initialize(bus_num_1based-1)
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# define px4_i2cbus_uninitialize(pdev) sam_i2cbus_uninitialize(pdev)
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# define px4_arch_configgpio(pinset) sam_configgpio(pinset)
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# define px4_arch_unconfiggpio(pinset) sam_unconfiggpio(pinset)
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# define px4_arch_gpioread(pinset) sam_gpioread(pinset)
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# define px4_arch_gpiowrite(pinset, value) sam_gpiowrite(pinset, value)
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# define px4_arch_gpiosetevent(pinset,r,f,e,fp) sam_gpiosetevent(pinset,r,f, e,fp)
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# endif
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#include <arch/board/board.h>
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__END_DECLS
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#endif
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