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git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5153 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
2012-09-17 18:18:44 +00:00
commit 57623d42eb
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nuttx/drivers/net/Kconfig
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#
# For a description of the syntax of this configuration file,
# see misc/tools/kconfig-language.txt.
#
config NET_DM90x0
bool "Davicom dm9000/dm9010 support"
default n
---help---
References: Davicom data sheets (DM9000-DS-F03-041906.pdf,
DM9010-DS-F01-103006.pdf) and looking at lots of other DM90x0
drivers.
config NET_CS89x0
bool "CS89x0 support"
default n
depends on EXPERIMENTAL
---help---
Under construction -- do not use
config ENC28J60
bool "Microchip ENC28J60 support"
default n
select SPI
---help---
References:
ENC28J60 Data Sheet, Stand-Alone Ethernet Controller with SPI Interface,
DS39662C, 2008 Microchip Technology Inc.
if ENC28J60
config ENC28J60_NINTERFACES
int "Number of physical ENC28J60"
default 1
range 1,1
---help---
Specifies the number of physical ENC28J60
devices that will be supported.
config ENC28J60_SPIMODE
int "SPI mode"
default 0
---help---
Controls the SPI mode. The ENC28J60 spec says that it supports SPI
mode 0,0 only: "The implementation used on this device supports SPI
mode 0,0 only. In addition, the SPI port requires that SCK be at Idle
in a low state; selectable clock polarity is not supported."
However, sometimes you need to tinker with these things.
config ENC28J60_FREQUENCY
int "SPI frequency"
default 20000000
---help---
Define to use a different bus frequency
config ENC28J60_STATS
bool "Network statistics support"
default n
---help---
Collect network statistics
config ENC28J60_HALFDUPPLEX
bool "Enable half dupplex"
default n
---help---
Default is full duplex
endif
config NET_E1000
bool "E1000 support"
default n
config NET_SLIP
bool "SLIP (serial line) support"
default n
---help---
Reference: RFC 1055
config NET_VNET
bool "VNET support"
default n
nuttx/drivers/net/Make.defs
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############################################################################
# drivers/net/Make.defs
#
# Copyright (C) 2007, 2010-2012 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
############################################################################
# Include nothing if networking is disabled
ifeq ($(CONFIG_NET),y)
# Include network interface drivers
ifeq ($(CONFIG_NET_DM90x0),y)
CSRCS += dm90x0.c
endif
ifeq ($(CONFIG_NET_CS89x0),y)
CSRCS += cs89x0.c
endif
ifeq ($(CONFIG_ENC28J60),y)
CSRCS += enc28j60.c
endif
ifeq ($(CONFIG_NET_VNET),y)
CSRCS += vnet.c
endif
ifeq ($(CONFIG_NET_E1000),y)
CSRCS += e1000.c
endif
ifeq ($(CONFIG_NET_SLIP),y)
CSRCS += slip.c
endif
# Include network build support
DEPPATH += --dep-path net
VPATH += :net
endif
nuttx/drivers/net/cs89x0.c
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/****************************************************************************
* drivers/net/cs89x0.c
*
* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_NET) && defined(CONFIG_NET_CS89x0)
#include <stdint.h>
#include <stdbool.h>
#include <time.h>
#include <string.h>
#include <debug.h>
#include <wdog.h>
#include <errno.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/net/uip/uip.h>
#include <nuttx/net/uip/uip-arp.h>
#include <nuttx/net/uip/uip-arch.h>
/****************************************************************************
* Definitions
****************************************************************************/
#error "Under construction -- do not use"
/* CONFIG_CS89x0_NINTERFACES determines the number of physical interfaces
* that will be supported.
*/
#ifndef CONFIG_CS89x0_NINTERFACES
# define CONFIG_CS89x0_NINTERFACES 1
#endif
/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per second */
#define CS89x0_WDDELAY (1*CLK_TCK)
#define CS89x0_POLLHSEC (1*2)
/* TX timeout = 1 minute */
#define CS89x0_TXTIMEOUT (60*CLK_TCK)
/* This is a helper pointer for accessing the contents of the Ethernet header */
#define BUF ((struct uip_eth_hdr *)cs89x0->cs_dev.d_buf)
/* If there is only one CS89x0 instance, then mapping the CS89x0 IRQ to
* a driver state instance is trivial.
*/
#if CONFIG_CS89x0_NINTERFACES == 1
# define cs89x0_mapirq(irq) g_cs89x0[0]
#endif
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
static FAR struct cs89x0_driver_s *g_cs89x0[CONFIG_CS89x0_NINTERFACES];
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* CS89x0 register access */
static uint16_t cs89x0_getreg(struct cs89x0_driver_s *cs89x0, int offset);
static void cs89x0_putreg(struct cs89x0_driver_s *cs89x0, int offset,
uint16_t value);
static uint16_t cs89x0_getppreg(struct cs89x0_driver_s *cs89x0, int addr);
static void cs89x0_putppreg(struct cs89x0_driver_s *cs89x0, int addr,
uint16_t value);
/* Common TX logic */
static int cs89x0_transmit(struct cs89x0_driver_s *cs89x0);
static int cs89x0_uiptxpoll(struct uip_driver_s *dev);
/* Interrupt handling */
static void cs89x0_receive(struct cs89x0_driver_s *cs89x0);
static void cs89x0_txdone(struct cs89x0_driver_s *cs89x0, uint16_t isq);
#if CONFIG_CS89x0_NINTERFACES > 1
static inline FAR struct cs89x0_driver_s *cs89x0_mapirq(int irq);
#endif
static int cs89x0_interrupt(int irq, FAR void *context);
/* Watchdog timer expirations */
static void cs89x0_polltimer(int argc, uint32_t arg, ...);
static void cs89x0_txtimeout(int argc, uint32_t arg, ...);
/* NuttX callback functions */
static int cs89x0_ifup(struct uip_driver_s *dev);
static int cs89x0_ifdown(struct uip_driver_s *dev);
static int cs89x0_txavail(struct uip_driver_s *dev);
#ifdef CONFIG_NET_IGMP
static int cs89x0_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac);
static int cs89x0_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac);
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Function: cs89x0_getreg and cs89x0_putreg
*
* Description:
* Read from and write to a CS89x0 register
*
* Parameters:
* cs89x0 - Reference to the driver state structure
* offset - Offset to the CS89x0 register
* value - Value to be written (cs89x0_putreg only)
*
* Returned Value:
* cs89x0_getreg: The 16-bit value of the register
* cs89x0_putreg: None
*
****************************************************************************/
static uint16_t cs89x0_getreg(struct cs89x0_driver_s *cs89x0, int offset)
{
#ifdef CONFIG_CS89x0_ALIGN16
return getreg16(s89x0->cs_base + offset);
#else
return (uint16_t)getreg32(s89x0->cs_base + offset);
#endif
}
static void cs89x0_putreg(struct cs89x0_driver_s *cs89x0, int offset, uint16_t value)
{
#ifdef CONFIG_CS89x0_ALIGN16
return putreg16(value, s89x0->cs_base + offset);
#else
return (uint16_t)putreg32((uint32_t)value, s89x0->cs_base + offset);
#endif
}
/****************************************************************************
* Function: cs89x0_getppreg and cs89x0_putppreg
*
* Description:
* Read from and write to a CS89x0 page packet register
*
* Parameters:
* cs89x0 - Reference to the driver state structure
* addr - Address of the CS89x0 page packet register
* value - Value to be written (cs89x0_putppreg only)
*
* Returned Value:
* cs89x0_getppreg: The 16-bit value of the page packet register
* cs89x0_putppreg: None
*
****************************************************************************/
static uint16_t cs89x0_getppreg(struct cs89x0_driver_s *cs89x0, int addr)
{
/* In memory mode, the CS89x0's internal registers and frame buffers are mapped
* into a contiguous 4kb block providing direct access to the internal registers
* and frame buffers.
*/
#ifdef CONFIG_CS89x0_MEMMODE
if (cs89x0->cs_memmode)
{
#ifdef CONFIG_CS89x0_ALIGN16
return getreg16(s89x0->cs_ppbase + (CS89x0_PDATA_OFFSET << ??));
#else
return (uint16_t)getreg32(s89x0->cs_ppbase + (CS89x0_PDATA_OFFSET << ??));
#endif
}
/* When configured in I/O mode, the CS89x0 is accessed through eight, 16-bit
* I/O ports that in the host system's I/O space.
*/
else
#endif
{
#ifdef CONFIG_CS89x0_ALIGN16
putreg16((uint16_t)addr, cs89x0->cs_base + CS89x0_PPTR_OFFSET);
return getreg16(s89x0->cs_base + CS89x0_PDATA_OFFSET);
#else
putreg32((uint32_t)addr, cs89x0->cs_base + CS89x0_PPTR_OFFSET);
return (uint16_t)getreg32(s89x0->cs_base + CS89x0_PDATA_OFFSET);
#endif
}
}
static void cs89x0_putppreg(struct cs89x0_driver_s *cs89x0, int addr, uint16_t value)
{
/* In memory mode, the CS89x0's internal registers and frame buffers are mapped
* into a contiguous 4kb block providing direct access to the internal registers
* and frame buffers.
*/
#ifdef CONFIG_CS89x0_MEMMODE
if (cs89x0->cs_memmode)
{
#ifdef CONFIG_CS89x0_ALIGN16
putreg16(value), cs89x0->cs_ppbase + (CS89x0_PDATA_OFFSET << ??));
#else
putreg32((uint32_t)value, cs89x0->cs_ppbase + (CS89x0_PDATA_OFFSET << ??));
#endif
}
/* When configured in I/O mode, the CS89x0 is accessed through eight, 16-bit
* I/O ports that in the host system's I/O space.
*/
else
#endif
{
#ifdef CONFIG_CS89x0_ALIGN16
putreg16((uint16_t)addr, cs89x0->cs_base + CS89x0_PPTR_OFFSET);
putreg16(value, cs89x0->cs_base + CS89x0_PDATA_OFFSET);
#else
putreg32((uint32_t)addr, cs89x0->cs_base + CS89x0_PPTR_OFFSET);
putreg32((uint32_t)value, cs89x0->cs_base + CS89x0_PDATA_OFFSET);
#endif
}
}
/****************************************************************************
* Function: cs89x0_transmit
*
* Description:
* Start hardware transmission. Called either from the txdone interrupt
* handling or from watchdog based polling.
*
* Parameters:
* cs89x0 - Reference to the driver state structure
*
* Returned Value:
* OK on success; a negated errno on failure
*
* Assumptions:
*
****************************************************************************/
static int cs89x0_transmit(struct cs89x0_driver_s *cs89x0)
{
/* Verify that the hardware is ready to send another packet */
#warning "Missing logic"
/* Increment statistics */
#warning "Missing logic"
/* Disable Ethernet interrupts */
#warning "Missing logic"
/* Send the packet: address=cs89x0->cs_dev.d_buf, length=cs89x0->cs_dev.d_len */
#warning "Missing logic"
/* Restore Ethernet interrupts */
#warning "Missing logic"
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
(void)wd_start(cs89x0->cs_txtimeout, CS89x0_TXTIMEOUT, cs89x0_txtimeout, 1, (uint32_t)cs89x0);
return OK;
}
/****************************************************************************
* Function: cs89x0_uiptxpoll
*
* Description:
* The transmitter is available, check if uIP has any outgoing packets ready
* to send. This is a callback from uip_poll(). uip_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
* 2. When the preceding TX packet send timesout and the interface is reset
* 3. During normal TX polling
*
* Parameters:
* dev - Reference to the NuttX driver state structure
*
* Returned Value:
* OK on success; a negated errno on failure
*
* Assumptions:
*
****************************************************************************/
static int cs89x0_uiptxpoll(struct uip_driver_s *dev)
{
struct cs89x0_driver_s *cs89x0 = (struct cs89x0_driver_s *)dev->d_private;
/* If the polling resulted in data that should be sent out on the network,
* the field d_len is set to a value > 0.
*/
if (cs89x0->cs_dev.d_len > 0)
{
uip_arp_out(&cs89x0->cs_dev);
cs89x0_transmit(cs89x0);
/* Check if there is room in the CS89x0 to hold another packet. If not,
* return a non-zero value to terminate the poll.
*/
#warning "Missing logic"
}
/* If zero is returned, the polling will continue until all connections have
* been examined.
*/
return 0;
}
/****************************************************************************
* Function: cs89x0_receive
*
* Description:
* An interrupt was received indicating the availability of a new RX packet
*
* Parameters:
* cs89x0 - Reference to the driver state structure
* isq - Interrupt status queue value read by interrupt handler
*
* Returned Value:
* None
*
* Assumptions:
*
****************************************************************************/
static void cs89x0_receive(struct cs89x0_driver_s *cs89x0, uint16_t isq)
{
uint16_t *dest;
uint16_t rxlength;
int nbytes;
/* Check for errors and update statistics */
rxlength = cs89x0_getreg(PPR_RXLENGTH);
if ((isq & RX_OK) == 0)
{
#ifdef CONFIG_C89x0_STATISTICS
cd89x0->cs_stats.rx_errors++;
if ((isq & RX_RUNT) != 0)
{
cd89x0->cs_stats.rx_lengtherrors++;
}
if ((isq & RX_EXTRA_DATA) != 0)
{
cd89x0->cs_stats.rx_lengtherrors++;
}
if (isq & RX_CRC_ERROR) != 0)
{
if (!(isq & (RX_EXTRA_DATA|RX_RUNT)))
{
cd89x0->cs_stats.rx_crcerrors++;
}
}
if ((isq & RX_DRIBBLE) != 0)
{
cd89x0->cs_stats.rx_frameerrors++;
}
#endif
return;
}
/* Check if the packet is a valid size for the uIP buffer configuration */
if (rxlength > ???)
{
#ifdef CONFIG_C89x0_STATISTICS
cd89x0->cs_stats.rx_errors++;
cd89x0->cs_stats.rx_lengtherrors++;
#endif
return;
}
/* Copy the data data from the hardware to cs89x0->cs_dev.d_buf. Set
* amount of data in cs89x0->cs_dev.d_len
*/
dest = (uint16_t*)cs89x0->cs_dev.d_buf;
for (nbytes = 0; nbytes < rxlength; nbytes += sizeof(uint16_t))
{
*dest++ = cs89x0_getreg(PPR_RXFRAMELOCATION);
}
#ifdef CONFIG_C89x0_STATISTICS
cd89x0->cs_stats.rx_packets++;
#endif
/* We only accept IP packets of the configured type and ARP packets */
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(UIP_ETHTYPE_IP6))
#else
if (BUF->type == HTONS(UIP_ETHTYPE_IP))
#endif
{
uip_arp_ipin(&cs89x0->cs_dev);
uip_input(&cs89x0->cs_dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
*/
if (cs89x0->cs_dev.d_len > 0)
{
uip_arp_out(&cs89x0->cs_dev);
cs89x0_transmit(cs89x0);
}
}
else if (BUF->type == htons(UIP_ETHTYPE_ARP))
{
uip_arp_arpin(&cs89x0->cs_dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
*/
if (cs89x0->cs_dev.d_len > 0)
{
cs89x0_transmit(cs89x0);
}
}
}
/****************************************************************************
* Function: cs89x0_txdone
*
* Description:
* An interrupt was received indicating that the last TX packet(s) is done
*
* Parameters:
* cs89x0 - Reference to the driver state structure
*
* Returned Value:
* None
*
* Assumptions:
*
****************************************************************************/
static void cs89x0_txdone(struct cs89x0_driver_s *cs89x0, uint16_t isq)
{
/* Check for errors and update statistics. The lower 6-bits of the ISQ
* hold the register address causing the interrupt. We got here because
* those bits indicated */
#ifdef CONFIG_C89x0_STATISTICS
cd89x0->cs_stats.tx_packets++;
if ((isq & ISQ_TXEVENT_TXOK) == 0)
{
cd89x0->cs_stats.tx_errors++;
}
if ((isq & ISQ_TXEVENT_LOSSOFCRS) != 0)
{
cd89x0->cs_stats.tx_carriererrors++;
}
if ((isq & ISQ_TXEVENT_SQEERROR) != 0)
{
cd89x0->cs_stats.tx_heartbeaterrors++;
}
if (i(sq & ISQ_TXEVENT_OUTWINDOW) != 0)
{
cd89x0->cs_stats.tx_windowerrors++;
}
if (isq & TX_16_COL)
{
cd89x0->cs_stats.tx_abortederrors++;
}
#endif
/* If no further xmits are pending, then cancel the TX timeout */
wd_cancel(cs89x0->cs_txtimeout);
/* Then poll uIP for new XMIT data */
(void)uip_poll(&cs89x0->cs_dev, cs89x0_uiptxpoll);
}
/****************************************************************************
* Function: cs89x0_mapirq
*
* Description:
* Map an IRQ number to a CS89x0 device state instance. This is only
* necessary to handler the case where the architecture includes more than
* on CS89x0 chip.
*
* Parameters:
* irq - Number of the IRQ that generated the interrupt
*
* Returned Value:
* A reference to device state structure (NULL if irq does not correspond
* to any CS89x0 device).
*
* Assumptions:
*
****************************************************************************/
#if CONFIG_CS89x0_NINTERFACES > 1
static inline FAR struct cs89x0_driver_s *cs89x0_mapirq(int irq)
{
int i;
for (i = 0; i < CONFIG_CS89x0_NINTERFACES; i++)
{
if (g_cs89x0[i] && g_cs89x0[i].irq == irq)
{
return g_cs89x0[i];
}
}
return NULL;
}
#endif
/****************************************************************************
* Function: cs89x0_interrupt
*
* Description:
* Hardware interrupt handler
*
* Parameters:
* irq - Number of the IRQ that generated the interrupt
* context - Interrupt register state save info (architecture-specific)
*
* Returned Value:
* OK on success
*
* Assumptions:
*
****************************************************************************/
static int cs89x0_interrupt(int irq, FAR void *context)
{
register struct cs89x0_driver_s *cs89x0 = s89x0_mapirq(irq);
uint16_t isq;
#ifdef CONFIG_DEBUG
if (!cs89x0)
{
return -ENODEV;
}
#endif
/* Read and process all of the events from the ISQ */
while ((isq = cs89x0_getreg(dev, CS89x0_ISQ_OFFSET)) != 0)
{
nvdbg("ISQ: %04x\n", isq);
switch (isq & ISQ_EVENTMASK)
{
case ISQ_RXEVENT:
cs89x0_receive(cs89x0);
break;
case ISQ_TXEVENT:
cs89x0_txdone(cs89x0, isq);
break;
case ISQ_BUFEVENT:
if ((isq & ISQ_BUFEVENT_TXUNDERRUN) != 0)
{
ndbg("Transmit underrun\n");
#ifdef CONFIG_CS89x0_XMITEARLY
cd89x0->cs_txunderrun++;
if (cd89x0->cs_txunderrun == 3)
{
cd89x0->cs_txstart = PPR_TXCMD_TXSTART381;
}
else if (cd89x0->cs_txunderrun == 6)
{
cd89x0->cs_txstart = PPR_TXCMD_TXSTARTFULL;
}
#endif
}
break;
case ISQ_RXMISSEVENT:
#ifdef CONFIG_C89x0_STATISTICS
cd89x0->cs_stats.rx_missederrors += (isq >>6);
#endif
break;
case ISQ_TXCOLEVENT:
#ifdef CONFIG_C89x0_STATISTICS
cd89x0->cs_stats.collisions += (isq >>6);
#endif
break;
}
}
return OK;
}
/****************************************************************************
* Function: cs89x0_txtimeout
*
* Description:
* Our TX watchdog timed out. Called from the timer interrupt handler.
* The last TX never completed. Reset the hardware and start again.
*
* Parameters:
* argc - The number of available arguments
* arg - The first argument
*
* Returned Value:
* None
*
* Assumptions:
*
****************************************************************************/
static void cs89x0_txtimeout(int argc, uint32_t arg, ...)
{
struct cs89x0_driver_s *cs89x0 = (struct cs89x0_driver_s *)arg;
/* Increment statistics and dump debug info */
#warning "Missing logic"
/* Then reset the hardware */
#warning "Missing logic"
/* Then poll uIP for new XMIT data */
(void)uip_poll(&cs89x0->cs_dev, cs89x0_uiptxpoll);
}
/****************************************************************************
* Function: cs89x0_polltimer
*
* Description:
* Periodic timer handler. Called from the timer interrupt handler.
*
* Parameters:
* argc - The number of available arguments
* arg - The first argument
*
* Returned Value:
* None
*
* Assumptions:
*
****************************************************************************/
static void cs89x0_polltimer(int argc, uint32_t arg, ...)
{
struct cs89x0_driver_s *cs89x0 = (struct cs89x0_driver_s *)arg;
/* Check if there is room in the send another TXr packet. */
#warning "Missing logic"
/* If so, update TCP timing states and poll uIP for new XMIT data */
(void)uip_timer(&cs89x0->cs_dev, cs89x0_uiptxpoll, CS89x0_POLLHSEC);
/* Setup the watchdog poll timer again */
(void)wd_start(cs89x0->cs_txpoll, CS89x0_WDDELAY, cs89x0_polltimer, 1, arg);
}
/****************************************************************************
* Function: cs89x0_ifup
*
* Description:
* NuttX Callback: Bring up the Ethernet interface when an IP address is
* provided
*
* Parameters:
* dev - Reference to the NuttX driver state structure
*
* Returned Value:
* None
*
* Assumptions:
*
****************************************************************************/
static int cs89x0_ifup(struct uip_driver_s *dev)
{
struct cs89x0_driver_s *cs89x0 = (struct cs89x0_driver_s *)dev->d_private;
ndbg("Bringing up: %d.%d.%d.%d\n",
dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
(dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 );
/* Initialize the Ethernet interface */
#warning "Missing logic"
/* Set and activate a timer process */
(void)wd_start(cs89x0->cs_txpoll, CS89x0_WDDELAY, cs89x0_polltimer, 1, (uint32_t)cs89x0);
/* Enable the Ethernet interrupt */
cs89x0->cs_bifup = true;
up_enable_irq(CONFIG_CS89x0_IRQ);
return OK;
}
/****************************************************************************
* Function: cs89x0_ifdown
*
* Description:
* NuttX Callback: Stop the interface.
*
* Parameters:
* dev - Reference to the NuttX driver state structure
*
* Returned Value:
* None
*
* Assumptions:
*
****************************************************************************/
static int cs89x0_ifdown(struct uip_driver_s *dev)
{
struct cs89x0_driver_s *cs89x0 = (struct cs89x0_driver_s *)dev->d_private;
irqstate_t flags;
/* Disable the Ethernet interrupt */
flags = irqsave();
up_disable_irq(CONFIG_CS89x0_IRQ);
/* Cancel the TX poll timer and TX timeout timers */
wd_cancel(cs89x0->cs_txpoll);
wd_cancel(cs89x0->cs_txtimeout);
/* Reset the device */
cs89x0->cs_bifup = false;
irqrestore(flags);
return OK;
}
/****************************************************************************
* Function: cs89x0_txavail
*
* Description:
* Driver callback invoked when new TX data is available. This is a
* stimulus perform an out-of-cycle poll and, thereby, reduce the TX
* latency.
*
* Parameters:
* dev - Reference to the NuttX driver state structure
*
* Returned Value:
* None
*
* Assumptions:
* Called in normal user mode
*
****************************************************************************/
static int cs89x0_txavail(struct uip_driver_s *dev)
{
struct cs89x0_driver_s *cs89x0 = (struct cs89x0_driver_s *)dev->d_private;
irqstate_t flags;
flags = irqsave();
/* Ignore the notification if the interface is not yet up */
if (cs89x0->cs_bifup)
{
/* Check if there is room in the hardware to hold another outgoing packet. */
#warning "Missing logic"
/* If so, then poll uIP for new XMIT data */
(void)uip_poll(&cs89x0->cs_dev, cs89x0_uiptxpoll);
}
irqrestore(flags);
return OK;
}
/****************************************************************************
* Function: cs89x0_addmac
*
* Description:
* NuttX Callback: Add the specified MAC address to the hardware multicast
* address filtering
*
* Parameters:
* dev - Reference to the NuttX driver state structure
* mac - The MAC address to be added
*
* Returned Value:
* None
*
* Assumptions:
*
****************************************************************************/
#ifdef CONFIG_NET_IGMP
static int cs89x0_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac)
{
FAR struct cs89x0_driver_s *priv = (FAR struct cs89x0_driver_s *)dev->d_private;
/* Add the MAC address to the hardware multicast routing table */
#warning "Multicast MAC support not implemented"
return OK;
}
#endif
/****************************************************************************
* Function: cs89x0_rmmac
*
* Description:
* NuttX Callback: Remove the specified MAC address from the hardware multicast
* address filtering
*
* Parameters:
* dev - Reference to the NuttX driver state structure
* mac - The MAC address to be removed
*
* Returned Value:
* None
*
* Assumptions:
*
****************************************************************************/
#ifdef CONFIG_NET_IGMP
static int cs89x0_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac)
{
FAR struct cs89x0_driver_s *priv = (FAR struct cs89x0_driver_s *)dev->d_private;
/* Add the MAC address to the hardware multicast routing table */
#warning "Multicast MAC support not implemented"
return OK;
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: cs89x0_initialize
*
* Description:
* Initialize the Ethernet driver
*
* Parameters:
* impl - decribes the implementation of the cs89x00 implementation.
* This reference is retained so so must remain stable throughout the
* life of the driver instance.
* devno - Identifies the device number. This must be a number between
* zero CONFIG_CS89x0_NINTERFACES and the same devno must not be
* initialized twice. The associated network device will be referred
* to with the name "eth" followed by this number (eth0, eth1, etc).
*
* Returned Value:
* OK on success; Negated errno on failure.
*
* Assumptions:
*
****************************************************************************/
/* Initialize the CS89x0 chip and driver */
int cs89x0_initialize(FAR const cs89x0_driver_s *cs89x0, int devno)
{
/* Sanity checks -- only performed with debug enabled */
#ifdef CONFIG_DEBUG
if (!cs89x0 || (unsigned)devno > CONFIG_CS89x0_NINTERFACES || g_cs89x00[devno])
{
return -EINVAL;
}
#endif
/* Check if a Ethernet chip is recognized at its I/O base */
#warning "Missing logic"
/* Attach the IRQ to the driver */
if (irq_attach(cs89x0->irq, cs89x0_interrupt))
{
/* We could not attach the ISR to the ISR */
return -EAGAIN;
}
/* Initialize the driver structure */
g_cs89x[devno] = cs89x0; /* Used to map IRQ back to instance */
cs89x0->cs_dev.d_ifup = cs89x0_ifup; /* I/F down callback */
cs89x0->cs_dev.d_ifdown = cs89x0_ifdown; /* I/F up (new IP address) callback */
cs89x0->cs_dev.d_txavail = cs89x0_txavail; /* New TX data callback */
#ifdef CONFIG_NET_IGMP
cs89x0->cs_dev.d_addmac = cs89x0_addmac; /* Add multicast MAC address */
cs89x0->cs_dev.d_rmmac = cs89x0_rmmac; /* Remove multicast MAC address */
#endif
cs89x0->cs_dev.d_private = (void*)cs89x0; /* Used to recover private state from dev */
/* Create a watchdog for timing polling for and timing of transmisstions */
cs89x0->cs_txpoll = wd_create(); /* Create periodic poll timer */
cs89x0->cs_txtimeout = wd_create(); /* Create TX timeout timer */
/* Read the MAC address from the hardware into cs89x0->cs_dev.d_mac.ether_addr_octet */
/* Register the device with the OS so that socket IOCTLs can be performed */
(void)netdev_register(&cs89x0->cs_dev);
return OK;
}
#endif /* CONFIG_NET && CONFIG_NET_CS89x0 */
nuttx/drivers/net/cs89x0.h
+326
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/****************************************************************************
* drivers/net/cs89x0.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __DRIVERS_NET_CS89x0_H
#define __DRIVERS_NET_CS89x0_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* CONFIG_CS89x0_ALIGN16/32 determines if the 16-bit CS89x0 registers are
* aligned to 16-bit or 32-bit address boundaries. NOTE: If there multiple
* CS89x00 parts in the board architecture, we assume that the address
* alignment is the same for all implementations. If that is not the
* case, then it will be necessary to move a shift value into
* the cs89x0_driver_s structure and calculate the offsets dynamically in
* the putreg and getreg functions.
*/
#if defined(CONFIG_CS89x0_ALIGN16)
# define CS89x0_RTDATA_OFFSET (0 << 1)
# define CS89x0_TxCMD_OFFSET (2 << 1)
# define CS89x0_TxLEN_OFFSET (3 << 1)
# define CS89x0_ISQ_OFFSET (4 << 1)
# define CS89x0_PPTR_OFFSET (5 << 1)
# define CS89x0_PDATA_OFFSET (6 << 1)
#elif defined(CONFIG_CS89x0_ALIGN32)
# define CS89x0_RTDATA_OFFSET (0 << 2)
# define CS89x0_TxCMD_OFFSET (2 << 2)
# define CS89x0_TxLEN_OFFSET (3 << 2)
# define CS89x0_ISQ_OFFSET (4 << 2)
# define CS89x0_PPTR_OFFSET (5 << 2)
# define CS89x0_PDATA_OFFSET (6 << 2)
#else
# error "CS89x00 address alignment is not defined"
#endif
/* ISQ register bit definitions */
#define ISQ_EVENTMASK 0x003f /* Bits 0-5 indicate the status register */
#define ISQ_RXEVENT 0x0004
#define ISQ_TXEVENT 0x0008
#define ISQ_BUFEVENT 0x000c
#define ISQ_RXMISSEVENT 0x0010
#define ISQ_TXCOLEVENT 0x0012
/* ISQ register TxEVENT bit definitions*/
#define ISQ_RXEVENT_IAHASH (1 << 6)
#define ISQ_RXEVENT_DRIBBLE (1 << 7)
#define ISQ_RXEVENT_RXOK (1 << 8)
#define ISQ_RXEVENT_HASHED (1 << 9)
#define ISQ_RXEVENT_HASHNDX_SHIFT 10
#define ISQ_RXEVENT_HASHNDX_MASK (0x3f << ISQ_RXEVENT_HASHNDX_SHIFT)
/* ISQ register TxEVENT bit definitions*/
#define ISQ_TXEVENT_LOSSOFCRS (1 << 6)
#define ISQ_TXEVENT_SQEERROR (1 << 7)
#define ISQ_TXEVENT_TXOK (1 << 8)
#define ISQ_TXEVENT_OUTWINDOW (1 << 9)
#define ISQ_TXEVENT_JABBER (1 << 10)
#define ISQ_TXEVENT_NCOLLISION_SHIFT 11
#define ISQ_TXEVENT_NCOLLISION_MASK (15 << ISQ_TXEVENT_NCOLLISION_SHIFT)
#define ISQ_TXEVENT_16COLL (1 << 15)
/* ISQ register BufEVENT bit definitions */
#define ISQ_BUFEVENT_SWINT (1 << 6)
#define ISQ_BUFEVENT_RXDMAFRAME (1 << 7)
#define ISQ_BUFEVENT_RDY4TX (1 << 8)
#define ISQ_BUFEVENT_TXUNDERRUN (1 << 9)
#define ISQ_BUFEVENT_RXMISS (1 << 10)
#define ISQ_BUFEVENT_RX128 (1 << 11)
#define ISQ_BUFEVENT_RXDEST (1 << 15)
/* Packet page register offsets *********************************************/
/* 0x0000 Bus interface registers */
#define PPR_CHIPID 0x0000 /* Chip identifier - must be 0x630E */
#define PPR_CHIPREV 0x0002 /* Chip revision, model codes */
#define PPR_IOBASEADDRESS 0x0020 /* I/O Base Address */
#define PPR_INTREG 0x0022 /* Interrupt configuration */
# define PPR_INTREG_IRQ0 0x0000 /* Use INTR0 pin */
# define PPR_INTREG_IRQ1 0x0001 /* Use INTR1 pin */
# define PPR_INTREG_IRQ2 0x0002 /* Use INTR2 pin */
# define PPR_INTREG_IRQ3 0x0003 /* Use INTR3 pin */
#define PPR_DMACHANNELNUMBER 0x0024 /* DMA Channel Number (0,1, or 2) */
#define PPR_DMASTARTOFFRAME 0x0026 /* DMA Start of Frame */
#define PPR_DMAFRAMECOUNT 0x0028 /* DMA Frame Count (12-bits) */
#define PPR_RXDMABYTECOUNT 0x002a /* Rx DMA Byte Count */
#define PPR_MEMORYBASEADDRESS 0x002c /* Memory Base Address Register (20-bit) */
#define PPR_BOOTPROMBASEADDRESS 0x0030 /* Boot PROM Base Address */
#define PPR_BOOTPROMADDRESSMASK 0x0034 /* Boot PROM Address Mask */
#define PPR_EEPROMCOMMAND 0x0040 /* EEPROM Command */
#define PPR_EEPROMDATA 0x0042 /* EEPROM Data */
#define PPR_RECVFRAMEBYTES 0x0050 /* Received Frame Byte Counter */
/* 0x0100 - Configuration and control registers */
#define PPR_RXCFG 0x0102 /* Receiver configuration */
# define PPR_RXCFG_SKIP1 (1 << 6) /* Skip (discard) current frame */
# define PPR_RXCFG_STREAM (1 << 7) /* Enable streaming mode */
# define PPR_RXCFG_RXOK (1 << 8) /* RxOK interrupt enable */
# define PPR_RxCFG_RxDMAonly (1 << 9) /* Use RxDMA for all frames */
# define PPR_RxCFG_AutoRxDMA (1 << 10) /* Select RxDMA automatically */
# define PPR_RxCFG_BufferCRC (1 << 11) /* Include CRC characters in frame */
# define PPR_RxCFG_CRC (1 << 12) /* Enable interrupt on CRC error */
# define PPR_RxCFG_RUNT (1 << 13) /* Enable interrupt on RUNT frames */
# define PPR_RxCFG_EXTRA (1 << 14) /* Enable interrupt on frames with extra data */
#define PPR_RXCTL 0x0104 /* Receiver control */
# define PPR_RXCTL_IAHASH (1 << 6) /* Accept frames that match hash */
# define PPR_RXCTL_PROMISCUOUS (1 << 7) /* Accept any frame */
# define PPR_RXCTL_RXOK (1 << 8) /* Accept well formed frames */
# define PPR_RXCTL_MULTICAST (1 << 9) /* Accept multicast frames */
# define PPR_RXCTL_IA (1 << 10) /* Accept frame that matches IA */
# define PPR_RXCTL_BROADCAST (1 << 11) /* Accept broadcast frames */
# define PPR_RXCTL_CRC (1 << 12) /* Accept frames with bad CRC */
# define PPR_RXCTL_RUNT (1 << 13) /* Accept runt frames */
# define PPR_RXCTL_EXTRA (1 << 14) /* Accept frames that are too long */
#define PPR_TXCFG 0x0106 /* Transmit configuration */
# define PPR_TXCFG_CRS (1 << 6) /* Enable interrupt on loss of carrier */
# define PPR_TXCFG_SQE (1 << 7) /* Enable interrupt on Signal Quality Error */
# define PPR_TXCFG_TXOK (1 << 8) /* Enable interrupt on successful xmits */
# define PPR_TXCFG_LATE (1 << 9) /* Enable interrupt on "out of window" */
# define PPR_TXCFG_JABBER (1 << 10) /* Enable interrupt on jabber detect */
# define PPR_TXCFG_COLLISION (1 << 11) /* Enable interrupt if collision */
# define PPR_TXCFG_16COLLISIONS (1 << 15) /* Enable interrupt if > 16 collisions */
#define PPR_TXCMD 0x0108 /* Transmit command status */
# define PPR_TXCMD_TXSTART5 (0 << 6) /* Start after 5 bytes in buffer */
# define PPR_TXCMD_TXSTART381 (1 << 6) /* Start after 381 bytes in buffer */
# define PPR_TXCMD_TXSTART1021 (2 << 6) /* Start after 1021 bytes in buffer */
# define PPR_TXCMD_TXSTARTFULL (3 << 6) /* Start after all bytes loaded */
# define PPR_TXCMD_FORCE (1 << 8) /* Discard any pending packets */
# define PPR_TXCMD_ONECOLLISION (1 << 9) /* Abort after a single collision */
# define PPR_TXCMD_NOCRC (1 << 12) /* Do not add CRC */
# define PPR_TXCMD_NOPAD (1 << 13) /* Do not pad short packets */
#define PPR_BUFCFG 0x010a /* Buffer configuration */
# define PPR_BUFCFG_SWI (1 << 6) /* Force interrupt via software */
# define PPR_BUFCFG_RXDMA (1 << 7) /* Enable interrupt on Rx DMA */
# define PPR_BUFCFG_TXRDY (1 << 8) /* Enable interrupt when ready for Tx */
# define PPR_BUFCFG_TXUE (1 << 9) /* Enable interrupt in Tx underrun */
# define PPR_BUFCFG_RXMISS (1 << 10) /* Enable interrupt on missed Rx packets */
# define PPR_BUFCFG_RX128 (1 << 11) /* Enable Rx interrupt after 128 bytes */
# define PPR_BUFCFG_TXCOL (1 << 12) /* Enable int on Tx collision ctr overflow */
# define PPR_BUFCFG_MISS (1 << 13) /* Enable int on Rx miss ctr overflow */
# define PPR_BUFCFG_RXDEST (1 << 15) /* Enable int on Rx dest addr match */
#define PPR_LINECTL 0x0112 /* Line control */
# define PPR_LINECTL_RX (1 << 6) /* Enable receiver */
# define PPR_LINECTL_TX (1 << 7) /* Enable transmitter */
# define PPR_LINECTL_AUIONLY (1 << 8) /* AUI interface only */
# define PPR_LINECTL_AUTOAUI10BT (1 << 9) /* Autodetect AUI or 10BaseT interface */
# define PPR_LINECTL_MODBACKOFFE (1 << 11) /* Enable modified backoff algorithm */
# define PPR_LINECTL_POLARITYDIS (1 << 12) /* Disable Rx polarity autodetect */
# define PPR_LINECTL_2PARTDEFDIS (1 << 13) /* Disable two-part defferal */
# define PPR_LINECTL_LORXSQUELCH (1 << 14) /* Reduce receiver squelch threshold */
#define PPR_SELFCTL 0x0114 /* Chip self control */
# define PPR_SELFCTL_RESET (1 << 6) /* Self-clearing reset */
# define PPR_SELFCTL_SWSUSPEND (1 << 8) /* Initiate suspend mode */
# define PPR_SELFCTL_HWSLEEPE (1 << 9) /* Enable SLEEP input */
# define PPR_SELFCTL_HWSTANDBYE (1 << 10) /* Enable standby mode */
# define PPR_SELFCTL_HC0E (1 << 12) /* Use HCB0 for LINK LED */
# define PPR_SELFCTL_HC1E (1 << 13) /* Use HCB1 for BSTATUS LED */
# define PPR_SELFCTL_HCB0 (1 << 14) /* Control LINK LED if HC0E set */
# define PPR_SELFCTL_HCB1 (1 << 15) /* Cntrol BSTATUS LED if HC1E set */
#define PPR_BUSCTL 0x0116 /* Bus control */
# define PPR_BUSCTL_RESETRXDMA (1 << 6) /* Reset RxDMA pointer */
# define PPR_BUSCTL_DMAEXTEND (1 << 8) /* Extend DMA cycle */
# define PPR_BUSCTL_USESA (1 << 9) /* Assert MEMCS16 on address decode */
# define PPR_BUSCTL_MEMORYE (1 << 10) /* Enable memory mode */
# define PPR_BUSCTL_DMABURST (1 << 11) /* Limit DMA access burst */
# define PPR_BUSCTL_IOCHRDYE (1 << 12) /* Set IOCHRDY high impedence */
# define PPR_BUSCTL_RXDMASIZE (1 << 13) /* Set DMA buffer size 64KB */
# define PPR_BUSCTL_ENABLEIRQ (1 << 15) /* Generate interrupt on interrupt event */
#define PPR_TESTCTL 0x0118 /* Test control */
# define PPR_TESTCTL_DISABLELT (1 << 7) /* Disable link status */
# define PPR_TESTCTL_ENDECLOOP (1 << 9) /* Internal loopback */
# define PPR_TESTCTL_AUILOOP (1 << 10) /* AUI loopback */
# define PPR_TESTCTL_DISBACKOFF (1 << 11) /* Disable backoff algorithm */
# define PPR_TESTCTL_FDX (1 << 14) /* Enable full duplex mode */
/* 0x0120 - Status and Event Registers */
#define PPR_ISQ 0x0120 /* Interrupt Status Queue */
#define PPR_RER 0x0124 /* Receive event */
# define PPR_RER_IAHASH (1 << 6) /* Frame hash match */
# define PPR_RER_DRIBBLE (1 << 7) /* Frame had 1-7 extra bits after last byte */
# define PPR_RER_RXOK (1 << 8) /* Frame received with no errors */
# define PPR_RER_HASHED (1 << 9) /* Frame address hashed OK */
# define PPR_RER_IA (1 << 10) /* Frame address matched IA */
# define PPR_RER_BROADCAST (1 << 11) /* Broadcast frame */
# define PPR_RER_CRC (1 << 12) /* Frame had CRC error */
# define PPR_RER_RUNT (1 << 13) /* Runt frame */
# define PPR_RER_EXTRA (1 << 14) /* Frame was too long */
#define PPR_TER 0x0128 /* Transmit event */
# define PPR_TER_CRS (1 << 6) /* Carrier lost */
# define PPR_TER_SQE (1 << 7) /* Signal Quality Error */
# define PPR_TER_TXOK (1 << 8) /* Packet sent without error */
# define PPR_TER_LATE (1 << 9) /* Out of window */
# define PPR_TER_JABBER (1 << 10) /* Stuck transmit? */
# define PPR_TER_NUMCOLLISIONS_SHIFT 11
# define PPR_TER_NUMCOLLISIONS_MASK (15 << PPR_TER_NUMCOLLISIONS_SHIFT)
# define PPR_TER_16COLLISIONS (1 << 15) /* > 16 collisions */
#define PPR_BER 0x012C /* Buffer event */
# define PPR_BER_SWINT (1 << 6) /* Software interrupt */
# define PPR_BER_RXDMAFRAME (1 << 7) /* Received framed DMAed */
# define PPR_BER_RDY4TX (1 << 8) /* Ready for transmission */
# define PPR_BER_TXUNDERRUN (1 << 9) /* Transmit underrun */
# define PPR_BER_RXMISS (1 << 10) /* Received frame missed */
# define PPR_BER_RX128 (1 << 11) /* 128 bytes received */
# define PPR_BER_RXDEST (1 << 15) /* Received framed passed address filter */
#define PPR_RXMISS 0x0130 /* Receiver miss counter */
#define PPR_TXCOL 0x0132 /* Transmit collision counter */
#define PPR_LINESTAT 0x0134 /* Line status */
# define PPR_LINESTAT_LINKOK (1 << 7) /* Line is connected and working */
# define PPR_LINESTAT_AUI (1 << 8) /* Connected via AUI */
# define PPR_LINESTAT_10BT (1 << 9) /* Connected via twisted pair */
# define PPR_LINESTAT_POLARITY (1 << 12) /* Line polarity OK (10BT only) */
# define PPR_LINESTAT_CRS (1 << 14) /* Frame being received */
#define PPR_SELFSTAT 0x0136 /* Chip self status */
# define PPR_SELFSTAT_33VACTIVE (1 << 6) /* supply voltage is 3.3V */
# define PPR_SELFSTAT_INITD (1 << 7) /* Chip initialization complete */
# define PPR_SELFSTAT_SIBSY (1 << 8) /* EEPROM is busy */
# define PPR_SELFSTAT_EEPROM (1 << 9) /* EEPROM present */
# define PPR_SELFSTAT_EEPROMOK (1 << 10) /* EEPROM checks out */
# define PPR_SELFSTAT_ELPRESENT (1 << 11) /* External address latch logic available */
# define PPR_SELFSTAT_EESIZE (1 << 12) /* Size of EEPROM */
#define PPR_BUSSTAT 0x0138 /* Bus status */
# define PPR_BUSSTAT_TXBID (1 << 7) /* Tx error */
# define PPR_BUSSTAT_TXRDY (1 << 8) /* Ready for Tx data */
#define PPR_TDR 0x013C /* AUI Time Domain Reflectometer */
/* 0x0144 - Initiate transmit registers */
#define PPR_TXCOMMAND 0x0144 /* Tx Command */
#define PPR_TXLENGTH 0x0146 /* Tx Length */
/* 0x0150 - Address filter registers */
#define PPR_LAF 0x0150 /* Logical address filter (6 bytes) */
#define PPR_IA 0x0158 /* Individual address (MAC) */
/* 0x0400 - Frame location registers */
#define PPR_RXSTATUS 0x0400 /* Rx Status */
#define PPR_RXLENGTH 0x0402 /* Rx Length */
#define PPR_RXFRAMELOCATION 0x0404 /* Rx Frame Location */
#define PPR_TXFRAMELOCATION 0x0a00 /* Tx Frame Location */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __DRIVERS_NET_CS89x0_H */
nuttx/drivers/net/dm90x0.c
+1815
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nuttx/drivers/net/e1000.c
+1049
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nuttx/drivers/net/e1000.h
+123
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@@ -0,0 +1,123 @@
/****************************************************************************
* drivers/net/e1000.h
*
* Copyright (C) 2011 Yu Qiang. All rights reserved.
* Author: Yu Qiang <yuq825@gmail.com>
*
* This file is a part of NuttX:
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __DRIVERS_NET_E1000_H
#define __DRIVERS_NET_E1000_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <rgmp/types.h>
#include <rgmp/trap.h>
#include <rgmp/arch/arch.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/************** PCI ID ***************/
#define INTEL_VENDERID 0x8086
#define E1000_82573L 0x109a
#define E1000_82540EM 0x100e
#define E1000_82574L 0x10d3
#define E1000_82567LM 0x10f5
#define E1000_82541PI 0x107c
/****************************************************************************
* Public Types
****************************************************************************/
enum e1000_registers {
E1000_CTRL = 0x0000, // Device Control
E1000_STATUS = 0x0008, // Device Status
E1000_CTRL_EXT = 0x0018, // Device Control Extension
E1000_FCAL = 0x0028, // Flow Control Address Low
E1000_FCAH = 0x002C, // Flow Control Address High
E1000_FCT = 0x0030, // Flow Control Type
E1000_ICR = 0x00C0, // Interrupt Cause Read
E1000_ICS = 0x00C8, // Interrupt Cause Set
E1000_IMS = 0x00D0, // Interrupt Mask Set
E1000_IMC = 0x00D8, // Interrupt Mask Clear
E1000_RCTL = 0x0100, // Receive Control
E1000_FCTTV = 0x0170, // Flow Control Transmit Timer Value
E1000_TCTL = 0x0400, // Transmit Control
E1000_PBA = 0x1000, // Packet Buffer Allocation
E1000_FCRTL = 0x2160, // Flow Control Receive Threshold Low
E1000_FCRTH = 0x2168, // Flow Control Receive Threshold High
E1000_RDBAL = 0x2800, // Rx Descriptor Base Address Low
E1000_RDBAH = 0x2804, // Rx Descriptor Base Address High
E1000_RDLEN = 0x2808, // Rx Descriptor Length
E1000_RDH = 0x2810, // Rx Descriptor Head
E1000_RDT = 0x2818, // Rx Descriptor Tail
E1000_RXDCTL = 0x2828, // Rx Descriptor Control
E1000_TDBAL = 0x3800, // Tx Descriptor Base Address Low
E1000_TDBAH = 0x3804, // Tx Descriptor Base Address High
E1000_TDLEN = 0x3808, // Tx Descriptor Length
E1000_TDH = 0x3810, // Tx Descriptor Head
E1000_TDT = 0x3818, // Tx Descriptor Tail
E1000_TXDCTL = 0x3828, // Tx Descriptor Control
E1000_TPR = 0x40D0, // Total Packets Received
E1000_TPT = 0x40D4, // Total Packets Transmitted
E1000_RA = 0x5400, // Receive-filter Array
};
/***************** e1000 device structure *****************/
struct tx_desc {
uint64_t base_address;
uint16_t packet_length;
uint8_t cksum_offset;
uint8_t desc_command;
uint8_t desc_status;
uint8_t cksum_origin;
uint16_t special_info;
};
struct rx_desc {
uint64_t base_address;
uint16_t packet_length;
uint16_t packet_cksum;
uint8_t desc_status;
uint8_t desc_errors;
uint16_t vlan_tag;
};
#endif
nuttx/drivers/net/enc28j60.c
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nuttx/drivers/net/enc28j60.h
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/****************************************************************************
* drivers/net/enc28j60.h
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* References:
* - ENC28J60 Data Sheet, Stand-Alone Ethernet Controller with SPI Interface,
* DS39662C, 2008 Microchip Technology Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __DRIVERS_NET_ENC28J60_H
#define __DRIVERS_NET_ENC28J60_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* ENC28J60 Commands ********************************************************/
/* A total of seven instructions are implemented on the ENC28J60. Where:
*
* aaaaaa is the 5-bit address of a control register, and
* dddddddd is one or more bytes of data that may accompany the command.
*/
#define ENC_RCR (0x00) /* Read Control Register
* 000 | aaaaa | (Register value returned)) */
#define ENC_RBM (0x3a) /* Read Buffer Memory
* 001 | 11010 | (Read buffer data follows) */
#define ENC_WCR (0x40) /* Write Control Register
* 010 | aaaaa | dddddddd */
#define ENC_WBM (0x7a) /* Write Buffer Memory
* 011 | 11010 | (Write buffer data follows) */
#define ENC_BFS (0x80) /* Bit Field Set
* 100 | aaaaa | dddddddd */
#define ENC_BFC (0xa0) /* Bit Field Clear
* 101 | aaaaa | dddddddd */
#define ENC_SRC (0xff) /* System Reset
* 111 | 11111 | (No data) */
/* Global Control Registers *************************************************/
/* Control registers are accessed with the RCR, RBM, WCR, BFS, and BFC
* commands. The following identifies all ENC28J60 control registers. The
* control register memory is partitioned into four banks, selectable by the
* bank select bits, BSEL1:BSEL0, in the ECON1 register.
*
* The last five locations (0x1b to 0x1f) of all banks point to a common set
* of registers: EIE, EIR, ESTAT, ECON2 and ECON1. These are key registers
* usedin controlling and monitoring the operation of the device. Their
* common mapping allows easy access without switching the bank.
*
* Control registers for the ENC28J60 are generically grouped as ETH, MAC and
* MII registers. Register names starting with E belong to the ETH group.
* Similarly, registers names starting with MA belong to the MAC group and
* registers prefixed with MI belong to the MII group.
*/
#define ENC_EIE (0x1b) /* Ethernet Interrupt Enable Register */
#define ENC_EIR (0x1c) /* Ethernet Interupt Request Register */
#define ENC_ESTAT (0x1d) /* Ethernet Status Register */
#define ENC_ECON2 (0x1e) /* Ethernet Control 2 Register */
#define ENC_ECON1 (0x1f) /* Ethernet Control 1 Register */
/* Ethernet Interrupt Enable Register Bit Definitions */
#define EIE_RXERIE (1 << 0) /* Bit 0: Receive Error Interrupt Enable */
#define EIE_TXERIE (1 << 1) /* Bit 1: Transmit Error Interrupt Enable */
/* Bit 2: Reserved */
#define EIE_TXIE (1 << 3) /* Bit 3: Transmit Enable */
#define EIE_LINKIE (1 << 4) /* Bit 4: Link Status Change Interrupt Enable */
#define EIE_DMAIE (1 << 5) /* Bit 5: DMA Interrupt Enable */
#define EIE_PKTIE (1 << 6) /* Bit 6: Receive Packet Pending Interrupt Enable */
#define EIE_INTIE (1 << 7) /* Bit 7: Global INT Interrupt Enable */
/* Ethernet Interrupt Request Register Bit Definitions */
#define EIR_RXERIF (1 << 0) /* Bit 0: Receive Error Interrupt */
#define EIR_TXERIF (1 << 1) /* Bit 1: Transmit Error Interrupt */
/* Bit 2: Reserved */
#define EIR_TXIF (1 << 3) /* Bit 3: Transmit Interrupt */
#define EIR_LINKIF (1 << 4) /* Bit 4: Link Change Interrupt */
#define EIR_DMAIF (1 << 5) /* Bit 5: DMA Interrupt */
#define EIR_PKTIF (1 << 6) /* Bit 6: Receive Packet Pending Interrupt */
/* Bit 7: Reserved */
#define EIR_ALLINTS (0x7b) /* All interrupts */
/* Ethernet Status Register Bit Definitions */
#define ESTAT_CLKRDY (1 << 0) /* Bit 0: Clock Ready */
#define ESTAT_TXABRT (1 << 1) /* Bit 1: Transmit Abort Error */
#define ESTAT_RXBUSY (1 << 2) /* Bit 2: Receive Busy */
/* Bit 3: Reserved */
#define ESTAT_LATECOL (1 << 4) /* Bit 4: Late Collision Error */
/* Bit 5: Reserved */
#define ESTAT_BUFER (1 << 6) /* Bit 6: Ethernet Buffer Error Status */
#define ESTAT_INT (1 << 7) /* Bit 7: INT Interrupt */
/* Ethernet Control 1 Register Bit Definitions */
#define ECON1_BSEL_SHIFT (0) /* Bits 0-1: Bank select */
#define ECON1_BSEL_MASK (3 << ECON1_BSEL_SHIFT)
# define ECON1_BSEL_BANK0 (0 << 0) /* Bank 0 */
# define ECON1_BSEL_BANK1 (1 << 1) /* Bank 1 */
# define ECON1_BSEL_BANK2 (2 << 0) /* Bank 2 */
# define ECON1_BSEL_BANK3 (3 << 0) /* Bank 3 */
#define ECON1_RXEN (1 << 2) /* Bit 2: Receive Enable */
#define ECON1_TXRTS (1 << 3) /* Bit 3: Transmit Request to Send */
#define ECON1_CSUMEN (1 << 4) /* Bit 4: DMA Checksum Enable */
#define ECON1_DMAST (1 << 5) /* Bit 5: DMA Start and Busy Status */
#define ECON1_RXRST (1 << 6) /* Bit 6: Receive Logic Reset */
#define ECON1_TXRST (1 << 7) /* Bit 7: Transmit Logic Reset */
/* Ethernet Control 2 Register */
/* Bits 0-2: Reserved */
#define ECON2_VRPS (1 << 3) /* Bit 3: Voltage Regulator Power Save Enable */
/* Bit 4: Reserved */
#define ECON2_PWRSV (1 << 5) /* Bit 5: Power Save Enable */
#define ECON2_PKTDEC (1 << 6) /* Bit 6: Packet Decrement */
#define ECON2_AUTOINC (1 << 7) /* Bit 7: Automatic Buffer Pointer Increment Enable */
/* Banked Control Registers *************************************************/
/* The remaining control registers are identified with a a 5 bit address and
* a bank selection. We pack the bank number and an indication if this is
* a MAC/PHY register access together with the control register address
* together to keep the design simpler.
*/
#define ENC_ADDR_SHIFT (0) /* Bits 0-4: Register address */
#define ENC_ADDR_MASK (0x1f << ENC_ADDR_SHIFT)
#define ENC_BANK_SHIFT (5) /* Bits 5-6: Bank number */
#define ENC_BANK_MASK (3 << ENC_BSEL_SHIFT)
# define ENC_BANK0 (0 << ENC_BSEL_SHIFT)
# define ENC_BANK1 (1 << ENC_BSEL_SHIFT)
# define ENC_BANK2 (2 << ENC_BSEL_SHIFT)
# define ENC_BANK3 (3 << ENC_BSEL_SHIFT)
#define ENC_PHYMAC_SHIFT (7) /* Bit 7: This is a PHY/MAC command */
#define ENC_PHYMAC (1 << ENC_PHYMAC_SHIFT)
#define REGADDR(a,b,m) ((m) << ENC_PHYMAC_SHIFT | (b) << ENC_BANK_SHIFT | (a))
#define GETADDR(a) ((a) & ENC_ADDR_MASK)
#define GETBANK(a) (((a) >> ENC_BANK_SHIFT) & 3)
#define ISPHYMAC(a) (((a) & ENC_PHYMAC) != 0)
/* Bank 0 Control Register Addresses */
#define ENC_ERDPTL REGADDR(0x00, 0, 0) /* Read Pointer Low Byte (ERDPT<7:0> */
#define ENC_ERDPTH REGADDR(0x01, 0, 0) /* Read Pointer High Byte (ERDPT<12:8>) */
#define ENC_EWRPTL REGADDR(0x02, 0, 0) /* Write Pointer Low Byte (EWRPT<7:0>) */
#define ENC_EWRPTH REGADDR(0x03, 0, 0) /* Write Pointer High Byte (EWRPT<12:8>) */
#define ENC_ETXSTL REGADDR(0x04, 0, 0) /* TX Start Low Byte (ETXST<7:0>) */
#define ENC_ETXSTH REGADDR(0x05, 0, 0) /* TX Start High Byte (ETXST<12:8>) */
#define ENC_ETXNDL REGADDR(0x06, 0, 0) /* TX End Low Byte (ETXND<7:0>) */
#define ENC_ETXNDH REGADDR(0x07, 0, 0) /* TX End High Byte (ETXND<12:8>) */
#define ENC_ERXSTL REGADDR(0x08, 0, 0) /* RX Start Low Byte (ERXST<7:0>) */
#define ENC_ERXSTH REGADDR(0x09, 0, 0) /* RX Start High Byte (ERXST<12:8>) */
#define ENC_ERXNDL REGADDR(0x0a, 0, 0) /* RX End Low Byte (ERXND<7:0>) */
#define ENC_ERXNDH REGADDR(0x0b, 0, 0) /* RX End High Byte (ERXND<12:8>) */
#define ENC_ERXRDPTL REGADDR(0x0c, 0, 0) /* RX RD Pointer Low Byte (ERXRDPT<7:0>) */
#define ENC_ERXRDPTH REGADDR(0x0d, 0, 0) /* RX RD Pointer High Byte (ERXRDPT<12:8>) */
#define ENC_ERXWRPTL REGADDR(0x0e, 0, 0) /* RX WR Pointer Low Byte (ERXWRPT<7:0>) */
#define ENC_ERXWRPTH REGADDR(0x0f, 0, 0) /* RX WR Pointer High Byte (ERXWRPT<12:8>) */
#define ENC_EDMASTL REGADDR(0x10, 0, 0) /* DMA Start Low Byte (EDMAST<7:0>) */
#define ENC_EDMASTH REGADDR(0x11, 0, 0) /* DMA Start High Byte (EDMAST<12:8>) */
#define ENC_EDMANDL REGADDR(0x12, 0, 0) /* DMA End Low Byte (EDMAND<7:0>) */
#define ENC_EDMANDH REGADDR(0x13, 0, 0) /* DMA End High Byte (EDMAND<12:8>) */
#define ENC_EDMADSTL REGADDR(0x14, 0, 0) /* DMA Destination Low Byte (EDMADST<7:0>) */
#define ENC_EDMADSTH REGADDR(0x15, 0, 0) /* DMA Destination High Byte (EDMADST<12:8>) */
#define ENC_EDMACSL REGADDR(0x16, 0, 0) /* DMA Checksum Low Byte (EDMACS<7:0>) */
#define ENC_EDMACSH REGADDR(0x17, 0, 0) /* DMA Checksum High Byte (EDMACS<15:8>) */
/* 0x18-0x1a: Reserved */
/* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */
/* Bank 1 Control Register Addresses */
#define ENC_EHT0 REGADDR(0x00, 1, 0) /* Hash Table Byte 0 (EHT<7:0>) */
#define ENC_EHT1 REGADDR(0x01, 1, 0) /* Hash Table Byte 1 (EHT<15:8>) */
#define ENC_EHT2 REGADDR(0x02, 1, 0) /* Hash Table Byte 2 (EHT<23:16>) */
#define ENC_EHT3 REGADDR(0x03, 1, 0) /* Hash Table Byte 3 (EHT<31:24>) */
#define ENC_EHT4 REGADDR(0x04, 1, 0) /* Hash Table Byte 4 (EHT<39:32>) */
#define ENC_EHT5 REGADDR(0x05, 1, 0) /* Hash Table Byte 5 (EHT<47:40>) */
#define ENC_EHT6 REGADDR(0x06, 1, 0) /* Hash Table Byte 6 (EHT<55:48>) */
#define ENC_EHT7 REGADDR(0x07, 1, 0) /* Hash Table Byte 7 (EHT<63:56>) */
#define ENC_EPMM0 REGADDR(0x08, 1, 0) /* Pattern Match Mask Byte 0 (EPMM<7:0>) */
#define ENC_EPMM1 REGADDR(0x09, 1, 0) /* Pattern Match Mask Byte 1 (EPMM<15:8>) */
#define ENC_EPMM2 REGADDR(0x0a, 1, 0) /* Pattern Match Mask Byte 2 (EPMM<23:16>) */
#define ENC_EPMM3 REGADDR(0x0b, 1, 0) /* Pattern Match Mask Byte 3 (EPMM<31:24>) */
#define ENC_EPMM4 REGADDR(0x0c, 1, 0) /* Pattern Match Mask Byte 4 (EPMM<39:32>) */
#define ENC_EPMM5 REGADDR(0x0d, 1, 0) /* Pattern Match Mask Byte 5 (EPMM<47:40>) */
#define ENC_EPMM6 REGADDR(0x0e, 1, 0) /* Pattern Match Mask Byte 6 (EPMM<55:48>) */
#define ENC_EPMM7 REGADDR(0x0f, 1, 0) /* Pattern Match Mask Byte 7 (EPMM<63:56>) */
#define ENC_EPMCSL REGADDR(0x10, 1, 0) /* Pattern Match Checksum Low Byte (EPMCS<7:0>) */
#define ENC_EPMCSH REGADDR(0x11, 1, 0) /* Pattern Match Checksum High Byte (EPMCS<15:0>) */
/* 0x12-0x13: Reserved */
#define ENC_EPMOL REGADDR(0x14, 1, 0) /* Pattern Match Offset Low Byte (EPMO<7:0>) */
#define ENC_EPMOH REGADDR(0x15, 1, 0) /* Pattern Match Offset High Byte (EPMO<12:8>) */
/* 0x16-0x17: Reserved */
#define ENC_ERXFCON REGADDR(0x18, 1, 0) /* Receive Filter Configuration */
#define ENC_EPKTCNT REGADDR(0x19, 1, 0) /* Ethernet Packet Count */
/* 0x1a: Reserved */
/* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */
/* Receive Filter Configuration Bit Definitions */
#define ERXFCON_BCEN (1 << 0) /* Bit 0: Broadcast Filter Enable */
#define ERXFCON_MCEN (1 << 1) /* Bit 1: Multicast Filter Enable */
#define ERXFCON_HTEN (1 << 2) /* Bit 2: Hash Table Filter Enable */
#define ERXFCON_MPEN (1 << 3) /* Bit 3: Magic Packet Filter Enable */
#define ERXFCON_PMEN (1 << 4) /* Bit 4: Pattern Match Filter Enable */
#define ERXFCON_CRCEN (1 << 5) /* Bit 5: Post-Filter CRC Check Enable */
#define ERXFCON_ANDOR (1 << 6) /* Bit 6: AND/OR Filter Select */
#define ERXFCON_UCEN (1 << 7) /* Bit 7: Unicast Filter Enable */
/* Bank 2 Control Register Addresses */
#define ENC_MACON1 REGADDR(0x00, 2, 1) /* MAC Control 1 */
/* 0x01: Reserved */
#define ENC_MACON3 REGADDR(0x02, 2, 1) /* MAC Control 3 */
#define ENC_MACON4 REGADDR(0x03, 2, 1) /* MAC Control 4 */
#define ENC_MABBIPG REGADDR(0x04, 2, 1) /* Back-to-Back Inter-Packet Gap (BBIPG<6:0>) */
/* 0x05: Reserved */
#define ENC_MAIPGL REGADDR(0x06, 2, 1) /* Non-Back-to-Back Inter-Packet Gap Low Byte (MAIPGL<6:0>) */
#define ENC_MAIPGH REGADDR(0x07, 2, 1) /* Non-Back-to-Back Inter-Packet Gap High Byte (MAIPGH<6:0>) */
#define ENC_MACLCON1 REGADDR(0x08, 2, 1) /* MAC Collision Control 1 */
#define ENC_MACLCON2 REGADDR(0x09, 2, 1) /* MAC Collision Control 2 */
#define ENC_MAMXFLL REGADDR(0x0a, 2, 1) /* Maximum Frame Length Low Byte (MAMXFL<7:0>) */
#define ENC_MAMXFLH REGADDR(0x0b, 2, 1) /* Maximum Frame Length High Byte (MAMXFL<15:8>) */
/* 0x0c-0x11: Reserved */
#define ENC_MICMD REGADDR(0x12, 2, 1) /* MII Command Register */
/* 0x13: Reserved */
#define ENC_MIREGADR REGADDR(0x14, 2, 1) /* MII Register Address */
/* 0x15: Reserved */
#define ENC_MIWRL REGADDR(0x16, 2, 1) /* MII Write Data Low Byte (MIWR<7:0>) */
#define ENC_MIWRH REGADDR(0x17, 2, 1) /* MII Write Data High Byte (MIWR<15:8>) */
#define ENC_MIRDL REGADDR(0x18, 2, 1) /* MII Read Data Low Byte (MIRD<7:0>) */
#define ENC_MIRDH REGADDR(0x19, 2, 1) /* MII Read Data High Byte(MIRD<15:8>) */
/* 0x1a: Reserved */
/* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */
/* MAC Control 1 Register Bit Definitions */
#define MACON1_MARXEN (1 << 0) /* Bit 0: MAC Receive Enable */
#define MACON1_PASSALL (1 << 1) /* Bit 1: Pass All Received Frames Enable */
#define MACON1_RXPAUS (1 << 2) /* Bit 2: Pause Control Frame Reception Enable */
#define MACON1_TXPAUS (1 << 3) /* Bit 3: Pause Control Frame Transmission Enable */
/* Bits 4-7: Unimplemented or reserved */
/* MAC Control 1 Register Bit Definitions */
#define MACON3_FULDPX (1 << 0) /* Bit 0: MAC Full-Duplex Enable */
#define MACON3_FRMLNEN (1 << 1) /* Bit 1: Frame Length Checking Enable */
#define MACON3_HFRMLEN (1 << 2) /* Bit 2: Huge Frame Enable */
#define MACON3_PHDRLEN (1 << 3) /* Bit 3: Proprietary Header Enable */
#define MACON3_TXCRCEN (1 << 4) /* Bit 4: Transmit CRC Enable */
#define MACON3_PADCFG0 (1 << 5) /* Bit 5: Automatic Pad and CRC Configuration */
#define MACON3_PADCFG1 (1 << 6) /* Bit 6: " " " " " " " " " " */
#define MACON3_PADCFG2 (1 << 7) /* Bit 7: " " " " " " " " " " */
/* MAC Control 1 Register Bit Definitions */
#define MACON4_NOBKOFF (1 << 4) /* Bit 4: No Backoff Enable */
#define MACON4_BPEN (1 << 5) /* Bit 5: No Backoff During Backpressure Enable */
#define MACON4_DEFER (1 << 6) /* Bit 6: Defer Transmission Enable bit */
/* MII Command Register Bit Definitions */
#define MICMD_MIIRD (1 << 0) /* Bit 0: MII Read Enable */
#define MICMD_MIISCAN (1 << 1) /* Bit 1: MII Scan Enable */
/* Bank 3 Control Register Addresses */
#define ENC_MAADR5 REGADDR(0x00, 3, 1) /* MAC Address Byte 5 (MAADR<15:8>) */
#define ENC_MAADR6 REGADDR(0x01, 3, 1) /* MAC Address Byte 6 (MAADR<7:0>) */
#define ENC_MAADR3 REGADDR(0x02, 3, 1) /* MAC Address Byte 3 (MAADR<31:24>), OUI Byte 3 */
#define ENC_MAADR4 REGADDR(0x03, 3, 1) /* MAC Address Byte 4 (MAADR<23:16>) */
#define ENC_MAADR1 REGADDR(0x04, 3, 1) /* MAC Address Byte 1 (MAADR<47:40>), OUI Byte 1 */
#define ENC_MAADR2 REGADDR(0x05, 3, 1) /* MAC Address Byte 2 (MAADR<39:32>), OUI Byte */
#define ENC_EBSTSD REGADDR(0x06, 3, 0) /* Built-in Self-Test Fill Seed (EBSTSD<7:0>) */
#define ENC_EBSTCON REGADDR(0x07, 3, 0) /* Built-in Self-Test Control */
#define ENC_EBSTCSL REGADDR(0x08, 3, 0) /* Built-in Self-Test Checksum Low Byte (EBSTCS<7:0>) */
#define ENC_EBSTCSH REGADDR(0x09, 3, 0) /* Built-in Self-Test Checksum High Byte (EBSTCS<15:8>) */
#define ENC_MISTAT REGADDR(0x0a, 3, 1) /* MII Status Register */
/* 0x0b-0x11: Reserved */
#define ENC_EREVID REGADDR(0x12, 3, 0) /* Ethernet Revision ID */
/* 0x13-0x14: Reserved */
#define ENC_ECOCON REGADDR(0x15, 3, 0) /* Clock Output Control */
/* 0x16: Reserved */
#define ENC_EFLOCON REGADDR(0x17, 3, 0) /* Ethernet Flow Control */
#define ENC_EPAUSL REGADDR(0x18, 3, 0) /* Pause Timer Value Low Byte (EPAUS<7:0>) */
#define ENC_EPAUSH REGADDR(0x19, 3, 0) /* Pause Timer Value High Byte (EPAUS<15:8>) */
/* 0x1a: Reserved */
/* 0x1b-0x1f: EIE, EIR, ESTAT, ECON2, ECON1 */
/* Built-in Self-Test Control Register Bit Definitions */
#define EBSTCON_BISTST (1 << 0) /* Bit 0: Built-in Self-Test Start/Busy */
#define EBSTCON_TME (1 << 1) /* Bit 1: Test Mode Enable */
#define EBSTCON_TMSEL0 (1 << 2) /* Bit 2: Test Mode Select */
#define EBSTCON_TMSEL1 (1 << 3) /* Bit 3: " " " " " " */
#define EBSTCON_PSEL (1 << 4) /* Bit 4: Port Select */
#define EBSTCON_PSV0 (1 << 5) /* Bit 5: Pattern Shift Value */
#define EBSTCON_PSV1 (1 << 6) /* Bit 6: " " " " " */
#define EBSTCON_PSV2 (1 << 7) /* Bit 7: " " " " " */
/* MII Status Register Register Bit Definitions */
#define MISTAT_BUSY (1 << 0) /* Bit 0: MII Management Busy */
#define MISTAT_SCAN (1 << 1) /* Bit 1: MII Management Scan Operation */
#define MISTAT_NVALID (1 << 2) /* Bit 2: MII Management Read Data Not Valid */
/* Bits 3-7: Reserved or unimplemented */
/* Ethernet Flow Control Register Bit Definitions */
#define EFLOCON_FCEN0 (1 << 0) /* Bit 0: Flow Control Enable */
#define EFLOCON_FCEN1 (1 << 1) /* Bit 1: " " " " " " */
#define EFLOCON_FULDPXS (1 << 2) /* Bit 2: Read-Only MAC Full-Duplex Shadow */
/* Bits 3-7: Reserved or unimplemented */
/* PHY Registers ************************************************************/
#define ENC_PHCON1 (0x00) /* PHY Control Register 1 */
#define ENC_PHSTAT1 (0x01) /* PHY Status 1 */
#define ENC_PHID1 (0x02) /* PHY ID Register 1 */
#define ENC_PHID2 (0x03) /* PHY ID Register 2 */
#define ENC_PHCON2 (0x10) /* PHY Control Register 2 */
#define ENC_PHSTAT2 (0x11) /* PHY Status 2 */
#define ENC_PHIE (0x12) /* PHY Interrupt Enable Register */
#define ENC_PHIR (0x13) /* PHY Interrupt Request Register */
#define ENC_PHLCON (0x14)
/* PHY Control Register 1 Register Bit Definitions */
#define PHCON1_PDPXMD (1 << 8) /* Bit 8: PHY Power-Down */
#define PHCON1_PPWRSV (1 << 11) /* Bit 11: PHY Power-Down */
#define PHCON1_PLOOPBK (1 << 14) /* Bit 14: PHY Loopback */
#define PHCON1_PRST (1 << 15) /* Bit 15: PHY Software Reset */
/* HY Status 1 Register Bit Definitions */
#define PHSTAT1_JBSTAT (1 << 1) /* Bit 1: PHY Latching Jabber Status */
#define PHSTAT1_LLSTAT (1 << 2) /* Bit 2: PHY Latching Link Status */
#define PHSTAT1_PHDPX (1 << 11) /* Bit 11: PHY Half-Duplex Capable */
#define PHSTAT1_PFDPX (1 << 12) /* Bit 12: PHY Full-Duplex Capable */
/* PHY Control Register 2 Register Bit Definitions */
#define PHCON2_HDLDIS (1 << 8) /* Bit 8: PHY Half-Duplex Loopback Disable */
#define PHCON2_JABBER (1 << 10) /* Bit 10: Jabber Correction Disable */
#define PHCON2_TXDIS (1 << 13) /* Bit 13: Twisted-Pair Transmitter Disable */
#define PHCON2_FRCLINK (1 << 14) /* Bit 14: PHY Force Linkup */
/* PHY Status 2 Register Bit Definitions */
#define PHSTAT2_PLRITY (1 << 5) /* Bit 5: Polarity Status */
#define PHSTAT2_DPXSTAT (1 << 9) /* Bit 9: PHY Duplex Status */
#define PHSTAT2_LSTAT (1 << 10) /* Bit 10: PHY Link Status */
#define PHSTAT2_COLSTAT (1 << 11) /* Bit 11: PHY Collision Status */
#define PHSTAT2_RXSTAT (1 << 12) /* Bit 12: PHY Receive Status */
#define PHSTAT2_TXSTAT (1 << 13) /* Bit 13: PHY Transmit Status */
/* PHY Interrupt Enable Register Bit Definitions */
#define PHIE_PGEIE (1 << 1) /* Bit 1: PHY Global Interrupt Enable */
#define PHIE_PLNKIE (1 << 4) /* Bit 4: PHY Link Change Interrupt Enable */
/* PHIR Regiser Bit Definitions */
#define PHIR_PGIF (1 << 2) /* Bit 2: PHY Global Interrupt */
#define PHIR_PLNKIF (1 << 4) /* Bit 4: PHY Link Change Interrupt */
/* PHLCON Regiser Bit Definitions */
/* Bit 0: Reserved */
#define PHLCON_STRCH (1 << 1) /* Bit 1: LED Pulse Stretching Enable */
#define PHLCON_LFRQ0 (1 << 2) /* Bit 2: LED Pulse Stretch Time Configuration */
#define PHLCON_LFRQ1 (1 << 3) /* Bit 3: " " " " " " " " " */
#define PHLCON_LBCFG0 (1 << 4) /* Bit 4: LEDB Configuration */
#define PHLCON_LBCFG1 (1 << 5) /* Bit 5: " " " " */
#define PHLCON_LBCFG2 (1 << 6) /* Bit 6: " " " " */
#define PHLCON_LBCFG3 (1 << 7) /* Bit 7: " " " " */
#define PHLCON_LACFG0 (1 << 8) /* Bit 8: LEDA Configuration */
#define PHLCON_LACFG1 (1 << 9) /* Bit 9: " " " " */
#define PHLCON_LACFG2 (1 << 10) /* Bit 10: " " " " */
#define PHLCON_LACFG3 (1 << 11) /* Bit 11: " " " " */
/* Packet Memory ************************************************************/
/* 8-Kbyte Transmit/Receive Packet Dual Port SRAM */
#define PKTMEM_START 0x0000
#define PKTMEM_END 0x1fff
/* Ethernet frames are between 64 and 1518 bytes long */
#define MIN_FRAMELEN 64
#define MAX_FRAMELEN 1518
/* Packet Control Bits Definitions ******************************************/
#define PKTCTRL_POVERRIDE (1 << 0) /* Bit 0: Per Packet Override */
#define PKTCTRL_PCRCEN (1 << 1) /* Bit 1: Per Packet CRC Enable */
#define PKTCTRL_PPADEN (1 << 2) /* Bit 2: Per Packet Padding Enable */
#define PKTCTRL_PHUGEEN (1 << 3) /* Bit 3: Per Packet Huge Frame Enable */
/* RX Status Bit Definitions ************************************************/
#define RXSTAT_LDEVENT (1 << 0) /* Bit 0: Long event or pack dropped */
/* Bit 1: Reserved */
#define RXSTAT_CEPS (1 << 2) /* Bit 2: Carrier event previously seen */
/* Bit 3: Reserved */
#define RXSTAT_CRCERROR (1 << 4) /* Bit 4: Frame CRC field bad */
#define RXSTAT_LENERROR (1 << 5) /* Bit 5: Packet length != data length */
#define RXSTAT_LENRANGE (1 << 6) /* Bit 6: Type/length field > 1500 bytes */
#define RXSTAT_OK (1 << 7) /* Bit 7: Packet with valid CRC and no symbol errors */
#define RXSTAT_MCAST (1 << 8) /* Bit 8: Packet with multicast address */
#define RXSTAT_BCAST (1 << 9) /* Bit 9: Packet with broadcast address */
#define RXSTAT_DRIBBLE (1 << 10) /* Bit 10: Additional bits received after packet */
#define RXSTAT_CTRLFRAME (1 << 11) /* Bit 11: Control frame with valid type/length */
#define RXSTAT_PAUSE (1 << 12) /* Bit 12: Control frame with pause frame opcde */
#define RXSTAT_UNKOPCODE (1 << 13) /* Bit 13: Control frame with unknown opcode */
#define RXSTAT_VLANTYPE (1 << 14) /* Bit 14: Current frame is a VLAN tagged frame */
/* Bit 15: Zero */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __DRIVERS_NET_ENC28J60_H */
nuttx/drivers/net/skeleton.c
+692
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@@ -0,0 +1,692 @@
/****************************************************************************
* drivers/net/skeleton.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_NET) && defined(CONFIG_NET_skeleton)
#include <stdint.h>
#include <stdbool.h>
#include <time.h>
#include <string.h>
#include <debug.h>
#include <wdog.h>
#include <errno.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/net/uip/uip.h>
#include <nuttx/net/uip/uip-arp.h>
#include <nuttx/net/uip/uip-arch.h>
/****************************************************************************
* Definitions
****************************************************************************/
/* CONFIG_skeleton_NINTERFACES determines the number of physical interfaces
* that will be supported.
*/
#ifndef CONFIG_skeleton_NINTERFACES
# define CONFIG_skeleton_NINTERFACES 1
#endif
/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per second */
#define skeleton_WDDELAY (1*CLK_TCK)
#define skeleton_POLLHSEC (1*2)
/* TX timeout = 1 minute */
#define skeleton_TXTIMEOUT (60*CLK_TCK)
/* This is a helper pointer for accessing the contents of the Ethernet header */
#define BUF ((struct uip_eth_hdr *)skel->sk_dev.d_buf)
/****************************************************************************
* Private Types
****************************************************************************/
/* The skel_driver_s encapsulates all state information for a single hardware
* interface
*/
struct skel_driver_s
{
bool sk_bifup; /* true:ifup false:ifdown */
WDOG_ID sk_txpoll; /* TX poll timer */
WDOG_ID sk_txtimeout; /* TX timeout timer */
/* This holds the information visible to uIP/NuttX */
struct uip_driver_s sk_dev; /* Interface understood by uIP */
};
/****************************************************************************
* Private Data
****************************************************************************/
static struct skel_driver_s g_skel[CONFIG_skeleton_NINTERFACES];
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* Common TX logic */
static int skel_transmit(FAR struct skel_driver_s *skel);
static int skel_uiptxpoll(struct uip_driver_s *dev);
/* Interrupt handling */
static void skel_receive(FAR struct skel_driver_s *skel);
static void skel_txdone(FAR struct skel_driver_s *skel);
static int skel_interrupt(int irq, FAR void *context);
/* Watchdog timer expirations */
static void skel_polltimer(int argc, uint32_t arg, ...);
static void skel_txtimeout(int argc, uint32_t arg, ...);
/* NuttX callback functions */
static int skel_ifup(struct uip_driver_s *dev);
static int skel_ifdown(struct uip_driver_s *dev);
static int skel_txavail(struct uip_driver_s *dev);
#ifdef CONFIG_NET_IGMP
static int skel_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac);
static int skel_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac);
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Function: skel_transmit
*
* Description:
* Start hardware transmission. Called either from the txdone interrupt
* handling or from watchdog based polling.
*
* Parameters:
* skel - Reference to the driver state structure
*
* Returned Value:
* OK on success; a negated errno on failure
*
* Assumptions:
* May or may not be called from an interrupt handler. In either case,
* global interrupts are disabled, either explicitly or indirectly through
* interrupt handling logic.
*
****************************************************************************/
static int skel_transmit(FAR struct skel_driver_s *skel)
{
/* Verify that the hardware is ready to send another packet. If we get
* here, then we are committed to sending a packet; Higher level logic
* must have assured that there is no transmission in progress.
*/
/* Increment statistics */
/* Send the packet: address=skel->sk_dev.d_buf, length=skel->sk_dev.d_len */
/* Enable Tx interrupts */
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
(void)wd_start(skel->sk_txtimeout, skeleton_TXTIMEOUT, skel_txtimeout, 1, (uint32_t)skel);
return OK;
}
/****************************************************************************
* Function: skel_uiptxpoll
*
* Description:
* The transmitter is available, check if uIP has any outgoing packets ready
* to send. This is a callback from uip_poll(). uip_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
* 2. When the preceding TX packet send timesout and the interface is reset
* 3. During normal TX polling
*
* Parameters:
* dev - Reference to the NuttX driver state structure
*
* Returned Value:
* OK on success; a negated errno on failure
*
* Assumptions:
* May or may not be called from an interrupt handler. In either case,
* global interrupts are disabled, either explicitly or indirectly through
* interrupt handling logic.
*
****************************************************************************/
static int skel_uiptxpoll(struct uip_driver_s *dev)
{
FAR struct skel_driver_s *skel = (FAR struct skel_driver_s *)dev->d_private;
/* If the polling resulted in data that should be sent out on the network,
* the field d_len is set to a value > 0.
*/
if (skel->sk_dev.d_len > 0)
{
uip_arp_out(&skel->sk_dev);
skel_transmit(skel);
/* Check if there is room in the device to hold another packet. If not,
* return a non-zero value to terminate the poll.
*/
}
/* If zero is returned, the polling will continue until all connections have
* been examined.
*/
return 0;
}
/****************************************************************************
* Function: skel_receive
*
* Description:
* An interrupt was received indicating the availability of a new RX packet
*
* Parameters:
* skel - Reference to the driver state structure
*
* Returned Value:
* None
*
* Assumptions:
* Global interrupts are disabled by interrupt handling logic.
*
****************************************************************************/
static void skel_receive(FAR struct skel_driver_s *skel)
{
do
{
/* Check for errors and update statistics */
/* Check if the packet is a valid size for the uIP buffer configuration */
/* Copy the data data from the hardware to skel->sk_dev.d_buf. Set
* amount of data in skel->sk_dev.d_len
*/
/* We only accept IP packets of the configured type and ARP packets */
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(UIP_ETHTYPE_IP6))
#else
if (BUF->type == HTONS(UIP_ETHTYPE_IP))
#endif
{
uip_arp_ipin(&skel->sk_dev);
uip_input(&skel->sk_dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
*/
if (skel->sk_dev.d_len > 0)
{
uip_arp_out(&skel->sk_dev);
skel_transmit(skel);
}
}
else if (BUF->type == htons(UIP_ETHTYPE_ARP))
{
uip_arp_arpin(&skel->sk_dev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
*/
if (skel->sk_dev.d_len > 0)
{
skel_transmit(skel);
}
}
}
while (); /* While there are more packets to be processed */
}
/****************************************************************************
* Function: skel_txdone
*
* Description:
* An interrupt was received indicating that the last TX packet(s) is done
*
* Parameters:
* skel - Reference to the driver state structure
*
* Returned Value:
* None
*
* Assumptions:
* Global interrupts are disabled by the watchdog logic.
*
****************************************************************************/
static void skel_txdone(FAR struct skel_driver_s *skel)
{
/* Check for errors and update statistics */
/* If no further xmits are pending, then cancel the TX timeout and
* disable further Tx interrupts.
*/
wd_cancel(skel->sk_txtimeout);
/* Then poll uIP for new XMIT data */
(void)uip_poll(&skel->sk_dev, skel_uiptxpoll);
}
/****************************************************************************
* Function: skel_interrupt
*
* Description:
* Hardware interrupt handler
*
* Parameters:
* irq - Number of the IRQ that generated the interrupt
* context - Interrupt register state save info (architecture-specific)
*
* Returned Value:
* OK on success
*
* Assumptions:
*
****************************************************************************/
static int skel_interrupt(int irq, FAR void *context)
{
register FAR struct skel_driver_s *skel = &g_skel[0];
/* Get and clear interrupt status bits */
/* Handle interrupts according to status bit settings */
/* Check if we received an incoming packet, if so, call skel_receive() */
skel_receive(skel);
/* Check if a packet transmission just completed. If so, call skel_txdone.
* This may disable further Tx interrupts if there are no pending
* tansmissions.
*/
skel_txdone(skel);
return OK;
}
/****************************************************************************
* Function: skel_txtimeout
*
* Description:
* Our TX watchdog timed out. Called from the timer interrupt handler.
* The last TX never completed. Reset the hardware and start again.
*
* Parameters:
* argc - The number of available arguments
* arg - The first argument
*
* Returned Value:
* None
*
* Assumptions:
* Global interrupts are disabled by the watchdog logic.
*
****************************************************************************/
static void skel_txtimeout(int argc, uint32_t arg, ...)
{
FAR struct skel_driver_s *skel = (FAR struct skel_driver_s *)arg;
/* Increment statistics and dump debug info */
/* Then reset the hardware */
/* Then poll uIP for new XMIT data */
(void)uip_poll(&skel->sk_dev, skel_uiptxpoll);
}
/****************************************************************************
* Function: skel_polltimer
*
* Description:
* Periodic timer handler. Called from the timer interrupt handler.
*
* Parameters:
* argc - The number of available arguments
* arg - The first argument
*
* Returned Value:
* None
*
* Assumptions:
* Global interrupts are disabled by the watchdog logic.
*
****************************************************************************/
static void skel_polltimer(int argc, uint32_t arg, ...)
{
FAR struct skel_driver_s *skel = (FAR struct skel_driver_s *)arg;
/* Check if there is room in the send another TX packet. We cannot perform
* the TX poll if he are unable to accept another packet for transmission.
*/
/* If so, update TCP timing states and poll uIP for new XMIT data. Hmmm..
* might be bug here. Does this mean if there is a transmit in progress,
* we will missing TCP time state updates?
*/
(void)uip_timer(&skel->sk_dev, skel_uiptxpoll, skeleton_POLLHSEC);
/* Setup the watchdog poll timer again */
(void)wd_start(skel->sk_txpoll, skeleton_WDDELAY, skel_polltimer, 1, arg);
}
/****************************************************************************
* Function: skel_ifup
*
* Description:
* NuttX Callback: Bring up the Ethernet interface when an IP address is
* provided
*
* Parameters:
* dev - Reference to the NuttX driver state structure
*
* Returned Value:
* None
*
* Assumptions:
*
****************************************************************************/
static int skel_ifup(struct uip_driver_s *dev)
{
FAR struct skel_driver_s *skel = (FAR struct skel_driver_s *)dev->d_private;
ndbg("Bringing up: %d.%d.%d.%d\n",
dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
(dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 );
/* Initialize PHYs, the Ethernet interface, and setup up Ethernet interrupts */
/* Set and activate a timer process */
(void)wd_start(skel->sk_txpoll, skeleton_WDDELAY, skel_polltimer, 1, (uint32_t)skel);
/* Enable the Ethernet interrupt */
skel->sk_bifup = true;
up_enable_irq(CONFIG_skeleton_IRQ);
return OK;
}
/****************************************************************************
* Function: skel_ifdown
*
* Description:
* NuttX Callback: Stop the interface.
*
* Parameters:
* dev - Reference to the NuttX driver state structure
*
* Returned Value:
* None
*
* Assumptions:
*
****************************************************************************/
static int skel_ifdown(struct uip_driver_s *dev)
{
FAR struct skel_driver_s *skel = (FAR struct skel_driver_s *)dev->d_private;
irqstate_t flags;
/* Disable the Ethernet interrupt */
flags = irqsave();
up_disable_irq(CONFIG_skeleton_IRQ);
/* Cancel the TX poll timer and TX timeout timers */
wd_cancel(skel->sk_txpoll);
wd_cancel(skel->sk_txtimeout);
/* Put the EMAC in its reset, non-operational state. This should be
* a known configuration that will guarantee the skel_ifup() always
* successfully brings the interface back up.
*/
/* Mark the device "down" */
skel->sk_bifup = false;
irqrestore(flags);
return OK;
}
/****************************************************************************
* Function: skel_txavail
*
* Description:
* Driver callback invoked when new TX data is available. This is a
* stimulus perform an out-of-cycle poll and, thereby, reduce the TX
* latency.
*
* Parameters:
* dev - Reference to the NuttX driver state structure
*
* Returned Value:
* None
*
* Assumptions:
* Called in normal user mode
*
****************************************************************************/
static int skel_txavail(struct uip_driver_s *dev)
{
FAR struct skel_driver_s *skel = (FAR struct skel_driver_s *)dev->d_private;
irqstate_t flags;
/* Disable interrupts because this function may be called from interrupt
* level processing.
*/
flags = irqsave();
/* Ignore the notification if the interface is not yet up */
if (skel->sk_bifup)
{
/* Check if there is room in the hardware to hold another outgoing packet. */
/* If so, then poll uIP for new XMIT data */
(void)uip_poll(&skel->sk_dev, skel_uiptxpoll);
}
irqrestore(flags);
return OK;
}
/****************************************************************************
* Function: skel_addmac
*
* Description:
* NuttX Callback: Add the specified MAC address to the hardware multicast
* address filtering
*
* Parameters:
* dev - Reference to the NuttX driver state structure
* mac - The MAC address to be added
*
* Returned Value:
* None
*
* Assumptions:
*
****************************************************************************/
#ifdef CONFIG_NET_IGMP
static int skel_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac)
{
FAR struct skel_driver_s *skel = (FAR struct skel_driver_s *)dev->d_private;
/* Add the MAC address to the hardware multicast routing table */
return OK;
}
#endif
/****************************************************************************
* Function: skel_rmmac
*
* Description:
* NuttX Callback: Remove the specified MAC address from the hardware multicast
* address filtering
*
* Parameters:
* dev - Reference to the NuttX driver state structure
* mac - The MAC address to be removed
*
* Returned Value:
* None
*
* Assumptions:
*
****************************************************************************/
#ifdef CONFIG_NET_IGMP
static int skel_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac)
{
FAR struct skel_driver_s *skel = (FAR struct skel_driver_s *)dev->d_private;
/* Add the MAC address to the hardware multicast routing table */
return OK;
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: skel_initialize
*
* Description:
* Initialize the Ethernet controller and driver
*
* Parameters:
* intf - In the case where there are multiple EMACs, this value
* identifies which EMAC is to be initialized.
*
* Returned Value:
* OK on success; Negated errno on failure.
*
* Assumptions:
*
****************************************************************************/
int skel_initialize(int intf)
{
struct skel_driver_s *priv;
/* Get the interface structure associated with this interface number. */
DEBUGASSERT(inf < CONFIG_skeleton_NINTERFACES);
priv = &g_skel[intf];
/* Check if a Ethernet chip is recognized at its I/O base */
/* Attach the IRQ to the driver */
if (irq_attach(CONFIG_skeleton_IRQ, skel_interrupt))
{
/* We could not attach the ISR to the interrupt */
return -EAGAIN;
}
/* Initialize the driver structure */
memset(priv, 0, sizeof(struct skel_driver_s));
priv->sk_dev.d_ifup = skel_ifup; /* I/F up (new IP address) callback */
priv->sk_dev.d_ifdown = skel_ifdown; /* I/F down callback */
priv->sk_dev.d_txavail = skel_txavail; /* New TX data callback */
#ifdef CONFIG_NET_IGMP
priv->sk_dev.d_addmac = skel_addmac; /* Add multicast MAC address */
priv->sk_dev.d_rmmac = skel_rmmac; /* Remove multicast MAC address */
#endif
priv->sk_dev.d_private = (void*)g_skel; /* Used to recover private state from dev */
/* Create a watchdog for timing polling for and timing of transmisstions */
priv->sk_txpoll = wd_create(); /* Create periodic poll timer */
priv->sk_txtimeout = wd_create(); /* Create TX timeout timer */
/* Put the interface in the down state. This usually amounts to resetting
* the device and/or calling skel_ifdown().
*/
/* Read the MAC address from the hardware into priv->sk_dev.d_mac.ether_addr_octet */
/* Register the device with the OS so that socket IOCTLs can be performed */
(void)netdev_register(&priv->sk_dev);
return OK;
}
#endif /* CONFIG_NET && CONFIG_NET_skeleton */
nuttx/drivers/net/slip.c
+1017
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nuttx/drivers/net/vnet.c
+673
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@@ -0,0 +1,673 @@
/****************************************************************************
* drivers/net/vnet.c
*
* Copyright (C) 2011 Yu Qiang. All rights reserved.
* Author: Yu Qiang <yuq825@gmail.com>
*
* This file is a part of NuttX:
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_NET) && defined(CONFIG_NET_VNET)
#include <stdint.h>
#include <stdbool.h>
#include <time.h>
#include <string.h>
#include <debug.h>
#include <wdog.h>
#include <errno.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/net/uip/uip.h>
#include <nuttx/net/uip/uip-arp.h>
#include <nuttx/net/uip/uip-arch.h>
#include <rgmp/vnet.h>
#include <rgmp/stdio.h>
/****************************************************************************
* Definitions
****************************************************************************/
/* CONFIG_VNET_NINTERFACES determines the number of physical interfaces
* that will be supported.
*/
#ifndef CONFIG_VNET_NINTERFACES
# define CONFIG_VNET_NINTERFACES 1
#endif
/* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */
#define VNET_WDDELAY (1*CLK_TCK)
#define VNET_POLLHSEC (1*2)
/* TX timeout = 1 minute */
#define VNET_TXTIMEOUT (60*CLK_TCK)
/* This is a helper pointer for accessing the contents of the Ethernet header */
#define BUF ((struct uip_eth_hdr *)vnet->sk_dev.d_buf)
/****************************************************************************
* Private Types
****************************************************************************/
/* The vnet_driver_s encapsulates all state information for a single hardware
* interface
*/
struct vnet_driver_s
{
bool sk_bifup; /* true:ifup false:ifdown */
WDOG_ID sk_txpoll; /* TX poll timer */
//WDOG_ID sk_txtimeout; /* TX timeout timer */
/* This holds the information visible to uIP/NuttX */
struct rgmp_vnet *vnet;
struct uip_driver_s sk_dev; /* Interface understood by uIP */
};
/****************************************************************************
* Private Data
****************************************************************************/
static struct vnet_driver_s g_vnet[CONFIG_VNET_NINTERFACES];
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* Common TX logic */
static int vnet_transmit(FAR struct vnet_driver_s *vnet);
static int vnet_uiptxpoll(struct uip_driver_s *dev);
/* Interrupt handling */
static void vnet_txdone(FAR struct vnet_driver_s *vnet);
/* Watchdog timer expirations */
static void vnet_polltimer(int argc, uint32_t arg, ...);
static void vnet_txtimeout(int argc, uint32_t arg, ...);
/* NuttX callback functions */
static int vnet_ifup(struct uip_driver_s *dev);
static int vnet_ifdown(struct uip_driver_s *dev);
static int vnet_txavail(struct uip_driver_s *dev);
#ifdef CONFIG_NET_IGMP
static int vnet_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac);
static int vnet_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac);
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Function: vnet_transmit
*
* Description:
* Start hardware transmission. Called either from the txdone interrupt
* handling or from watchdog based polling.
*
* Parameters:
* vnet - Reference to the driver state structure
*
* Returned Value:
* OK on success; a negated errno on failure
*
* Assumptions:
* May or may not be called from an interrupt handler. In either case,
* global interrupts are disabled, either explicitly or indirectly through
* interrupt handling logic.
*
****************************************************************************/
static int vnet_transmit(FAR struct vnet_driver_s *vnet)
{
int err;
/* Verify that the hardware is ready to send another packet. If we get
* here, then we are committed to sending a packet; Higher level logic
* must have assured that there is not transmission in progress.
*/
/* Increment statistics */
/* Send the packet: address=vnet->sk_dev.d_buf, length=vnet->sk_dev.d_len */
err = vnet_xmit(vnet->vnet, (char *)vnet->sk_dev.d_buf, vnet->sk_dev.d_len);
if (err) {
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
//(void)wd_start(vnet->sk_txtimeout, VNET_TXTIMEOUT, vnet_txtimeout, 1, (uint32_t)vnet);
// When vnet_xmit fail, it means TX buffer is full. Watchdog
// is of no use here because no TX done INT will happen. So
// we reset the TX buffer directly.
#ifdef CONFIG_DEBUG
cprintf("VNET: TX buffer is full\n");
#endif
return ERROR;
}
else {
// this step may be unnecessary here
vnet_txdone(vnet);
}
return OK;
}
/****************************************************************************
* Function: vnet_uiptxpoll
*
* Description:
* The transmitter is available, check if uIP has any outgoing packets ready
* to send. This is a callback from uip_poll(). uip_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
* 2. When the preceding TX packet send timesout and the interface is reset
* 3. During normal TX polling
*
* Parameters:
* dev - Reference to the NuttX driver state structure
*
* Returned Value:
* OK on success; a negated errno on failure
*
* Assumptions:
* May or may not be called from an interrupt handler. In either case,
* global interrupts are disabled, either explicitly or indirectly through
* interrupt handling logic.
*
****************************************************************************/
static int vnet_uiptxpoll(struct uip_driver_s *dev)
{
FAR struct vnet_driver_s *vnet = (FAR struct vnet_driver_s *)dev->d_private;
/* If the polling resulted in data that should be sent out on the network,
* the field d_len is set to a value > 0.
*/
if (vnet->sk_dev.d_len > 0)
{
uip_arp_out(&vnet->sk_dev);
vnet_transmit(vnet);
/* Check if there is room in the device to hold another packet. If not,
* return a non-zero value to terminate the poll.
*/
if (vnet_is_txbuff_full(vnet->vnet))
return 1;
}
/* If zero is returned, the polling will continue until all connections have
* been examined.
*/
return 0;
}
/****************************************************************************
* Function: rtos_vnet_recv
*
* Description:
* An interrupt was received indicating the availability of a new RX packet
*
* Parameters:
* vnet - Reference to the driver state structure
*
* Returned Value:
* None
*
* Assumptions:
* Global interrupts are disabled by interrupt handling logic.
*
****************************************************************************/
void rtos_vnet_recv(struct rgmp_vnet *vnet_dummy, char *data, int len)
{
// now only support 1 vnet
struct vnet_driver_s *vnet = &g_vnet[0];
do {
/* Check for errors and update statistics */
/* Check if the packet is a valid size for the uIP buffer configuration */
if (len > CONFIG_NET_BUFSIZE || len < 14) {
#ifdef CONFIG_DEBUG
cprintf("VNET: receive invalid packet of size %d\n", len);
#endif
return;
}
// Copy the data data from the hardware to vnet->sk_dev.d_buf. Set
// amount of data in vnet->sk_dev.d_len
memcpy(vnet->sk_dev.d_buf, data, len);
vnet->sk_dev.d_len = len;
/* We only accept IP packets of the configured type and ARP packets */
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(UIP_ETHTYPE_IP6))
#else
if (BUF->type == HTONS(UIP_ETHTYPE_IP))
#endif
{
uip_arp_ipin(&vnet->sk_dev);
uip_input(&vnet->sk_dev);
// If the above function invocation resulted in data that should be
// sent out on the network, the field d_len will set to a value > 0.
if (vnet->sk_dev.d_len > 0) {
uip_arp_out(&vnet->sk_dev);
vnet_transmit(vnet);
}
}
else if (BUF->type == htons(UIP_ETHTYPE_ARP)) {
uip_arp_arpin(&vnet->sk_dev);
// If the above function invocation resulted in data that should be
// sent out on the network, the field d_len will set to a value > 0.
if (vnet->sk_dev.d_len > 0) {
vnet_transmit(vnet);
}
}
}
while (0); /* While there are more packets to be processed */
}
/****************************************************************************
* Function: vnet_txdone
*
* Description:
* An interrupt was received indicating that the last TX packet(s) is done
*
* Parameters:
* vnet - Reference to the driver state structure
*
* Returned Value:
* None
*
* Assumptions:
* Global interrupts are disabled by the watchdog logic.
*
****************************************************************************/
static void vnet_txdone(FAR struct vnet_driver_s *vnet)
{
/* Check for errors and update statistics */
/* If no further xmits are pending, then cancel the TX timeout and
* disable further Tx interrupts.
*/
//wd_cancel(vnet->sk_txtimeout);
/* Then poll uIP for new XMIT data */
(void)uip_poll(&vnet->sk_dev, vnet_uiptxpoll);
}
/****************************************************************************
* Function: vnet_txtimeout
*
* Description:
* Our TX watchdog timed out. Called from the timer interrupt handler.
* The last TX never completed. Reset the hardware and start again.
*
* Parameters:
* argc - The number of available arguments
* arg - The first argument
*
* Returned Value:
* None
*
* Assumptions:
* Global interrupts are disabled by the watchdog logic.
*
****************************************************************************/
static void vnet_txtimeout(int argc, uint32_t arg, ...)
{
FAR struct vnet_driver_s *vnet = (FAR struct vnet_driver_s *)arg;
/* Increment statistics and dump debug info */
/* Then reset the hardware */
/* Then poll uIP for new XMIT data */
(void)uip_poll(&vnet->sk_dev, vnet_uiptxpoll);
}
/****************************************************************************
* Function: vnet_polltimer
*
* Description:
* Periodic timer handler. Called from the timer interrupt handler.
*
* Parameters:
* argc - The number of available arguments
* arg - The first argument
*
* Returned Value:
* None
*
* Assumptions:
* Global interrupts are disabled by the watchdog logic.
*
****************************************************************************/
static void vnet_polltimer(int argc, uint32_t arg, ...)
{
FAR struct vnet_driver_s *vnet = (FAR struct vnet_driver_s *)arg;
/* Check if there is room in the send another TX packet. We cannot perform
* the TX poll if he are unable to accept another packet for transmission.
*/
if (vnet_is_txbuff_full(vnet->vnet)) {
#ifdef CONFIG_DEBUG
cprintf("VNET: TX buffer is full\n");
#endif
return;
}
/* If so, update TCP timing states and poll uIP for new XMIT data. Hmmm..
* might be bug here. Does this mean if there is a transmit in progress,
* we will missing TCP time state updates?
*/
(void)uip_timer(&vnet->sk_dev, vnet_uiptxpoll, VNET_POLLHSEC);
/* Setup the watchdog poll timer again */
(void)wd_start(vnet->sk_txpoll, VNET_WDDELAY, vnet_polltimer, 1, arg);
}
/****************************************************************************
* Function: vnet_ifup
*
* Description:
* NuttX Callback: Bring up the Ethernet interface when an IP address is
* provided
*
* Parameters:
* dev - Reference to the NuttX driver state structure
*
* Returned Value:
* None
*
* Assumptions:
*
****************************************************************************/
static int vnet_ifup(struct uip_driver_s *dev)
{
FAR struct vnet_driver_s *vnet = (FAR struct vnet_driver_s *)dev->d_private;
ndbg("Bringing up: %d.%d.%d.%d\n",
dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
(dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 );
/* Initialize PHYs, the Ethernet interface, and setup up Ethernet interrupts */
/* Set and activate a timer process */
(void)wd_start(vnet->sk_txpoll, VNET_WDDELAY, vnet_polltimer, 1, (uint32_t)vnet);
vnet->sk_bifup = true;
return OK;
}
/****************************************************************************
* Function: vnet_ifdown
*
* Description:
* NuttX Callback: Stop the interface.
*
* Parameters:
* dev - Reference to the NuttX driver state structure
*
* Returned Value:
* None
*
* Assumptions:
*
****************************************************************************/
static int vnet_ifdown(struct uip_driver_s *dev)
{
FAR struct vnet_driver_s *vnet = (FAR struct vnet_driver_s *)dev->d_private;
irqstate_t flags;
/* Disable the Ethernet interrupt */
flags = irqsave();
/* Cancel the TX poll timer and TX timeout timers */
wd_cancel(vnet->sk_txpoll);
//wd_cancel(vnet->sk_txtimeout);
/* Put the the EMAC is its reset, non-operational state. This should be
* a known configuration that will guarantee the vnet_ifup() always
* successfully brings the interface back up.
*/
/* Mark the device "down" */
vnet->sk_bifup = false;
irqrestore(flags);
return OK;
}
/****************************************************************************
* Function: vnet_txavail
*
* Description:
* Driver callback invoked when new TX data is available. This is a
* stimulus perform an out-of-cycle poll and, thereby, reduce the TX
* latency.
*
* Parameters:
* dev - Reference to the NuttX driver state structure
*
* Returned Value:
* None
*
* Assumptions:
* Called in normal user mode
*
****************************************************************************/
static int vnet_txavail(struct uip_driver_s *dev)
{
FAR struct vnet_driver_s *vnet = (FAR struct vnet_driver_s *)dev->d_private;
irqstate_t flags;
/* Disable interrupts because this function may be called from interrupt
* level processing.
*/
flags = irqsave();
/* Ignore the notification if the interface is not yet up */
if (vnet->sk_bifup)
{
/* Check if there is room in the hardware to hold another outgoing packet. */
if (vnet_is_txbuff_full(vnet->vnet)) {
#ifdef CONFIG_DEBUG
cprintf("VNET: TX buffer is full\n");
#endif
goto out;
}
/* If so, then poll uIP for new XMIT data */
(void)uip_poll(&vnet->sk_dev, vnet_uiptxpoll);
}
out:
irqrestore(flags);
return OK;
}
/****************************************************************************
* Function: vnet_addmac
*
* Description:
* NuttX Callback: Add the specified MAC address to the hardware multicast
* address filtering
*
* Parameters:
* dev - Reference to the NuttX driver state structure
* mac - The MAC address to be added
*
* Returned Value:
* None
*
* Assumptions:
*
****************************************************************************/
#ifdef CONFIG_NET_IGMP
static int vnet_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac)
{
FAR struct vnet_driver_s *vnet = (FAR struct vnet_driver_s *)dev->d_private;
/* Add the MAC address to the hardware multicast routing table */
return OK;
}
#endif
/****************************************************************************
* Function: vnet_rmmac
*
* Description:
* NuttX Callback: Remove the specified MAC address from the hardware multicast
* address filtering
*
* Parameters:
* dev - Reference to the NuttX driver state structure
* mac - The MAC address to be removed
*
* Returned Value:
* None
*
* Assumptions:
*
****************************************************************************/
#ifdef CONFIG_NET_IGMP
static int vnet_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac)
{
FAR struct vnet_driver_s *vnet = (FAR struct vnet_driver_s *)dev->d_private;
/* Add the MAC address to the hardware multicast routing table */
return OK;
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: vnet_initialize
*
* Description:
* Initialize the Ethernet controller and driver
*
* Parameters:
* intf - In the case where there are multiple EMACs, this value
* identifies which EMAC is to be initialized.
*
* Returned Value:
* OK on success; Negated errno on failure.
*
* Assumptions:
*
****************************************************************************/
void vnet_initialize(void)
{
struct vnet_driver_s *priv;
struct rgmp_vnet *vnet = vnet_list.next;
int i;
for (i=0; i<CONFIG_VNET_NINTERFACES; i++) {
if (vnet == NULL)
break;
priv = &g_vnet[i];
/* Initialize the driver structure */
memset(priv, 0, sizeof(struct vnet_driver_s));
priv->sk_dev.d_ifup = vnet_ifup; /* I/F down callback */
priv->sk_dev.d_ifdown = vnet_ifdown; /* I/F up (new IP address) callback */
priv->sk_dev.d_txavail = vnet_txavail; /* New TX data callback */
#ifdef CONFIG_NET_IGMP
priv->sk_dev.d_addmac = vnet_addmac; /* Add multicast MAC address */
priv->sk_dev.d_rmmac = vnet_rmmac; /* Remove multicast MAC address */
#endif
priv->sk_dev.d_private = (void*)g_vnet; /* Used to recover private state from dev */
/* Create a watchdog for timing polling for and timing of transmisstions */
priv->sk_txpoll = wd_create(); /* Create periodic poll timer */
//priv->sk_txtimeout = wd_create(); /* Create TX timeout timer */
priv->vnet = vnet;
/* Register the device with the OS */
(void)netdev_register(&priv->sk_dev);
vnet = vnet->next;
}
}
#endif /* CONFIG_NET && CONFIG_NET_VNET */