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Resync new repository with old repo r5166
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patacongo
@@ -0,0 +1,214 @@
|
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#
|
||||
# For a description of the syntax of this configuration file,
|
||||
# see misc/tools/kconfig-language.txt.
|
||||
#
|
||||
config LCD_MAXCONTRAST
|
||||
int "LCD maximum contrast"
|
||||
default 63 if NOKIA6100_S1D15G10
|
||||
default 127 if NOKIA6100_PCF8833
|
||||
default 255 if LCD_P14201
|
||||
default 63
|
||||
---help---
|
||||
must be 63 with the Epson controller and 127 with
|
||||
the Phillips controller.
|
||||
|
||||
config LCD_MAXPOWER
|
||||
int "LCD maximum power"
|
||||
default 1
|
||||
---help---
|
||||
Maximum value of backlight setting. The backlight
|
||||
control is managed outside of the 6100 driver so this value has no
|
||||
meaning to the driver. Board-specific logic may place restrictions on
|
||||
this value.
|
||||
|
||||
config LCD_P14201
|
||||
bool "Rit P1402 series display"
|
||||
default n
|
||||
---help---
|
||||
p14201.c. Driver for RiT P14201 series display with SD1329 IC
|
||||
controller. This OLED is used with older versions of the
|
||||
TI/Luminary LM3S8962 Evaluation Kit.
|
||||
if LCD_P14201
|
||||
config P14201_NINTERFACES
|
||||
int "Number of physical P14201 devices"
|
||||
default 1
|
||||
range 1,1
|
||||
---help---
|
||||
Specifies the number of physical P14201
|
||||
devices that will be supported.
|
||||
|
||||
config P14201_SPIMODE
|
||||
int "SPI mode"
|
||||
default 2
|
||||
range 0,3
|
||||
---help---
|
||||
Controls the SPI mode
|
||||
|
||||
config P14201_FREQUENCY
|
||||
int "SPI frequency"
|
||||
default 1000000
|
||||
---help---
|
||||
Define to use a different bus frequency,FIXME DEFAULT VALUE OK?
|
||||
|
||||
config P14201_FRAMEBUFFER
|
||||
bool "Enable P14201 GDDRAM cache"
|
||||
default y
|
||||
---help---
|
||||
If defined, accesses will be performed
|
||||
using an in-memory copy of the OLEDs GDDRAM. This cost of this
|
||||
buffer is 128 * 96 / 2 = 6Kb. If this is defined, then the driver
|
||||
will be fully functional. If not, then it will have the following
|
||||
limitations:
|
||||
|
||||
Reading graphics memory cannot be supported, and
|
||||
|
||||
All pixel writes must be aligned to byte boundaries.
|
||||
The latter limitation effectively reduces the 128x96 disply to 64x96.
|
||||
endif
|
||||
|
||||
config LCD_NOKIA6100
|
||||
bool "Nokia 6100 display support"
|
||||
default n
|
||||
---help---
|
||||
nokia6100.c. Supports the Nokia 6100 display with either the Philips
|
||||
PCF883 or the Epson S1D15G10 display controller. This LCD is used
|
||||
with the Olimex LPC1766-STK (but has not been fully integrated).
|
||||
if LCD_NOKIA6100
|
||||
config NOKIA6100_NINTERFACES
|
||||
int "Number of physical NOKIA6100 devices"
|
||||
default 1
|
||||
range 1,1
|
||||
---help---
|
||||
Specifies the number of physical Nokia
|
||||
6100 devices that will be supported.
|
||||
|
||||
choice NOKIA6100_CONTROLLER
|
||||
prompt "Controller Setup"
|
||||
default NOKIA6100_S1D15G10
|
||||
config NOKIA6100_S1D15G10
|
||||
bool "S1D15G10 controller"
|
||||
---help---
|
||||
Selects the Epson S1D15G10 display controller
|
||||
|
||||
config NOKIA6100_PCF8833
|
||||
bool "PCF8833 controller"
|
||||
---help---
|
||||
Selects the Phillips PCF8833 display controller
|
||||
endchoice
|
||||
|
||||
config NOKIA6100_SPIMODE
|
||||
int "SPI mode"
|
||||
default 0
|
||||
range 0,3
|
||||
---help---
|
||||
Controls the SPI mode
|
||||
|
||||
config NOKIA6100_FREQUENCY
|
||||
int "SPI frequency"
|
||||
default 1000000
|
||||
---help---
|
||||
Define to use a different bus frequency
|
||||
|
||||
config NOKIA6100_BLINIT
|
||||
bool "Back light initial"
|
||||
default n
|
||||
---help---
|
||||
Initial backlight setting
|
||||
The following may need to be tuned for your hardware:
|
||||
|
||||
config NOKIA6100_BPP
|
||||
int "Display bits per pixel"
|
||||
default 8
|
||||
---help---
|
||||
Device supports 8, 12, and 16 bits per pixel.
|
||||
|
||||
config NOKIA6100_INVERT
|
||||
int "Display inversion"
|
||||
default 1
|
||||
range 0,1
|
||||
---help---
|
||||
Display inversion, 0 or 1, Default: 1
|
||||
|
||||
config NOKIA6100_MY
|
||||
int "Display row direction"
|
||||
default 0
|
||||
range 0,1
|
||||
---help---
|
||||
Display row direction, 0 or 1, Default: 0
|
||||
|
||||
config NOKIA6100_MX
|
||||
int "Display column direction"
|
||||
default 1
|
||||
range 0,1
|
||||
---help---
|
||||
Display column direction, 0 or 1, Default: 1
|
||||
|
||||
config NOKIA6100_V
|
||||
int "Display address direction"
|
||||
default 0
|
||||
range 0,1
|
||||
---help---
|
||||
Display address direction, 0 or 1, Default: 0
|
||||
|
||||
config NOKIA6100_ML
|
||||
int "Display scan direction"
|
||||
default 0
|
||||
range 0,1
|
||||
---help---
|
||||
Display scan direction, 0 or 1, Default: 0
|
||||
|
||||
config NOKIA6100_RGBORD
|
||||
int "Display RGB order"
|
||||
default 0
|
||||
range 0,1
|
||||
---help---
|
||||
Display RGB order, 0 or 1, Default: 0
|
||||
Required LCD driver settings:
|
||||
endif
|
||||
|
||||
config LCD_UG9664HSWAG01
|
||||
bool "9664HSWAG01 OLED Display Module"
|
||||
default n
|
||||
---help---
|
||||
ug-9664hswag01.c. OLED Display Module, UG-9664HSWAG01", Univision
|
||||
Technology Inc. Used with the LPC Xpresso and Embedded Artists
|
||||
base board.
|
||||
|
||||
choice
|
||||
prompt "LCD Orientation"
|
||||
default LCD_LANDSCAPE
|
||||
depends on LCD
|
||||
---help---
|
||||
Some LCD drivers may support displays in different orientations.
|
||||
If the LCD driver supports this capability, than these are configuration
|
||||
options to select that display orientation.
|
||||
|
||||
config LCD_LANDSCAPE
|
||||
bool "Landscape orientation"
|
||||
---help---
|
||||
Define for "landscape" orientation support. Landscape mode refers one
|
||||
of two orientations where the the display is wider than it is tall
|
||||
(LCD_RLANDSCAPE is the other). This is the default orientation.
|
||||
|
||||
config LCD_PORTRAIT
|
||||
bool "Portrait orientation"
|
||||
---help---
|
||||
Define for "portrait" orientation support. Portrait mode refers one
|
||||
of two orientations where the the display is taller than it is wide
|
||||
(LCD_RPORTAIT is the other).
|
||||
|
||||
config LCD_RPORTRAIT
|
||||
bool "Reverse portrait display"
|
||||
---help---
|
||||
Define for "reverse portrait" orientation support. Reverse portrait mode
|
||||
refers one of two orientations where the the display is taller than it is
|
||||
wide (LCD_PORTAIT is the other).
|
||||
|
||||
config LCD_RLANDSCAPE
|
||||
bool "Reverse landscape orientation"
|
||||
---help---
|
||||
Define for "reverse landscape" orientation support. Reverse landscape mode
|
||||
refers one of two orientations where the the display is wider than it is
|
||||
tall (LCD_LANDSCAPE is the other).
|
||||
|
||||
endchoice
|
||||
@@ -0,0 +1,68 @@
|
||||
############################################################################
|
||||
# drivers/lcd/Make.defs
|
||||
#
|
||||
# Copyright (C) 2010-2012 Gregory Nutt. All rights reserved.
|
||||
# Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in
|
||||
# the documentation and/or other materials provided with the
|
||||
# distribution.
|
||||
# 3. Neither the name NuttX nor the names of its contributors may be
|
||||
# used to endorse or promote products derived from this software
|
||||
# without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
############################################################################
|
||||
|
||||
# Don't build anything if there is no NX support for LCD drivers
|
||||
|
||||
ifeq ($(CONFIG_NX_LCDDRIVER),y)
|
||||
|
||||
# Include LCD drivers
|
||||
|
||||
ifeq ($(CONFIG_LCD_P14201),y)
|
||||
CSRCS += p14201.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LCD_NOKIA6100),y)
|
||||
CSRCS += nokia6100.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LCD_UG9664HSWAG01),y)
|
||||
CSRCS += ug-9664hswag01.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LCD_SSD1289),y)
|
||||
CSRCS += ssd1289.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LCD_MIO283QT2),y)
|
||||
CSRCS += mio283qt2.c
|
||||
endif
|
||||
|
||||
# Include LCD driver build support
|
||||
|
||||
DEPPATH += --dep-path lcd
|
||||
VPATH += :lcd
|
||||
CFLAGS += ${shell $(TOPDIR)/tools/incdir.sh $(INCDIROPT) "$(CC)" $(TOPDIR)/drivers/lcd}
|
||||
endif
|
||||
|
||||
@@ -0,0 +1,165 @@
|
||||
nuttx/drivers/lcd README
|
||||
========================
|
||||
|
||||
This is the README.txt file for the drivers/lcd/ directory.
|
||||
|
||||
Contents
|
||||
========
|
||||
|
||||
- LCD Header files
|
||||
include/nuttx/lcd/lcd.h
|
||||
struct lcd_dev_s
|
||||
- Binding LCD Drivers
|
||||
- Examples: /drivers/lcd/
|
||||
- Examples: configs/
|
||||
- graphics/
|
||||
|
||||
LCD Header files
|
||||
================
|
||||
|
||||
include/nuttx/lcd/lcd.h
|
||||
|
||||
Structures and APIs needed to work with LCD drivers are provided in
|
||||
this header file. This header file also depends on some of the same
|
||||
definitions used for the frame buffer driver as privided in
|
||||
include/nuttx/fb.h.
|
||||
|
||||
struct lcd_dev_s
|
||||
|
||||
Each LCD device driver must implement an instance of struct lcd_dev_s.
|
||||
That structure defines a call table with the following methods:
|
||||
|
||||
- Get information about the LCD video controller configuration and the
|
||||
configuration of each LCD color plane.
|
||||
|
||||
int (*getvideoinfo)(FAR struct lcd_dev_s *dev,
|
||||
FAR struct fb_videoinfo_s *vinfo);
|
||||
int (*getplaneinfo)(FAR struct lcd_dev_s *dev, unsigned int planeno,
|
||||
FAR struct lcd_planeinfo_s *pinfo);
|
||||
|
||||
- The following are provided only if the video hardware supports RGB
|
||||
color mapping:
|
||||
|
||||
int (*getcmap)(FAR struct lcd_dev_s *dev,
|
||||
FAR struct fb_cmap_s *cmap);
|
||||
int (*putcmap)(FAR struct lcd_dev_s *dev,
|
||||
FAR const struct fb_cmap_s *cmap);
|
||||
|
||||
- The following are provided only if the video hardware supports a
|
||||
hardware cursor:
|
||||
|
||||
int (*getcursor)(FAR struct lcd_dev_s *dev,
|
||||
FAR struct fb_cursorattrib_s *attrib);
|
||||
int (*setcursor)(FAR struct lcd_dev_s *dev,
|
||||
FAR struct fb_setcursor_s *settings);
|
||||
|
||||
- Get the LCD panel power status (0: full off - CONFIG_LCD_MAXPOWER:
|
||||
full on). On backlit LCDs, this setting may correspond to the
|
||||
backlight setting.
|
||||
|
||||
int (*getpower)(struct lcd_dev_s *dev);
|
||||
|
||||
- Enable/disable LCD panel power (0: full off - CONFIG_LCD_MAXPOWER:
|
||||
full on). On backlit LCDs, this setting may correspond to the
|
||||
backlight setting.
|
||||
|
||||
int (*setpower)(struct lcd_dev_s *dev, int power);
|
||||
|
||||
- Get the current contrast setting (0-CONFIG_LCD_MAXCONTRAST) */
|
||||
|
||||
int (*getcontrast)(struct lcd_dev_s *dev);
|
||||
|
||||
- Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST)
|
||||
|
||||
int (*setcontrast)(struct lcd_dev_s *dev, unsigned int contrast);
|
||||
|
||||
Binding LCD Drivers
|
||||
===================
|
||||
|
||||
LCD drivers are not normally directly accessed by user code, but are
|
||||
usually bound to another, higher level device driver. In general, the
|
||||
binding sequence is:
|
||||
|
||||
1. Get an instance of struct lcd_dev_s from the hardware-specific LCD
|
||||
device driver, and
|
||||
2. Provide that instance to the initialization method of the higher
|
||||
level device driver.
|
||||
|
||||
Examples: /drivers/lcd/
|
||||
=======================
|
||||
|
||||
Re-usable LCD drivers reside in the drivers/lcd directory:
|
||||
|
||||
mio283qt2.c. This is a driver for the MI0283QT-2 LCD from Multi-Inno
|
||||
Technology Co., Ltd. This LCD is based on the Himax HX8347-D LCD
|
||||
controller.
|
||||
|
||||
nokia6100.c. Supports the Nokia 6100 display with either the Philips
|
||||
PCF883 or the Epson S1D15G10 display controller. This LCD is used
|
||||
with the Olimex LPC1766-STK (but has not been fully integrated).
|
||||
|
||||
p14201.c. Driver for RiT P14201 series display with SD1329 IC
|
||||
controller. This OLED is used with older versions of the
|
||||
TI/Luminary LM3S8962 Evaluation Kit.
|
||||
|
||||
ssd12989.c. Generic LCD driver for LCDs based on the Solomon Systech
|
||||
SSD1289 LCD controller. Think of this as a template for an LCD driver
|
||||
that you will proably ahve to customize for any particular LCD
|
||||
hardware. (see also configs/hymini-stm32v/src/ssd1289.c below).
|
||||
|
||||
ug-9664hswag01.c. OLED Display Module, UG-9664HSWAG01", Univision
|
||||
Technology Inc. Used with the LPC Xpresso and Embedded Artists
|
||||
base board.
|
||||
|
||||
Examples: configs/
|
||||
==================
|
||||
|
||||
There are additional LCD drivers in the configs/<board>/src directory
|
||||
that support additional LCDs. LCD drivers in the configuration directory
|
||||
if they support some differ LCD interface (such as a parallel interface)
|
||||
that makes then less re-usable:
|
||||
|
||||
configs/compal_e99/src/ssd1783.c
|
||||
|
||||
SSD1783
|
||||
|
||||
configs/hymini-stm32v/src/ssd1289.c. See also drivers/lcd/ssd1298.c
|
||||
above.
|
||||
|
||||
SSD1289
|
||||
|
||||
configs/kwikstik-k40/src/up_lcd.c. Don't waste your time. This is
|
||||
just a stub.
|
||||
|
||||
configs/olimex-lpc1766stk/src/up_lcd.c. This examples is the
|
||||
bottom half for the SSD1289 driver at drivers/lcd/nokia6100.c.
|
||||
This was never completedly debugged ... there are probably issues
|
||||
with that nasty 9-bit SPI interfaces.
|
||||
|
||||
configs/sam3u-ek/src/up_lcd.c
|
||||
|
||||
The SAM3U-EK developement board features a TFT/Transmissive color
|
||||
LCD module with touch-screen, FTM280C12D, with integrated driver IC
|
||||
HX8346.
|
||||
|
||||
configs/skp16c26/src/up_lcd.c. Untested alphanumeric LCD driver.
|
||||
|
||||
configs/stm3210e-eval/src/up_lcd.c
|
||||
|
||||
This driver supports the following LCDs:
|
||||
|
||||
1. Ampire AM-240320LTNQW00H
|
||||
2. Orise Tech SPFD5408B
|
||||
3. RenesasSP R61580
|
||||
|
||||
configs/stm3220g-eval/src/up_lcd.c and configs/stm3240g-eval/src/up_lcd.c.
|
||||
AM-240320L8TNQW00H (LCD_ILI9320 or LCD_ILI9321) and
|
||||
AM-240320D5TOQW01H (LCD_ILI9325)
|
||||
|
||||
configs/stm32f4discovery/src/up_ssd1289.c. This examples is the
|
||||
bottom half for the SSD1289 driver at drivers/lcd/ssd1289.c
|
||||
|
||||
graphics/
|
||||
=========
|
||||
|
||||
See also the usage of the LCD driver in the graphics/ directory.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,152 @@
|
||||
/**************************************************************************************
|
||||
* drivers/lcd/pcf8833.h
|
||||
* Definitions for the Phillips PCF8833 LCD controller
|
||||
*
|
||||
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* References: "Data Sheet, PCF8833 STN RGB 132x132x3 driver," Phillips, 2003 Feb 14.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
**************************************************************************************/
|
||||
|
||||
#ifndef __DRIVERS_LCD_PCF8833_H
|
||||
#define __DRIVERS_LCD_PCF8833_H
|
||||
|
||||
/**************************************************************************************
|
||||
* Included Files
|
||||
**************************************************************************************/
|
||||
|
||||
/**************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
**************************************************************************************/
|
||||
/* Pixel format codes */
|
||||
|
||||
#define PCF8833_FMT_8BPS (2)
|
||||
#define PCF8833_FMT_12BPS (3)
|
||||
#define PCF8833_FMT_16BPS (5)
|
||||
|
||||
/* LCD Commands */
|
||||
|
||||
#define PCF8833_NOP 0x00 /* No operation; Data: none */
|
||||
#define PCF8833_SWRESET 0x01 /* Software reset ; Data: none */
|
||||
#define PCF8833_BSTROFF 0x02 /* Booster voltage off; Data: none */
|
||||
#define PCF8833_BSTRON 0x03 /* Booster voltage on; Data: none */
|
||||
#define PCF8833_RDDIDIF 0x04 /* Read display identification; Data: none */
|
||||
#define PCF8833_RDDST 0x09 /* Read display status; Data: none */
|
||||
#define PCF8833_SLEEPIN 0x10 /* Sleep_IN; Data: none */
|
||||
#define PCF8833_SLEEPOUT 0x11 /* Sleep_OUT; Data: none */
|
||||
#define PCF8833_PTLON 0x12 /* Partial mode on; Data: none */
|
||||
#define PCF8833_NORON 0x13 /* Normal Display mode on; Data: none */
|
||||
#define PCF8833_INVOFF 0x20 /* Display inversion off; Data: none */
|
||||
#define PCF8833_INVON 0x21 /* Display inversion on; Data: none */
|
||||
#define PCF8833_DALO 0x22 /* All pixel off; Data: none */
|
||||
#define PCF8833_DAL 0x23 /* All pixel on; Data: none */
|
||||
#define PCF8833_SETCON 0x25 /* Set contrast; Data: (1) contrast */
|
||||
#define PCF8833_DISPOFF 0x28 /* Display off; Data: none */
|
||||
#define PCF8833_DISPON 0x29 /* Display on; Data: none */
|
||||
#define PCF8833_CASET 0x2a /* Column address set; Data: (1) X start (2) X end */
|
||||
#define PCF8833_PASET 0x2b /* Page address set Data: (1) Y start (2) Y end */
|
||||
#define PCF8833_RAMWR 0x2c /* Memory write; Data: (1) write data */
|
||||
#define PCF8833_RGBSET 0x2d /* Colour set; Data: (1-8) red tones, (9-16) green tones, (17-20) blue tones */
|
||||
#define PCF8833_PTLAR 0x30 /* Partial area; Data: (1) start address (2) end address */
|
||||
#define PCF8833_VSCRDEF 0x33 /* Vertical scroll definition; Data: (1) top fixed, (2) scrol area, (3) bottom fixed */
|
||||
#define PCF8833_TEOFF 0x34 /* Tearing line off; Data: none */
|
||||
#define PCF8833_TEON 0x35 /* Tearing line on; Data: (1) don't care */
|
||||
#define PCF8833_MADCTL 0x36 /* Memory data access control; Data: (1) access control settings */
|
||||
#define PCF8833_SEP 0x37 /* Set Scroll Entry Point; Data: (1) scroll entry point */
|
||||
#define PCF8833_IDMOFF 0x38 /* Idle mode off; Data: none */
|
||||
#define PCF8833_IDMON 0x39 /* Idle mode on; Data: none */
|
||||
#define PCF8833_COLMOD 0x3a /* Interface pixel format; Data: (1) color interface format */
|
||||
#define PCF8833_SETVOP 0xb0 /* Set VOP; Data: (1) VOP5-8 (2) VOP0-4 */
|
||||
#define PCF8833_BRS 0xb4 /* Bottom Row Swap; Data: none */
|
||||
#define PCF8833_TRS 0xb6 /* Top Row Swap; Data: none */
|
||||
#define PCF8833_FINV 0xb9 /* Super Frame INVersion; Data: none */
|
||||
#define PCF8833_DOR 0xba /* Data ORder; Data: none */
|
||||
#define PCF8833_TCDFE 0xbd /* Enable/disable DF temp comp; Data: none */
|
||||
#define PCF8833_TCVOPE 0xbf /* Enable or disable VOP temp comp; Data: none */
|
||||
#define PCF8833_EC 0xc0 /* Internal or external oscillator; Data: none */
|
||||
#define PCF8833_SETMUL 0xc2 /* Set multiplication factor; Data: (1) Multiplication factor */
|
||||
#define PCF8833_TCVOPAB 0xc3 /* Set TCVOP slopes A and B; Data: (1) SLB and SLA */
|
||||
#define PCF8833_TCVOPCD 0xc4 /* Set TCVOP slopes C and D; Data: (1) SLD and SLC */
|
||||
#define PCF8833_TCDF 0xc5 /* Set divider frequency; Data: Divider factor in region (1) A (2) B (3) C (4) D */
|
||||
#define PCF8833_DF8COLOR 0xc6 /* Set divider frequency 8-colour mode; Data: (1) DF80-6 */
|
||||
#define PCF8833_SETBS 0xc7 /* Set bias system; Data: (1) Bias systems */
|
||||
#define PCF8833_RDTEMP 0xc8 /* Temperature read back; Data: none */
|
||||
#define PCF8833_NLI 0xc9 /* N-Line Inversion; Data: (1) NLI time slots invervsion */
|
||||
#define PCF8833_RDID1 0xda /* Read ID1; Data: none */
|
||||
#define PCF8833_RDID2 0xdb /* Read ID2; Data: none */
|
||||
#define PCF8833_RDID3 0xdc /* Read ID3; Data: none */
|
||||
#define PCF8833_SFD 0xef /* Select factory defaults; Data: none */
|
||||
#define PCF8833_ECM 0xf0 /* Enter Calibration mode; Data: (1) Calibration control settings */
|
||||
#define PCF8833_OTPSHTIN 0xf1 /* Shift data in OTP shift registers; Data: Any number of bytes */
|
||||
|
||||
/* Memory data access control (MADCTL) bit definitions */
|
||||
|
||||
#define MADCTL_RGB (1 << 3) /* Bit 3: BGR */
|
||||
#define MADCTL_LAO (1 << 4) /* Bit 4: Line address order bottom to top */
|
||||
#define MADCTL_V (1 << 5) /* Bit 5: Vertical RAM write; in Y direction */
|
||||
#define MADCTL_MX (1 << 6) /* Bit 6: Mirror X */
|
||||
#define MADCTL_MY (1 << 7) /* Bit 7: Mirror Y */
|
||||
|
||||
/* PCF8833 status register bit definitions */
|
||||
/* CMD format: RDDST command followed by four status bytes: */
|
||||
/* Byte 1: D31 d30 D29 D28 D27 D26 --- --- */
|
||||
|
||||
#define PCF8833_ST_RGB (1 << 2) /* Bit 2: D26 - RGB/BGR order */
|
||||
#define PCF8833_ST_LINEADDR (1 << 3) /* Bit 3: D27 - Line address order */
|
||||
#define PCF8833_ST_ADDRMODE (1 << 4) /* Bit 4: D28 - Vertical/horizontal addressing mode */
|
||||
#define PCF8833_ST_XADDR (1 << 5) /* Bit 5: D29 - X address order */
|
||||
#define PCF8833_ST_YADDR (1 << 6) /* Bit 6: D30 - Y address order */
|
||||
#define PCF8833_ST_BOOSTER (1 << 7) /* Bit 7: D31 - Booster voltage status */
|
||||
|
||||
/* Byte 2: --- D22 D21 D20 D19 D18 D17 D16 */
|
||||
|
||||
#define PCF8833_ST_NORMAL (1 << 0) /* Bit 0: D16 - Normal display mode */
|
||||
#define PCF8833_ST_SLEEPIN (1 << 1) /* Bit 1: D17 - Sleep in selected */
|
||||
#define PCF8833_ST_PARTIAL (1 << 2) /* Bit 2: D18 - Partial mode on */
|
||||
#define PCF8833_ST_IDLE (1 << 3) /* Bit 3: D19 - Idle mode selected */
|
||||
#define PCF8833_ST_PIXELFMT_SHIFT (4) /* Bits 4-6: D20-D22 - Interface pixel format */
|
||||
#define PCF8833_ST_PIXELFMT_MASK (7 << PCF8833_ST_PIXELFMT_SHIFT)
|
||||
# define PCF8833_ST_PIXELFMT_8BPS (PCF8833_FMT_8BPS << PCF8833_ST_PIXELFMT_SHIFT)
|
||||
# define PCF8833_ST_PIXELFMT_12BPS (PCF8833_FMT_12BPS << PCF8833_ST_PIXELFMT_SHIFT)
|
||||
# define PCF8833_ST_PIXELFMT_16BPS (PCF8833_FMT_16BPS << PCF8833_ST_PIXELFMT_SHIFT)
|
||||
|
||||
/* Byte 3: D15 -- D13 D12 D11 D10 D9 --- */
|
||||
|
||||
#define PCF8833_ST_TEARING (1 << 1) /* Bit 1: D9 - Tearing effect on */
|
||||
#define PCF8833_ST_DISPLAYON (1 << 2) /* Bit 2: D10 - Display on */
|
||||
#define PCF8833_ST_PIXELSOFF (1 << 3) /* Bit 3: D11 - All pixels off */
|
||||
#define PCF8833_ST_PIXELSON (1 << 4) /* Bit 4: D12 - All pixels on */
|
||||
#define PCF8833_ST_INV (1 << 5) /* Bit 5: D13 - Display inversion */
|
||||
#define PCF8833_ST_VSCROLL (1 << 7) /* Bit 6: D15 - Vertical scroll mode */
|
||||
|
||||
/* Byte 4: All zero */
|
||||
|
||||
#endif /* __DRIVERS_LCD_PCF8833_H */
|
||||
@@ -0,0 +1,141 @@
|
||||
/**************************************************************************************
|
||||
* drivers/lcd/s1d15g10.h
|
||||
* Definitions for the Epson S1D15G0 LCD controller
|
||||
*
|
||||
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* References: S1D15G0D08B000, Seiko Epson Corportation, 2002.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
**************************************************************************************/
|
||||
|
||||
#ifndef __DRIVERS_LCD_S1D15G10_H
|
||||
#define __DRIVERS_LCD_S1D15G10_H
|
||||
|
||||
/**************************************************************************************
|
||||
* Included Files
|
||||
**************************************************************************************/
|
||||
|
||||
/**************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
**************************************************************************************/
|
||||
|
||||
/* Epson S1D15G10 Command Set */
|
||||
|
||||
#define S1D15G10_DISON 0xaf /* Display on; Data: none */
|
||||
#define S1D15G10_DISOFF 0xae /* Display off; Data: none */
|
||||
#define S1D15G10_DISNOR 0xa6 /* Normal display; Data: none */
|
||||
#define S1D15G10_DISINV 0xa7 /* Inverse display; Data: none */
|
||||
#define S1D15G10_COMSCN 0xbb /* Common scan direction; Data: (1) common scan direction */
|
||||
#define S1D15G10_DISCTL 0xca /* Display control; Data: Data: (1) CL div, F1/2 pat, (2) duty, (3) FR inverse (4) dispersion */
|
||||
#define S1D15G10_SLPIN 0x95 /* Sleep in; Data: none */
|
||||
#define S1D15G10_SLPOUT 0x94 /* Sleep out; Data: none */
|
||||
#define S1D15G10_PASET 0x75 /* Page address set; Data: (1) start page, (2) end page */
|
||||
#define S1D15G10_CASET 0x15 /* Column address set; Data: (1) start addr, (2) end addr */
|
||||
#define S1D15G10_DATCTL 0xbc /* Data scan direction, etc.; Data: (1) inverse, scan dir (2) RGB, (3) gray-scale */
|
||||
#define S1D15G10_RGBSET8 0xce /* 256-color position set; Data: (1-8) red tones, (9-16) green tones, (17-20) blue tones */
|
||||
#define S1D15G10_RAMWR 0x5c /* Writing to memory; Data: (1) write data */
|
||||
#define S1D15G10_RAMRD 0x5d /* Reading from memory; Data: (1) read data */
|
||||
#define S1D15G10_PTLIN 0xa8 /* Partial display in; Data: (1) start addr, (2) end addr */
|
||||
#define S1D15G10_PTLOUT 0xa9 /* Partial display out; Data: none */
|
||||
#define S1D15G10_RMWIN 0xe0 /* Read and modify write; Data: none */
|
||||
#define S1D15G10_RMWOUT 0xee /* End; Data: none */
|
||||
#define S1D15G10_ASCSET 0xaa /* Area scroll set; Data: (1) top addr, (2) bottom addr, (3) Num blocks, (4) scroll mode */
|
||||
#define S1D15G10_SCSTART 0xab /* Scroll start set; Data: (1) start block addr */
|
||||
#define S1D15G10_OSCON 0xd1 /* Internal oscillation on; Data: none */
|
||||
#define S1D15G10_OSCOFF 0xd2 /* Internal oscillation off; Data: none */
|
||||
#define S1D15G10_PWRCTR 0x20 /* Power control; Data: (1) LCD drive power */
|
||||
#define S1D15G10_VOLCTR 0x81 /* Electronic volume control; Data: (1) volume value, (2) resistance ratio */
|
||||
#define S1D15G10_VOLUP 0xd6 /* Increment electronic control by 1; Data: none */
|
||||
#define S1D15G10_VOLDOWN 0xd7 /* Decrement electronic control by 1; Data: none */
|
||||
#define S1D15G10_TMPGRD 0x82 /* Temperature gradient set; Data: (1-14) temperature gradient */
|
||||
#define S1D15G10_EPCTIN 0xcd /* Control EEPROM; Data: (1) read/write */
|
||||
#define S1D15G10_EPCOUT 0xcc /* Cancel EEPROM control; Data: none */
|
||||
#define S1D15G10_EPMWR 0xfc /* Write into EEPROM; Data: none */
|
||||
#define S1D15G10_EPMRD 0xfd /* Read from EEPROM; Data: none */
|
||||
#define S1D15G10_EPSRRD1 0x7c /* Read register 1; Data: none */
|
||||
#define S1D15G10_EPSRRD2 0x7d /* Read regiser 2; Data: none */
|
||||
#define S1D15G10_NOP 0x25 /* NOP intruction (0x45?); Data: none */
|
||||
#define S1D15G10_STREAD 0x20 /* Status read; Data: none */
|
||||
|
||||
/* Display control (DISCTL) bit definitions */
|
||||
|
||||
#define DISCTL_PERIOD_SHIFT (0) /* P1: Bits 0-1, F1 and F2 drive-pattern switching period */
|
||||
#define DISCTL_PERIOD_MASK (3 << DISCTL_PERIOD_SHIFT)
|
||||
# define DISCTL_PERIOD_8 (0 << DISCTL_PERIOD_SHIFT)
|
||||
# define DISCTL_PERIOD_4 (1 << DISCTL_PERIOD_SHIFT)
|
||||
# define DISCTL_PERIOD_16 (2 << DISCTL_PERIOD_SHIFT)
|
||||
# define DISCTL_PERIOD_FLD (3 << DISCTL_PERIOD_SHIFT)
|
||||
#define DISCTL_CLDIV_SHIFT (2) /* P1: Bits 2-4, Clock divider */
|
||||
#define DISCTL_CLDIV_MASK (7 << DISCTL_CLDIV_SHIFT)
|
||||
# define DISCTL_CLDIV_2 (0 << DISCTL_CLDIV_SHIFT)
|
||||
# define DISCTL_CLDIV_4 (1 << DISCTL_CLDIV_SHIFT)
|
||||
# define DISCTL_CLDIV_8 (2 << DISCTL_CLDIV_SHIFT)
|
||||
# define DISCTL_CLDIV_NONE (3 << DISCTL_CLDIV_SHIFT)
|
||||
|
||||
/* Power control (PWRCTR) bit definitions */
|
||||
|
||||
#define PWCTR_REFVOLTAGE (1 << 0) /* P1: Bit 0, Turn on reference voltage generation circuit. */
|
||||
#define PWCTR_REGULATOR (1 << 1) /* P1: Bit 1, Turn on voltage regulator and circuit voltage follower. */
|
||||
#define PWCTR_BOOSTER2 (1 << 2) /* P1: Bit 2, Turn on secondary booster/step-down circuit. */
|
||||
#define PWCTR_BOOSTER1 (1 << 3) /* P1: Bit 3, Turn on primary booster circuit. */
|
||||
#define PWCTR_EXTR (1 << 4) /* P1: Bit 4, Use external resistance to adjust voltage. */
|
||||
|
||||
/* Data control (DATCTL) bit definitions */
|
||||
|
||||
#define DATCTL_PGADDR_INV (1 << 0) /* P1: Bit 0, Inverse display of the page address. */
|
||||
#define DATCTL_COLADDR_REV (1 << 1) /* P1: Bit 1, Reverse turn of column address. */
|
||||
#define DATCTL_ADDR_PGDIR (1 << 2) /* P1: Bit 2, Address-scan direction in page (vs column) direction. */
|
||||
|
||||
#define DATCTL_BGR (1 << 0) /* P2: Bit0, RGB->BGR */
|
||||
|
||||
#define DATCTL_8GRAY (1) /* P3: Bits 0-2 = 001, 8 gray-scale */
|
||||
#define DATCTL_16GRAY_A (2) /* P3: Bits 0-2 = 010, 16 gray-scale display type A */
|
||||
#define DATCTL_16GRAY_B (4) /* P3: Bits 0-2 = 100, 16 gray-scale display type B */
|
||||
|
||||
/* Status register bit definions (after reset or NOP) */
|
||||
|
||||
#define S1D15G10_SR_PARTIAL (1 << 0) /* Bit 0: Partial display */
|
||||
#define S1D15G10_SR_NORMAL (1 << 1) /* Bit 1: Normal (vs. inverse) display */
|
||||
#define S1D15G10_SR_EEPROM (1 << 2) /* Bit 2: EEPROM access */
|
||||
#define S1D15G10_SR_DISPON (1 << 3) /* Bit 3: Display on */
|
||||
#define S1D15G10_SR_COLSCAN (1 << 4) /* Bit 4: Column (vs. page) scan direction */
|
||||
#define S1D15G10_SR_RMW (1 << 5) /* Bit 5: Read modify write */
|
||||
#define S1D15G10_SR_SCROLL (3 << 6) /* Bits 6-7: Area scroll mode */
|
||||
|
||||
/* Status register bit definions (after EPSRRD1) */
|
||||
|
||||
#define S1D15G10_SR_VOLUME 0x3f /* Bits 0-5: Electronic volume control values */
|
||||
|
||||
/* Status register bit definions (after EPSRRD2) */
|
||||
|
||||
#define S1D15G10_SR_RRATIO 0x07 /* Bits 0-2: Built-in resistance ratio */
|
||||
|
||||
#endif /* __DRIVERS_LCD_S1D15G10_H */
|
||||
@@ -0,0 +1,527 @@
|
||||
/****************************************************************************
|
||||
* drivers/lcd/sd1329.h
|
||||
*
|
||||
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __DRIVERS_LCD_SD1329_H
|
||||
#define __DRIVERS_LCD_SD1329_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-Processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* SD1329 Commands **********************************************************/
|
||||
/* Set column Address.
|
||||
*
|
||||
* This triple byte command specifies column start address and end address of
|
||||
* the display data RAM. This command also sets the column address pointer to
|
||||
* column start address. This pointer is used to define the current read/write
|
||||
* column address in graphic display data RAM. If horizontal address increment
|
||||
* mode is enabled by command 0xa0, after finishing read/write one column data,
|
||||
* it is incremented automatically to the next column address. Whenever the
|
||||
* column address pointer finishes accessing the end column address, it is
|
||||
* reset back to start column address and the row address is incremented to the
|
||||
* next row.
|
||||
*
|
||||
* Byte 1: 0x15
|
||||
* Byte 2: A[5:0]: Start Address, range: 0x00-0x3f
|
||||
* Byte 3: B[5:0]: End Address, range: 0x00-0x3f
|
||||
*/
|
||||
|
||||
#define SSD1329_SET_COLADDR 0x15
|
||||
|
||||
/* Set Row Address.
|
||||
*
|
||||
* This triple byte command specifies row start address and end address of the
|
||||
* display data RAM. This command also sets the row address pointer to row
|
||||
* start address. This pointer is used to define the current read/write row
|
||||
* address in graphic display data RAM. If vertical address increment mode is
|
||||
* enabled by command 0xa0, after finishing read/write one row data, it is
|
||||
* incremented automatically to the next row address. Whenever the row address
|
||||
* pointer finishes accessing the end row address, it is reset back to start
|
||||
* row address.
|
||||
*
|
||||
* Byte 1: 0x75
|
||||
* Byte 2: A[6:0]: Start Address, range: 0x00-0x7f
|
||||
* Byte 3: B[6:0]: End Address, range: 0x00-0x7f
|
||||
*/
|
||||
|
||||
#define SSD1329_SET_ROWADDR 0x75
|
||||
|
||||
/* Set Contract Current
|
||||
*
|
||||
* This double byte command is to set Contrast Setting of the display. The
|
||||
* chip has 256 contrast steps from 0x00 to 0xff. The segment output current
|
||||
* increases linearly with the increase of contrast step.
|
||||
*
|
||||
* Byte 1: 0x81
|
||||
* Byte 2: A[7:0]: Contrast Value, range: 0-255
|
||||
*/
|
||||
|
||||
#define SSD1329_SET_CONTRAST 0x81
|
||||
|
||||
/* Set Second Pre-Charge Speed
|
||||
*
|
||||
* This command is used to set the speed of second pre-charge in phase 3.
|
||||
* This speed can be doubled to achieve faster pre-charging through setting
|
||||
* 0x82 A[0].
|
||||
*
|
||||
* Byte 1: 0x82
|
||||
* Byte 2: A[7:1]: Second Pre-charge Speed
|
||||
* A[0] = 1, Enable doubling the Second Pre-charge speed
|
||||
*/
|
||||
|
||||
#define SSD1329_PRECHRG2_SPEED 0x82
|
||||
# define SSD1329_PRECHRG2_DBL 0x01
|
||||
|
||||
/* Set Master Icon Control
|
||||
*
|
||||
* This double command is used to set the ON / OFF conditions of internal
|
||||
* charge pump, icon circuits and overall icon status.
|
||||
*
|
||||
* Byte 1: 0x90
|
||||
* Byte 2: Icon control (OR of bits 0-1,4-5)
|
||||
*/
|
||||
|
||||
#define SSD1329_ICON_CONTROL 0x90
|
||||
# define SSD1329_ICON_NORMAL 0x00 /* A[1:0]1=00: Icon RESET to normal display */
|
||||
# define SSD1329_ICON_ALLON 0x01 /* A[1:0]1=01: Icon All ON */
|
||||
# define SSD1329_ICON_ALLOFF 0x02 /* A[1:0]=10: Icon All OFF */
|
||||
# define SSD1329_ICON_DISABLE 0x00 /* A[4]=0: Disable Icon display */
|
||||
# define SSD1329_ICON_ENABLE 0x10 /* A[4]=1: Enable Icon display */
|
||||
# define SSD1329_VICON_DISABLE 0x00 /* A[5]=0: Disable VICON charge pump circuit */
|
||||
# define SSD1329_VICON_ENABLE 0x20 /* A[5]=1: Enable VICON charge pump circuit */
|
||||
|
||||
/* Set Icon Current Range
|
||||
*
|
||||
* This double byte command is used to set one fix current range for all icons
|
||||
* between the range of 0uA and 127.5uA. The uniformity improves as the icon
|
||||
* current range increases.
|
||||
*
|
||||
* Byte 1: 0x91
|
||||
* Byte 2: A[7:0]: Max icon current:
|
||||
* 00 = 0.0 uA
|
||||
* 01 = 0.5 uA
|
||||
* ...
|
||||
* ff = 127.5 uA
|
||||
*/
|
||||
|
||||
#define SSD1329_ICON_CURRRNG 0x91
|
||||
|
||||
/* Set Individual Icon Current
|
||||
*
|
||||
* This multiple byte command is used to fine tune the current for each of the
|
||||
* 64 icons. Command 0x92 followed by 64 single byte data. These 64 byte data
|
||||
* have to be entered in order to make this command function. Below is the
|
||||
* formula for calculating the icon current.
|
||||
*
|
||||
* Icon Current = Single byte value / 127 x Maximum icon current set with command 0x91
|
||||
*
|
||||
* Byte 1: 0x92
|
||||
* Byte 2-65: An[6:0]: icon current for ICSn, range: 0x00-0x7f
|
||||
* Icon Current of ICSn = An[6:0]/127) x max icon current
|
||||
*/
|
||||
|
||||
#define SSD1329_ICON_CURRENT 0x92
|
||||
|
||||
/* Set Individual Icon ON / OFF Register
|
||||
*
|
||||
* This double byte command is used to select one of the 64 icons and choose the
|
||||
* ON, OFF or blinking condition of the selected icon.
|
||||
*
|
||||
* Byte 1: 0x93
|
||||
* Byte 2: A[5:0]: Select one of the 64 icons from ICS0 ~ ICS63
|
||||
* A[7:6]: OFF/ON/BLINK
|
||||
*/
|
||||
|
||||
#define SSD1329_ICON_SELECT 0x93
|
||||
# define SSD1329_ICON_OFF 0x00
|
||||
# define SSD1329_ICON_ON 0x40
|
||||
# define SSD1329_ICON_BLINK 0xc0
|
||||
|
||||
/* Set Icon ON / OFF Registers
|
||||
*
|
||||
* This double byte command is used to set the ON / OFF status of all 64 icons.
|
||||
*
|
||||
* Byte 1: 0x94
|
||||
* Byte 2: A[7:6]: OFF/ON/BLINK (Same as 0x93)
|
||||
*/
|
||||
|
||||
#define SSD1329_ICON_ALL 0x94
|
||||
|
||||
/* Set Icon Blinking Cycle
|
||||
*
|
||||
* This double byte command is used to set icon oscillator frequency and
|
||||
* blinking cycle selected with above command 0x93.
|
||||
*
|
||||
* Byte 1: 0x95
|
||||
* Byte 2:
|
||||
* - A[2:0]:Icon Blinking cycle
|
||||
* - A[5:4]:Icon oscillation frequency
|
||||
*/
|
||||
|
||||
#define SSD1329_ICON_BLINKING 0x95
|
||||
# define SSD1329_ICON_BLINK_0p25S 0x00 /* 0.25 sec */
|
||||
# define SSD1329_ICON_BLINK_0p50S 0x01 /* 0.50 sec */
|
||||
# define SSD1329_ICON_BLINK_0p75S 0x02 /* 0.75 sec */
|
||||
# define SSD1329_ICON_BLINK_0p100S 0x03 /* 1.00 sec */
|
||||
# define SSD1329_ICON_BLINK_0p125S 0x04 /* 1.25 sec */
|
||||
# define SSD1329_ICON_BLINK_0p150S 0x05 /* 1.50 sec */
|
||||
# define SSD1329_ICON_BLINK_0p175S 0x06 /* 1.75 sec */
|
||||
# define SSD1329_ICON_BLINK_0p200S 0x07 /* 2.00 sec */
|
||||
# define SSD1329_ICON_BLINK_61KHZ 0x00 /* 61 KHz */
|
||||
# define SSD1329_ICON_BLINK_64KHZ 0x10 /* 64 KHz */
|
||||
# define SSD1329_ICON_BLINK_68KHZ 0x20 /* 68 KHz */
|
||||
# define SSD1329_ICON_BLINK_73KHZ 0x30 /* 73 KHz */
|
||||
|
||||
/* Set Icon Duty
|
||||
*
|
||||
* This double byte command is used to set the icon frame frequency and icon AC
|
||||
* drive duty ratio.
|
||||
*
|
||||
* Byte 1: 0x96
|
||||
* Byte 2:
|
||||
* - A[2:0]: AC Drive
|
||||
* - A[7:4]: con frame frequency
|
||||
*/
|
||||
|
||||
#define SSD1329_ICON_ACDRIVE 0x96
|
||||
# define SSD1329_ICON_DUTY_DC 0x00
|
||||
# define SSD1329_ICON_DUTY_63_64 0x01
|
||||
# define SSD1329_ICON_DUTY_62_64 0x02
|
||||
# define SSD1329_ICON_DUTY_61_64 0x03
|
||||
# define SSD1329_ICON_DUTY_60_64 0x04
|
||||
# define SSD1329_ICON_DUTY_59_64 0x05
|
||||
# define SSD1329_ICON_DUTY_58_64 0x06
|
||||
# define SSD1329_ICON_DUTY_57_64 0x07
|
||||
|
||||
/* Set Re-map
|
||||
*
|
||||
* This double command has multiple configurations and each bit setting is
|
||||
* described as follows:
|
||||
*
|
||||
* Column Address Remapping (A[0])
|
||||
* This bit is made for increase the flexibility layout of segment signals in
|
||||
* OLED module with segment arranged from left to right (when A[0] is set to 0)
|
||||
* or from right to left (when A[0] is set to 1).
|
||||
*
|
||||
* Nibble Remapping (A[1])
|
||||
* When A[1] is set to 1, the two nibbles of the data bus for RAM access are
|
||||
* re-mapped, such that (D7, D6, D5, D4, D3, D2, D1, D0) acts like (D3, D2, D1,
|
||||
* D0, D7, D6, D5, D4) If this feature works together with Column Address
|
||||
* Re-map, it would produce an effect of flipping the outputs from SEG0-127 to
|
||||
* SEG127-SEG0.
|
||||
*
|
||||
* Address increment mode (A[2])
|
||||
* When A[2] is set to 0, the driver is set as horizontal address incremen
|
||||
* mode. After the display RAM is read/written, the column address pointer is
|
||||
* increased automatically by 1. If the column address pointer reaches column
|
||||
* end address, the column address pointer is reset to column start address and
|
||||
* row address pointer is increased by 1.
|
||||
*
|
||||
* When A[2] is set to 1, the driver is set to vertical address increment mode.
|
||||
* After the display RAM is read/written, the row address pointer is increased
|
||||
* automatically by 1. If the row address pointer reaches the row end address,
|
||||
* the row address pointer is reset to row start address and column address
|
||||
* pointer is increased by 1.
|
||||
*
|
||||
* COM Remapping (A[4])
|
||||
* This bit defines the scanning direction of the common for flexible layout
|
||||
* of common signals in OLED module either from up to down (when A[4] is set to
|
||||
* 0) or from bottom to up (when A[4] is set to 1).
|
||||
*
|
||||
* Splitting of Odd / Even COM Signals (A[6])
|
||||
* This bit is made to match the COM layout connection on the panel. When A[6]
|
||||
* is set to 0, no splitting odd / even of the COM signal is performed. When
|
||||
* A[6] is set to 1, splitting odd / even of the COM signal is performed,
|
||||
* output pin assignment sequence is shown as below (for 128MUX ratio):
|
||||
*
|
||||
* Byte 1: 0xa0
|
||||
* Byte 2: A[7:0]
|
||||
*/
|
||||
|
||||
#define SSD1329_GDDRAM_REMAP 0xa0
|
||||
# define SSD1329_COLADDR_REMAP 0x01 /* A[0]: Enable column re-map */
|
||||
# define SSD1329_NIBBLE_REMAP 0x02 /* A[1]: Enable nibble re-map */
|
||||
# define SSD1329_VADDR_INCR 0x04 /* A[1]: Enable vertical address increment */
|
||||
# define SSD1329_COM_REMAP 0x10 /* A[4]: Enable COM re-map */
|
||||
# define SSD1329_COM_SPLIT 0x40 /* A[6]: Enable COM slip even/odd */
|
||||
|
||||
/* Set Display Start Line
|
||||
*
|
||||
* This double byte command is to set Display Start Line register for
|
||||
* determining the starting address of display RAM to be displayed by selecting
|
||||
* a value from 0 to 127.
|
||||
*
|
||||
* Byte 1: 0xa1
|
||||
* Byte 2: A[6:0]: Vertical scroll by setting the starting address of
|
||||
* display RAM from 0-127
|
||||
*/
|
||||
|
||||
#define SSD1329_VERT_START 0xa1
|
||||
|
||||
/* Set Display Offset
|
||||
*
|
||||
* This double byte command specifies the mapping of display start line (it is
|
||||
* assumed that COM0 is the display start line, display start line register
|
||||
* equals to 0) to one of COM0-COM127.
|
||||
*
|
||||
* Byte 1: 0xa2
|
||||
* Byte 2: A[6:0]: Set vertical offset by COM from 0-127
|
||||
*/
|
||||
|
||||
#define SSD1329_VERT_OFFSET 0xa2
|
||||
|
||||
/* Set Display Mode - Normal, all on, all off, inverse
|
||||
*
|
||||
* These are single byte commands and are used to set display status to Normal
|
||||
* Display, Entire Display ON, Entire Display OFF or Inverse Display.
|
||||
*
|
||||
* Normal Display (0xa4)
|
||||
* Reset the “Entire Display ON, Entire Display OFF or Inverse Display” effects
|
||||
* and turn the data to ON at the corresponding gray level.
|
||||
*
|
||||
* Set Entire Display ON (0xa5)
|
||||
* Force the entire display to be at gray scale level GS15, regardless of the
|
||||
* contents of the display data RAM.
|
||||
*
|
||||
* Set Entire Display OFF (0xa6)
|
||||
* Force the entire display to be at gray scale level GS0, regardless of the
|
||||
* contents of the display data RAM.
|
||||
*
|
||||
* Inverse Display (0xa7)
|
||||
* The gray scale level of display data are swapped such that “GS0” <-> “GS15”,
|
||||
* “GS1” <-> “GS14”, etc.
|
||||
*
|
||||
* Byte 1: Display mode command
|
||||
*/
|
||||
|
||||
#define SSD1329_DISP_NORMAL 0xa4
|
||||
#define SSD1329_DISP_OFF 0xa5
|
||||
#define SSD1329_DISP_ON 0xa6
|
||||
#define SSD1329_DISP_INVERT 0xa7
|
||||
|
||||
/* Set MUX Ratio
|
||||
*
|
||||
* This double byte command sets multiplex ratio (MUX ratio) from 16MUX to
|
||||
* 128MUX. In POR, multiplex ratio is 128MUX.
|
||||
*
|
||||
* Byte 1: 0xa8
|
||||
* Byte 2: A[6:0] 15-127 representing 16-128 MUX
|
||||
*/
|
||||
|
||||
#define SSD1329_MUX_RATIO 0xa8
|
||||
|
||||
/* Set Sleep mode ON / OFF
|
||||
*
|
||||
* These single byte commands are used to turn the matrix display on the OLED
|
||||
* panel display either ON or OFF. When the sleep mode is set to ON (0xae), the
|
||||
* display is OFF, the segment and common output are in high impedance state
|
||||
* and circuits will be turned OFF. When the sleep mode is set to OFF (0xaf),
|
||||
* the display is ON.
|
||||
*
|
||||
* Byte 1: sleep mode command
|
||||
*/
|
||||
|
||||
#define SSD1329_SLEEP_ON 0xae
|
||||
#define SSD1329_SLEEP_OFF 0xaf
|
||||
|
||||
/* Set Phase Length
|
||||
*
|
||||
* In the second byte of this double command, lower nibble and higher nibble is
|
||||
* defined separately. The lower nibble adjusts the phase length of Reset (phase
|
||||
* 1). The higher nibble is used to select the phase length of first pre-charge
|
||||
* phase (phase 2). The phase length is ranged from 1 to 16 DCLK's. RESET for
|
||||
* A[3:0] is set to 3 which means 4 DCLK’s selected for Reset phase. POR for
|
||||
* A[7:4] is set to 5 which means 6 DCLK’s is selected for first pre-charge
|
||||
* phase. Please refer to Table 9-1 for detail breakdown levels of each step.
|
||||
*
|
||||
* Byte 1: 0xb1
|
||||
* Byte 2: A[3:0]: Phase 1 period of 1~16 DCLK’s
|
||||
* A[7:4]: Phase 2 period of 1~16 DCLK’s
|
||||
*/
|
||||
|
||||
#define SSD1329_PHASE_LENGTH 0xb1
|
||||
|
||||
/* Set Frame Frequency
|
||||
*
|
||||
* This double byte command is used to set the number of DCLK’s per row between
|
||||
* the range of 0x14 and 0x7f. Then the Frame frequency of the matrix display
|
||||
* is equal to DCLK frequency / A[6:0].
|
||||
*
|
||||
* Byte 1: 0xb2
|
||||
* Byte 2: A[6:0]:Total number of DCLK’s per row. Ranging from
|
||||
* 0x14 to 0x4e DCLK’s. frame Frequency = DCLK freq /A[6:0].
|
||||
*/
|
||||
|
||||
#define SSD1329_FRAME_FREQ 0xb2
|
||||
|
||||
/* Set Front Clock Divider / Oscillator Frequency
|
||||
*
|
||||
* This double command is used to set the frequency of the internal display
|
||||
* clocks, DCLK's. It is defined by dividing the oscillator frequency by the
|
||||
* divide ratio (Value from 1 to 16). Frame frequency is determined by divide
|
||||
* ratio, number of display clocks per row, MUX ratio and oscillator frequency.
|
||||
* The lower nibble of the second byte is used to select the oscillator
|
||||
* frequency. Please refer to Table 9-1 for detail breakdown levels of each
|
||||
* step.
|
||||
*
|
||||
* Byte 1: 0xb3
|
||||
* Byte 2: A[3:0]: Define divide ratio (D) of display clock (DCLK)
|
||||
* Divide ratio=A[3:0]+1
|
||||
* A[7:4] : Set the Oscillator Frequency, FOSC. Range:0-15
|
||||
*/
|
||||
|
||||
#define SSD1329_DCLK_DIV 0xb3
|
||||
|
||||
/* Set Default Gray Scale Table
|
||||
*
|
||||
* This single byte command is used to set the gray scale table to initial
|
||||
* default setting.
|
||||
*
|
||||
* Byte 1: 0xb7
|
||||
*/
|
||||
|
||||
#define SSD1329_GSCALE_TABLE 0xb7
|
||||
|
||||
/* Look Up Table for Gray Scale Pulse width
|
||||
*
|
||||
* This command is used to set each individual gray scale level for the display.
|
||||
* Except gray scale level GS0 that has no pre-charge and current drive, each
|
||||
* gray scale level is programmed in the length of current drive stage pulse
|
||||
* width with unit of DCLK. The longer the length of the pulse width, the
|
||||
* brighter the OLED pixel when it’s turned ON.
|
||||
*
|
||||
* The setting of gray scale table entry can perform gamma correction on OLED
|
||||
* panel display. Normally, it is desired that the brightness response of the
|
||||
* panel is linearly proportional to the image data value in display data RAM.
|
||||
* However, the OLED panel is somehow responded in non-linear way. Appropriate
|
||||
* gray scale table setting like example below can compensate this effect.
|
||||
*
|
||||
* Byte 1: 0xb8
|
||||
* Bytes 2-16: An[5:0], value for GSn level Pulse width
|
||||
*/
|
||||
|
||||
#define SSD1329_GSCALE_LOOKUP 0xb8
|
||||
|
||||
/* Set Second Pre-charge Period
|
||||
*
|
||||
* This double byte command is used to set the phase 3 second pre-charge period.
|
||||
* The period of phase 3 can be programmed by command 0xbb and it is ranged from
|
||||
* 0 to 15 DCLK's.
|
||||
*
|
||||
* Byte 1: 0xbb
|
||||
* Byte 2: 0-15 DCLKs
|
||||
*/
|
||||
|
||||
#define SSD1329_PRECHRG2_PERIOD 0xbb
|
||||
|
||||
/* Set First Precharge voltage, VP
|
||||
*
|
||||
* This double byte command is used to set phase 2 first pre-charge voltage
|
||||
* level. It can be programmed to set the first pre-charge voltage reference to
|
||||
* VCC or VCOMH.
|
||||
*
|
||||
* Byte 1: 0xbc
|
||||
* Byte 2: A[5] == 0, Pre-charge voltage is (0.30 + A[4:0]) * Vcc
|
||||
* A{5] == 1, 1.00 x VCC or connect to VCOMH if VCC > VCOMH
|
||||
*/
|
||||
|
||||
#define SSD1329_PRECHRG1_VOLT 0xbc
|
||||
|
||||
/* Set VCOMH
|
||||
*
|
||||
* This double byte command sets the high voltage level of common pins, VCOMH.
|
||||
* The level of VCOMH is programmed with reference to VCC.
|
||||
*
|
||||
* Byte 1: 0xbe
|
||||
* Byte 2: (0.51 + A[5:0]) * Vcc
|
||||
*/
|
||||
|
||||
#define SSD1329_COM_HIGH 0xbe
|
||||
|
||||
/* NOOP
|
||||
*
|
||||
* This is a no operation command.
|
||||
*
|
||||
* Byte 1: 0xe3
|
||||
*/
|
||||
|
||||
#define SSD1329_NOOP 0xe3
|
||||
|
||||
/* Set Command Lock
|
||||
*
|
||||
* This command is used to lock the MCU from accepting any command.
|
||||
*
|
||||
* Byte 1: 0xfd
|
||||
* Byte 2: 0x12 | A[2]
|
||||
* A[2] == 1, Enable locking the MCU from entering command
|
||||
*/
|
||||
|
||||
#define SSD1329_CMD_LOCK 0xfd
|
||||
# define SSD1329_LOCK_ON 0x13
|
||||
# define SSD1329_LOCK_OFF 0x12
|
||||
|
||||
/* SD1329 Status ************************************************************/
|
||||
|
||||
#define SDD1329_STATUS_ON 0x00 /* D[6]=0: indicates the display is ON */
|
||||
#define SDD1329_STATUS_OFF 0x40 /* D[6]=1: indicates the display is OFF */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
#endif /* __DRIVERS_LCD_SD1329_H */
|
||||
@@ -0,0 +1,401 @@
|
||||
/**************************************************************************************
|
||||
* drivers/lcd/skeleton.c
|
||||
*
|
||||
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
**************************************************************************************/
|
||||
|
||||
/**************************************************************************************
|
||||
* Included Files
|
||||
**************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <string.h>
|
||||
#include <errno.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/spi.h>
|
||||
#include <nuttx/lcd/lcd.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
|
||||
/**************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
**************************************************************************************/
|
||||
|
||||
/* Configuration **********************************************************************/
|
||||
/* Verify that all configuration requirements have been met */
|
||||
|
||||
/* Debug ******************************************************************************/
|
||||
/* Define the following to enable register-level debug output */
|
||||
|
||||
#undef CONFIG_LCD_SKELDEBUG
|
||||
|
||||
/* Verbose debug must also be enabled */
|
||||
|
||||
#ifndef CONFIG_DEBUG
|
||||
# undef CONFIG_DEBUG_VERBOSE
|
||||
# undef CONFIG_DEBUG_GRAPHICS
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_DEBUG_VERBOSE
|
||||
# undef CONFIG_LCD_SKELDEBUG
|
||||
#endif
|
||||
|
||||
/* Color Properties *******************************************************************/
|
||||
|
||||
/* Display Resolution */
|
||||
|
||||
#define SKEL_XRES 320
|
||||
#define SKEL_YRES 240
|
||||
|
||||
/* Color depth and format */
|
||||
|
||||
#define SKEL_BPP 16
|
||||
#define SKEL_COLORFMT FB_FMT_RGB16_565
|
||||
|
||||
/* Debug ******************************************************************************/
|
||||
|
||||
#ifdef CONFIG_LCD_SKELDEBUG
|
||||
# define skeldbg(format, arg...) vdbg(format, ##arg)
|
||||
#else
|
||||
# define skeldbg(x...)
|
||||
#endif
|
||||
|
||||
/**************************************************************************************
|
||||
* Private Type Definition
|
||||
**************************************************************************************/
|
||||
|
||||
/* This structure describes the state of this driver */
|
||||
|
||||
struct skel_dev_s
|
||||
{
|
||||
/* Publically visible device structure */
|
||||
|
||||
struct lcd_dev_s dev;
|
||||
|
||||
/* Private LCD-specific information follows */
|
||||
};
|
||||
|
||||
/**************************************************************************************
|
||||
* Private Function Protototypes
|
||||
**************************************************************************************/
|
||||
|
||||
/* LCD Data Transfer Methods */
|
||||
|
||||
static int skel_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buffer,
|
||||
size_t npixels);
|
||||
static int skel_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer,
|
||||
size_t npixels);
|
||||
|
||||
/* LCD Configuration */
|
||||
|
||||
static int skel_getvideoinfo(FAR struct lcd_dev_s *dev,
|
||||
FAR struct fb_videoinfo_s *vinfo);
|
||||
static int skel_getplaneinfo(FAR struct lcd_dev_s *dev, unsigned int planeno,
|
||||
FAR struct lcd_planeinfo_s *pinfo);
|
||||
|
||||
/* LCD RGB Mapping */
|
||||
|
||||
#ifdef CONFIG_FB_CMAP
|
||||
# error "RGB color mapping not supported by this driver"
|
||||
#endif
|
||||
|
||||
/* Cursor Controls */
|
||||
|
||||
#ifdef CONFIG_FB_HWCURSOR
|
||||
# error "Cursor control not supported by this driver"
|
||||
#endif
|
||||
|
||||
/* LCD Specific Controls */
|
||||
|
||||
static int skel_getpower(struct lcd_dev_s *dev);
|
||||
static int skel_setpower(struct lcd_dev_s *dev, int power);
|
||||
static int skel_getcontrast(struct lcd_dev_s *dev);
|
||||
static int skel_setcontrast(struct lcd_dev_s *dev, unsigned int contrast);
|
||||
|
||||
/**************************************************************************************
|
||||
* Private Data
|
||||
**************************************************************************************/
|
||||
|
||||
/* This is working memory allocated by the LCD driver for each LCD device
|
||||
* and for each color plane. This memory will hold one raster line of data.
|
||||
* The size of the allocated run buffer must therefore be at least
|
||||
* (bpp * xres / 8). Actual alignment of the buffer must conform to the
|
||||
* bitwidth of the underlying pixel type.
|
||||
*
|
||||
* If there are multiple planes, they may share the same working buffer
|
||||
* because different planes will not be operate on concurrently. However,
|
||||
* if there are multiple LCD devices, they must each have unique run buffers.
|
||||
*/
|
||||
|
||||
static uint16_t g_runbuffer[SKEL_XRES];
|
||||
|
||||
/* This structure describes the overall LCD video controller */
|
||||
|
||||
static const struct fb_videoinfo_s g_videoinfo =
|
||||
{
|
||||
.fmt = SKEL_COLORFMT, /* Color format: RGB16-565: RRRR RGGG GGGB BBBB */
|
||||
.xres = SKEL_XRES, /* Horizontal resolution in pixel columns */
|
||||
.yres = SKEL_YRES, /* Vertical resolution in pixel rows */
|
||||
.nplanes = 1, /* Number of color planes supported */
|
||||
};
|
||||
|
||||
/* This is the standard, NuttX Plane information object */
|
||||
|
||||
static const struct lcd_planeinfo_s g_planeinfo =
|
||||
{
|
||||
.putrun = skel_putrun, /* Put a run into LCD memory */
|
||||
.getrun = skel_getrun, /* Get a run from LCD memory */
|
||||
.buffer = (uint8_t*)g_runbuffer, /* Run scratch buffer */
|
||||
.bpp = SKEL_BPP, /* Bits-per-pixel */
|
||||
};
|
||||
|
||||
/* This is the standard, NuttX LCD driver object */
|
||||
|
||||
static struct skel_dev_s g_lcddev =
|
||||
{
|
||||
.dev =
|
||||
{
|
||||
/* LCD Configuration */
|
||||
|
||||
.getvideoinfo = skel_getvideoinfo,
|
||||
.getplaneinfo = skel_getplaneinfo,
|
||||
|
||||
/* LCD RGB Mapping -- Not supported */
|
||||
/* Cursor Controls -- Not supported */
|
||||
|
||||
/* LCD Specific Controls */
|
||||
|
||||
.getpower = skel_getpower,
|
||||
.setpower = skel_setpower,
|
||||
.getcontrast = skel_getcontrast,
|
||||
.setcontrast = skel_setcontrast,
|
||||
},
|
||||
};
|
||||
|
||||
/**************************************************************************************
|
||||
* Private Functions
|
||||
**************************************************************************************/
|
||||
|
||||
/**************************************************************************************
|
||||
* Name: skel_putrun
|
||||
*
|
||||
* Description:
|
||||
* This method can be used to write a partial raster line to the LCD:
|
||||
*
|
||||
* row - Starting row to write to (range: 0 <= row < yres)
|
||||
* col - Starting column to write to (range: 0 <= col <= xres-npixels)
|
||||
* buffer - The buffer containing the run to be written to the LCD
|
||||
* npixels - The number of pixels to write to the LCD
|
||||
* (range: 0 < npixels <= xres-col)
|
||||
*
|
||||
**************************************************************************************/
|
||||
|
||||
static int skel_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buffer,
|
||||
size_t npixels)
|
||||
{
|
||||
/* Buffer must be provided and aligned to a 16-bit address boundary */
|
||||
|
||||
gvdbg("row: %d col: %d npixels: %d\n", row, col, npixels);
|
||||
DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0);
|
||||
|
||||
/* Set up to write the run. */
|
||||
|
||||
/* Write the run to GRAM. */
|
||||
#warning "Missing logic"
|
||||
return OK;
|
||||
}
|
||||
|
||||
/**************************************************************************************
|
||||
* Name: skel_getrun
|
||||
*
|
||||
* Description:
|
||||
* This method can be used to read a partial raster line from the LCD:
|
||||
*
|
||||
* row - Starting row to read from (range: 0 <= row < yres)
|
||||
* col - Starting column to read read (range: 0 <= col <= xres-npixels)
|
||||
* buffer - The buffer in which to return the run read from the LCD
|
||||
* npixels - The number of pixels to read from the LCD
|
||||
* (range: 0 < npixels <= xres-col)
|
||||
*
|
||||
**************************************************************************************/
|
||||
|
||||
static int skel_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer,
|
||||
size_t npixels)
|
||||
{
|
||||
/* Buffer must be provided and aligned to a 16-bit address boundary */
|
||||
|
||||
gvdbg("row: %d col: %d npixels: %d\n", row, col, npixels);
|
||||
DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0);
|
||||
|
||||
#warning "Missing logic"
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
/**************************************************************************************
|
||||
* Name: skel_getvideoinfo
|
||||
*
|
||||
* Description:
|
||||
* Get information about the LCD video controller configuration.
|
||||
*
|
||||
**************************************************************************************/
|
||||
|
||||
static int skel_getvideoinfo(FAR struct lcd_dev_s *dev,
|
||||
FAR struct fb_videoinfo_s *vinfo)
|
||||
{
|
||||
DEBUGASSERT(dev && vinfo);
|
||||
gvdbg("fmt: %d xres: %d yres: %d nplanes: %d\n",
|
||||
g_videoinfo.fmt, g_videoinfo.xres, g_videoinfo.yres, g_videoinfo.nplanes);
|
||||
memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s));
|
||||
return OK;
|
||||
}
|
||||
|
||||
/**************************************************************************************
|
||||
* Name: skel_getplaneinfo
|
||||
*
|
||||
* Description:
|
||||
* Get information about the configuration of each LCD color plane.
|
||||
*
|
||||
**************************************************************************************/
|
||||
|
||||
static int skel_getplaneinfo(FAR struct lcd_dev_s *dev, unsigned int planeno,
|
||||
FAR struct lcd_planeinfo_s *pinfo)
|
||||
{
|
||||
DEBUGASSERT(dev && pinfo && planeno == 0);
|
||||
gvdbg("planeno: %d bpp: %d\n", planeno, g_planeinfo.bpp);
|
||||
memcpy(pinfo, &g_planeinfo, sizeof(struct lcd_planeinfo_s));
|
||||
return OK;
|
||||
}
|
||||
|
||||
/**************************************************************************************
|
||||
* Name: skel_getpower
|
||||
*
|
||||
* Description:
|
||||
* Get the LCD panel power status (0: full off - CONFIG_LCD_MAXPOWER: full on). On
|
||||
* backlit LCDs, this setting may correspond to the backlight setting.
|
||||
*
|
||||
**************************************************************************************/
|
||||
|
||||
static int skel_getpower(struct lcd_dev_s *dev)
|
||||
{
|
||||
struct skel_dev_s *priv = (struct skel_dev_s *)dev;
|
||||
gvdbg("power: %d\n", 0);
|
||||
#warning "Missing logic"
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**************************************************************************************
|
||||
* Name: skel_setpower
|
||||
*
|
||||
* Description:
|
||||
* Enable/disable LCD panel power (0: full off - CONFIG_LCD_MAXPOWER: full on). On
|
||||
* backlit LCDs, this setting may correspond to the backlight setting.
|
||||
*
|
||||
**************************************************************************************/
|
||||
|
||||
static int skel_setpower(struct lcd_dev_s *dev, int power)
|
||||
{
|
||||
struct skel_dev_s *priv = (struct skel_dev_s *)dev;
|
||||
|
||||
gvdbg("power: %d\n", power);
|
||||
DEBUGASSERT(power <= CONFIG_LCD_MAXPOWER);
|
||||
|
||||
/* Set new power level */
|
||||
#warning "Missing logic"
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/**************************************************************************************
|
||||
* Name: skel_getcontrast
|
||||
*
|
||||
* Description:
|
||||
* Get the current contrast setting (0-CONFIG_LCD_MAXCONTRAST).
|
||||
*
|
||||
**************************************************************************************/
|
||||
|
||||
static int skel_getcontrast(struct lcd_dev_s *dev)
|
||||
{
|
||||
gvdbg("Not implemented\n");
|
||||
#warning "Missing logic"
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
/**************************************************************************************
|
||||
* Name: skel_setcontrast
|
||||
*
|
||||
* Description:
|
||||
* Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST).
|
||||
*
|
||||
**************************************************************************************/
|
||||
|
||||
static int skel_setcontrast(struct lcd_dev_s *dev, unsigned int contrast)
|
||||
{
|
||||
gvdbg("contrast: %d\n", contrast);
|
||||
#warning "Missing logic"
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
/**************************************************************************************
|
||||
* Public Functions
|
||||
**************************************************************************************/
|
||||
|
||||
/**************************************************************************************
|
||||
* Name: up_oledinitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the LCD video hardware. The initial state of the LCD is fully
|
||||
* initialized, display memory cleared, and the LCD ready to use, but with the power
|
||||
* setting at 0 (full off).
|
||||
*
|
||||
**************************************************************************************/
|
||||
|
||||
FAR struct lcd_dev_s *up_oledinitialize(FAR struct spi_dev_s *spi)
|
||||
{
|
||||
gvdbg("Initializing\n");
|
||||
|
||||
/* Configure GPIO pins */
|
||||
#warning "Missing logic"
|
||||
|
||||
/* Enable clocking */
|
||||
#warning "Missing logic"
|
||||
|
||||
/* Configure and enable LCD */
|
||||
#warning "Missing logic"
|
||||
|
||||
return &g_lcddev.dev;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,425 @@
|
||||
/**************************************************************************************
|
||||
* drivers/lcd/ssd1289.h
|
||||
* Definitions for the Solomon Systech SSD1289 LCD controller
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* References: SSD1289, Rev 1.3, Apr 2007, Solomon Systech Limited
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
**************************************************************************************/
|
||||
|
||||
#ifndef __DRIVERS_LCD_SSD1289_H
|
||||
#define __DRIVERS_LCD_SSD1289_H
|
||||
|
||||
/**************************************************************************************
|
||||
* Included Files
|
||||
**************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#ifdef CONFIG_LCD_SSD1289
|
||||
|
||||
/**************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
**************************************************************************************/
|
||||
|
||||
/* SSD1289 Register Addresses (All with DC=1) */
|
||||
|
||||
#define SSD1289_OSCSTART 0x00 /* Oscillation Start (write) */
|
||||
#define SSD1289_DEVCODE 0x00 /* Oscillation Start (read) */
|
||||
#define SSD1289_OUTCTRL 0x01 /* Driver output control */
|
||||
#define SSD1289_ACCTRL 0x02 /* LCD drive AC control */
|
||||
#define SSD1289_PWRCTRL1 0x03 /* Power control 1 */
|
||||
#define SSD1289_CMP1 0x05 /* Compare register 1 */
|
||||
#define SSD1289_CMP2 0x06 /* Compare register 2 */
|
||||
#define SSD1289_DSPCTRL 0x07 /* Display control */
|
||||
#define SSD1289_FCYCCTRL 0x0b /* Frame cycle control */
|
||||
#define SSD1289_PWRCTRL2 0x0c /* Power control 2 */
|
||||
#define SSD1289_PWRCTRL3 0x0d /* Power control 3 */
|
||||
#define SSD1289_PWRCTRL4 0x0e /* Power control 4 */
|
||||
#define SSD1289_GSTART 0x0f /* Gate scan start position */
|
||||
#define SSD1289_SLEEP 0x10 /* Sleep mode */
|
||||
#define SSD1289_ENTRY 0x11 /* Entry mode */
|
||||
#define SSD1289_OPT3 0x12 /* Optimize Access Speed 3 */
|
||||
#define SSD1289_GIFCTRL 0x15 /* Generic Interface Control */
|
||||
#define SSD1289_HPORCH 0x16 /* Horizontal Porch */
|
||||
#define SSD1289_VPORCH 0x17 /* Vertical Porch */
|
||||
#define SSD1289_PWRCTRL5 0x1e /* Power control 5 */
|
||||
#define SSD1289_DATA 0x22 /* RAM data/write data */
|
||||
#define SSD1289_WRMASK1 0x23 /* RAM write data mask 1 */
|
||||
#define SSD1289_WRMASK2 0x24 /* RAM write data mask 2 */
|
||||
#define SSD1289_FFREQ 0x25 /* Frame Frequency */
|
||||
#define SSD1289_VCOMOTP1 0x28 /* VCOM OTP */
|
||||
#define SSD1289_OPT1 0x28 /* Optimize Access Speed 1 */
|
||||
#define SSD1289_VCOMOTP2 0x29 /* VCOM OTP */
|
||||
#define SSD1289_OPT2 0x2f /* Optimize Access Speed 2 */
|
||||
#define SSD1289_GAMMA1 0x30 /* Gamma control 1 */
|
||||
#define SSD1289_GAMMA2 0x31 /* Gamma control 2 */
|
||||
#define SSD1289_GAMMA3 0x32 /* Gamma control 3 */
|
||||
#define SSD1289_GAMMA4 0x33 /* Gamma control 4 */
|
||||
#define SSD1289_GAMMA5 0x34 /* Gamma control 5 */
|
||||
#define SSD1289_GAMMA6 0x35 /* Gamma control 6 */
|
||||
#define SSD1289_GAMMA7 0x36 /* Gamma control 7 */
|
||||
#define SSD1289_GAMMA8 0x37 /* Gamma control 8 */
|
||||
#define SSD1289_GAMMA9 0x3a /* Gamma control 9 */
|
||||
#define SSD1289_GAMMA10 0x3b /* Gamma control 10 */
|
||||
#define SSD1289_VSCROLL1 0x41 /* Vertical scroll control 1 */
|
||||
#define SSD1289_VSCROLL2 0x42 /* Vertical scroll control 2 */
|
||||
#define SSD1289_HADDR 0x44 /* Horizontal RAM address position */
|
||||
#define SSD1289_VSTART 0x45 /* Vertical RAM address start position */
|
||||
#define SSD1289_VEND 0x46 /* Vertical RAM address end position */
|
||||
#define SSD1289_W1START 0x48 /* First window start */
|
||||
#define SSD1289_W1END 0x49 /* First window end */
|
||||
#define SSD1289_W2START 0x4a /* Second window start */
|
||||
#define SSD1289_W2END 0x4b /* Second window end */
|
||||
#define SSD1289_XADDR 0x4e /* Set GDDRAM X address counter */
|
||||
#define SSD1289_YADDR 0x4f /* Set GDDRAM Y address counter */
|
||||
|
||||
/* SSD1289 Register Bit definitions */
|
||||
|
||||
/* Index register (DC=0) */
|
||||
|
||||
#define SSD1289_INDEX_MASK 0xff
|
||||
|
||||
/* Device code (read) */
|
||||
|
||||
#define SSD1289_DEVCODE_VALUE 0x8989
|
||||
|
||||
/* Oscillation Start (write) */
|
||||
|
||||
#define SSD1289_OSCSTART_OSCEN (1 << 0) /* Enable oscillator */
|
||||
|
||||
/* Driver output control */
|
||||
|
||||
#define SSD1289_OUTCTRL_MUX_SHIFT (0) /* Number of lines for the LCD driver */
|
||||
#define SSD1289_OUTCTRL_MUX_MASK (0x1ff << SSD1289_OUTCTRL_MUX_SHIFT)
|
||||
# define SSD1289_OUTCTRL_MUX(n) ((n) << SSD1289_OUTCTRL_MUX_SHIFT)
|
||||
#define SSD1289_OUTCTRL_TB (1 << 9) /* Selects the output shift direction of the gate driver */
|
||||
#define SSD1289_OUTCTRL_SM (1 << 10) /* Scanning order of gate driver */
|
||||
#define SSD1289_OUTCTRL_BGR (1 << 11) /* Order from RGB to BGR in 18-bit GDDRAM data */
|
||||
#define SSD1289_OUTCTRL_CAD (1 << 12) /* Retention capacitor configuration of the TFT panel */
|
||||
#define SSD1289_OUTCTRL_REV (1 << 13) /* Reversed display */
|
||||
#define SSD1289_OUTCTRL_RL (1 << 14) /* RL pin state */
|
||||
|
||||
/* LCD drive AC control */
|
||||
|
||||
#define SSD1289_ACCTRL_NW_SHIFT (0) /* Number of lines to alternate in N-line inversion */
|
||||
#define SSD1289_ACCTRL_NW_MASK (0xff << SSD1289_ACCTRL_NW_SHIFT)
|
||||
#define SSD1289_ACCTRL_WSMD (1 << 8) /* Waveform of WSYNC output */
|
||||
#define SSD1289_ACCTRL_EOR (1 << 9) /* EOR signals */
|
||||
#define SSD1289_ACCTRL_BC (1 << 10) /* Select the liquid crystal drive waveform */
|
||||
#define SSD1289_ACCTRL_ENWS (1 << 11) /* Enables WSYNC output pin */
|
||||
#define SSD1289_ACCTRL_FLD (1 << 12) /* Set display in interlace drive mode */
|
||||
|
||||
/* Power control 1 */
|
||||
|
||||
#define SSD1289_PWRCTRL1_AP_SHIFT (1) /* Current from internal operational amplifier */
|
||||
#define SSD1289_PWRCTRL1_AP_MASK (7 << SSD1289_PWRCTRL1_AP_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_AP_LEAST (0 << SSD1289_PWRCTRL1_AP_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_AP_SMALL (1 << SSD1289_PWRCTRL1_AP_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_AP_SMMED (2 << SSD1289_PWRCTRL1_AP_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_AP_MEDIUM (3 << SSD1289_PWRCTRL1_AP_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_AP_MEDLG (4 << SSD1289_PWRCTRL1_AP_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_AP_LARGE (5 << SSD1289_PWRCTRL1_AP_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_AP_LGMX (6 << SSD1289_PWRCTRL1_AP_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_AP_MAX (7 << SSD1289_PWRCTRL1_AP_SHIFT)
|
||||
#define SSD1289_PWRCTRL1_DC_SHIFT (4) /* Set the step-up cycle of the step-up circuit for 262k-color mode */
|
||||
#define SSD1289_PWRCTRL1_DC_MASK (15 << SSD1289_PWRCTRL1_DC_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DC_FLINEx24 (0 << SSD1289_PWRCTRL1_DC_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DC_FLINEx16 (1 << SSD1289_PWRCTRL1_DC_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DC_FLINEx12 (2 << SSD1289_PWRCTRL1_DC_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DC_FLINEx8 (3 << SSD1289_PWRCTRL1_DC_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DC_FLINEx6 (4 << SSD1289_PWRCTRL1_DC_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DC_FLINEx5 (5 << SSD1289_PWRCTRL1_DC_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DC_FLINEx4 (6 << SSD1289_PWRCTRL1_DC_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DC_FLINEx3 (7 << SSD1289_PWRCTRL1_DC_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DC_FLINEx2 (8 << SSD1289_PWRCTRL1_DC_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DC_FLINEx1 (9 << SSD1289_PWRCTRL1_DC_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DC_FOSd4 (10 << SSD1289_PWRCTRL1_DC_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DC_FOSd6 (11 << SSD1289_PWRCTRL1_DC_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DC_FOSd8 (12 << SSD1289_PWRCTRL1_DC_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DC_FOSd10 (13 << SSD1289_PWRCTRL1_DC_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DC_FOSd12 (14 << SSD1289_PWRCTRL1_DC_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DC_FOSd16 (15 << SSD1289_PWRCTRL1_DC_SHIFT)
|
||||
#define SSD1289_PWRCTRL1_BT_SHIFT (9) /* Control the step-up factor of the step-up circuit */
|
||||
#define SSD1289_PWRCTRL1_BT_MASK (7 << SSD1289_PWRCTRL1_BT_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_BT_p6m5 (0 << SSD1289_PWRCTRL1_BT_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_BT_p6m4 (1 << SSD1289_PWRCTRL1_BT_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_BT_p6m6 (2 << SSD1289_PWRCTRL1_BT_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_BT_p5m5 (3 << SSD1289_PWRCTRL1_BT_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_BT_p5m4 (4 << SSD1289_PWRCTRL1_BT_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_BT_p5m3 (5 << SSD1289_PWRCTRL1_BT_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_BT_p4m4 (6 << SSD1289_PWRCTRL1_BT_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_BT_p4m3 (7 << SSD1289_PWRCTRL1_BT_SHIFT)
|
||||
#define SSD1289_PWRCTRL1_DCT_SHIFT (12) /* Step-up cycle of the step-up circuit for 8-color mode */
|
||||
#define SSD1289_PWRCTRL1_DCT_MASK (15 << SSD1289_PWRCTRL1_DCT_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DCT_FLINEx24 (0 << SSD1289_PWRCTRL1_DCT_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DCT_FLINEx16 (1 << SSD1289_PWRCTRL1_DCT_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DCT_FLINEx12 (2 << SSD1289_PWRCTRL1_DCT_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DCT_FLINEx8 (3 << SSD1289_PWRCTRL1_DCT_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DCT_FLINEx6 (4 << SSD1289_PWRCTRL1_DCT_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DCT_FLINEx5 (5 << SSD1289_PWRCTRL1_DCT_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DCT_FLINEx4 (6 << SSD1289_PWRCTRL1_DCT_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DCT_FLINEx3 (7 << SSD1289_PWRCTRL1_DCT_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DCT_FLINEx2 (8 << SSD1289_PWRCTRL1_DCT_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DCT_FLINEx1 (9 << SSD1289_PWRCTRL1_DCT_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DCT_FOSd4 (10 << SSD1289_PWRCTRL1_DCT_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DCT_FOSd6 (11 << SSD1289_PWRCTRL1_DCT_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DCT_FOSd8 (12 << SSD1289_PWRCTRL1_DCT_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DCT_FOSd10 (13 << SSD1289_PWRCTRL1_DCT_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DCT_FOSd12 (14 << SSD1289_PWRCTRL1_DCT_SHIFT)
|
||||
# define SSD1289_PWRCTRL1_DCT_FOSd16 (15 << SSD1289_PWRCTRL1_DCT_SHIFT)
|
||||
|
||||
/* Compare register 1 and 2 */
|
||||
|
||||
#define SSD1289_CMP1_CPG_SHIFT (2)
|
||||
#define SSD1289_CMP1_CPG_MASK (0x3f << SSD1289_CMP1_CPG_SHIFT)
|
||||
#define SSD1289_CMP1_CPR_SHIFT (10)
|
||||
#define SSD1289_CMP1_CPR_MASK (0x3f << SSD1289_CMP1_CPR_SHIFT)
|
||||
|
||||
#define SSD1289_CMP2_CPB_SHIFT (2)
|
||||
#define SSD1289_CMP2_CPB_MASK (0x3f << SSD1289_CMP2_CPB_SHIFT)
|
||||
|
||||
/* Display control */
|
||||
|
||||
#define SSD1289_DSPCTRL_D_SHIFT (0) /* Display control */
|
||||
#define SSD1289_DSPCTRL_D_MASK (3 << SSD1289_DSPCTRL_D_SHIFT)
|
||||
# define SSD1289_DSPCTRL_OFF (0 << SSD1289_DSPCTRL_D_SHIFT)
|
||||
# define SSD1289_DSPCTRL_INTERNAL (1 << SSD1289_DSPCTRL_D_SHIFT)
|
||||
# define SSD1289_DSPCTRL_ON (3 << SSD1289_DSPCTRL_D_SHIFT)
|
||||
#define SSD1289_DSPCTRL_CM (1 << 3) /* 8-color mode setting */
|
||||
#define SSD1289_DSPCTRL_DTE (1 << 4) /* Selected gate level */
|
||||
#define SSD1289_DSPCTRL_GON (1 << 5) /* Gate off level */
|
||||
#define SSD1289_DSPCTRL_SPT (1 << 8) /* 2-division LCD drive */
|
||||
#define SSD1289_DSPCTRL_VLE_SHIFT (9) /* Vertical scroll control */
|
||||
#define SSD1289_DSPCTRL_VLE_MASK (3 << SSD1289_DSPCTRL_VLE_SHIFT)
|
||||
# define SSD1289_DSPCTRL_VLE(n) ((n) << SSD1289_DSPCTRL_VLE_SHIFT)
|
||||
#define SSD1289_DSPCTRL_PT_SHIFT (11) /* Normalize the source outputs */
|
||||
#define SSD1289_DSPCTRL_PT_MASK (3 << SSD1289_DSPCTRL_PT_SHIFT)
|
||||
# define SSD1289_DSPCTRL_PT(n) ((n) << SSD1289_DSPCTRL_PT_SHIFT)
|
||||
|
||||
/* Frame cycle control */
|
||||
|
||||
#define SSD1289_FCYCCTRL_RTN_SHIFT (0) /* Number of clocks in each line */
|
||||
#define SSD1289_FCYCCTRL_RTN_MASK (3 << SSD1289_FCYCCTRL_RTN_SHIFT)
|
||||
# define SSD1289_FCYCCTRL_RTN(n) (((n)-16) << SSD1289_FCYCCTRL_RTN_SHIFT)
|
||||
#define SSD1289_FCYCCTRL_SRTN (1 << 4) /* When SRTN =1, RTN3-0 value will be count */
|
||||
#define SSD1289_FCYCCTRL_SDIV (1 << 5) /* When SDIV = 1, DIV1-0 value will be count */
|
||||
#define SSD1289_FCYCCTRL_DIV_SHIFT (6) /* Set the division ratio of clocks */
|
||||
#define SSD1289_FCYCCTRL_DIV_MASK (3 << SSD1289_FCYCCTRL_DIV_SHIFT)
|
||||
# define SSD1289_FCYCCTRL_DIV1 (0 << SSD1289_FCYCCTRL_DIV_SHIFT)
|
||||
# define SSD1289_FCYCCTRL_DIV2 (1 << SSD1289_FCYCCTRL_DIV_SHIFT)
|
||||
# define SSD1289_FCYCCTRL_DIV4 (2 << SSD1289_FCYCCTRL_DIV_SHIFT)
|
||||
# define SSD1289_FCYCCTRL_DIV8 (3 << SSD1289_FCYCCTRL_DIV_SHIFT)
|
||||
#define SSD1289_FCYCCTRL_EQ_SHIFT (8) /* Sets the equalizing period */
|
||||
#define SSD1289_FCYCCTRL_EQ_MASK (3 << SSD1289_FCYCCTRL_EQ_SHIFT)
|
||||
# define SSD1289_FCYCCTRL_EQ(n) (((n)-1) << SSD1289_FCYCCTRL_EQ_SHIFT) /* n = 2-8 clocks */
|
||||
#define SSD1289_FCYCCTRL_SDT_SHIFT (12) /* Set delay amount from the gate output */
|
||||
#define SSD1289_FCYCCTRL_SDT_MASK (3 << SSD1289_FCYCCTRL_SDT_SHIFT)
|
||||
# define SSD1289_FCYCCTRL_SDT(n) ((n) << SSD1289_FCYCCTRL_SDT_SHIFT) /* n = 1-3 clocks */
|
||||
#define SSD1289_FCYCCTRL_NO_SHIFT (14) /* Sets amount of non-overlap of the gate output */
|
||||
#define SSD1289_FCYCCTRL_NO_MASK (3 << SSD1289_FCYCCTRL_NO_SHIFT)
|
||||
# define SSD1289_FCYCCTRL_NO(n) ((n) << SSD1289_FCYCCTRL_NO_SHIFT) /* n = 1-3 clocks */
|
||||
|
||||
/* Power control 2 */
|
||||
|
||||
#define SSD1289_PWRCTRL2_VRC_SHIFT (0) /* Adjust VCIX2 output voltage */
|
||||
#define SSD1289_PWRCTRL2_VRC_MASK (7 << SSD1289_PWRCTRL2_VRC_SHIFT)
|
||||
# define SSD1289_PWRCTRL2_VRC_5p1V (0 << SSD1289_PWRCTRL2_VRC_SHIFT)
|
||||
# define SSD1289_PWRCTRL2_VRC_5p2V (1 << SSD1289_PWRCTRL2_VRC_SHIFT)
|
||||
# define SSD1289_PWRCTRL2_VRC_5p3V (2 << SSD1289_PWRCTRL2_VRC_SHIFT)
|
||||
# define SSD1289_PWRCTRL2_VRC_5p4V (3 << SSD1289_PWRCTRL2_VRC_SHIFT)
|
||||
# define SSD1289_PWRCTRL2_VRC_5p5V (4 << SSD1289_PWRCTRL2_VRC_SHIFT)
|
||||
# define SSD1289_PWRCTRL2_VRC_5p6V (5 << SSD1289_PWRCTRL2_VRC_SHIFT)
|
||||
# define SSD1289_PWRCTRL2_VRC_5p7V (6 << SSD1289_PWRCTRL2_VRC_SHIFT)
|
||||
# define SSD1289_PWRCTRL2_VRC_5p8V (7 << SSD1289_PWRCTRL2_VRC_SHIFT)
|
||||
|
||||
/* Power control 3 */
|
||||
|
||||
#define SSD1289_PWRCTRL3_VRH_SHIFT (0) /* Set amplitude magnification of VLCD63 */
|
||||
#define SSD1289_PWRCTRL3_VRH_MASK (15 << SSD1289_PWRCTRL3_VRH_SHIFT)
|
||||
# define SSD1289_PWRCTRL3_VRH_x1p540 (0 << SSD1289_PWRCTRL3_VRH_SHIFT)
|
||||
# define SSD1289_PWRCTRL3_VRH_x1p620 (1 << SSD1289_PWRCTRL3_VRH_SHIFT)
|
||||
# define SSD1289_PWRCTRL3_VRH_x1p700 (2 << SSD1289_PWRCTRL3_VRH_SHIFT)
|
||||
# define SSD1289_PWRCTRL3_VRH_x1p780 (3 << SSD1289_PWRCTRL3_VRH_SHIFT)
|
||||
# define SSD1289_PWRCTRL3_VRH_x1p850 (4 << SSD1289_PWRCTRL3_VRH_SHIFT)
|
||||
# define SSD1289_PWRCTRL3_VRH_x1p930 (5 << SSD1289_PWRCTRL3_VRH_SHIFT)
|
||||
# define SSD1289_PWRCTRL3_VRH_x2p020 (6 << SSD1289_PWRCTRL3_VRH_SHIFT)
|
||||
# define SSD1289_PWRCTRL3_VRH_x2p090 (7 << SSD1289_PWRCTRL3_VRH_SHIFT)
|
||||
# define SSD1289_PWRCTRL3_VRH_x2p165 (8 << SSD1289_PWRCTRL3_VRH_SHIFT)
|
||||
# define SSD1289_PWRCTRL3_VRH_x2p245 (9 << SSD1289_PWRCTRL3_VRH_SHIFT)
|
||||
# define SSD1289_PWRCTRL3_VRH_x2p335 (10 << SSD1289_PWRCTRL3_VRH_SHIFT)
|
||||
# define SSD1289_PWRCTRL3_VRH_x2p400 (11 << SSD1289_PWRCTRL3_VRH_SHIFT)
|
||||
# define SSD1289_PWRCTRL3_VRH_x2p500 (12 << SSD1289_PWRCTRL3_VRH_SHIFT)
|
||||
# define SSD1289_PWRCTRL3_VRH_x2p570 (13 << SSD1289_PWRCTRL3_VRH_SHIFT)
|
||||
# define SSD1289_PWRCTRL3_VRH_x2p645 (14 << SSD1289_PWRCTRL3_VRH_SHIFT)
|
||||
# define SSD1289_PWRCTRL3_VRH_x2p725 (15 << SSD1289_PWRCTRL3_VRH_SHIFT)
|
||||
|
||||
/* Power control 4 */
|
||||
|
||||
#define SSD1289_PWRCTRL4_VDV_SHIFT (8) /* Set amplitude magnification of VLCD63 */
|
||||
#define SSD1289_PWRCTRL4_VDV_MASK (32 << SSD1289_PWRCTRL4_VDV_SHIFT)
|
||||
# define SSD1289_PWRCTRL4_VDV(n) ((n) << SSD1289_PWRCTRL4_VDV_SHIFT)
|
||||
#define SSD1289_PWRCTRL4_VCOMG (1 << 13) /* VcomL variable */
|
||||
|
||||
/* Gate scan start position */
|
||||
|
||||
#define SSD1289_GSTART_MASK 0x1ff
|
||||
|
||||
/* Sleep mode */
|
||||
|
||||
#define SSD1289_SLEEP_ON (1 << 0)
|
||||
|
||||
/* Entry mode */
|
||||
|
||||
#define SSD1289_ENTRY_LG_SHIFT (0) /* Write after comparing */
|
||||
#define SSD1289_ENTRY_LG_MASK (7 << SSD1289_ENTRY_LG_SHIFT)
|
||||
#define SSD1289_ENTRY_AM (1 << 3) /* Address counter direction */
|
||||
#define SSD1289_ENTRY_ID_SHIFT (4) /* Address increment mode */
|
||||
#define SSD1289_ENTRY_ID_MASK (3 << SSD1289_ENTRY_ID_SHIFT)
|
||||
# define SSD1289_ENTRY_ID_HDECVDEC (0 << SSD1289_ENTRY_ID_SHIFT)
|
||||
# define SSD1289_ENTRY_ID_HINCVDEC (1 << SSD1289_ENTRY_ID_SHIFT)
|
||||
# define SSD1289_ENTRY_ID_HDECVINC (2 << SSD1289_ENTRY_ID_SHIFT)
|
||||
# define SSD1289_ENTRY_ID_HINCVINC (3 << SSD1289_ENTRY_ID_SHIFT)
|
||||
#define SSD1289_ENTRY_TY_SHIFT (6) /* RAM data write method */
|
||||
#define SSD1289_ENTRY_TY_MASK (3 << SSD1289_ENTRY_TY_SHIFT)
|
||||
# define SSD1289_ENTRY_TY_A (0 << SSD1289_ENTRY_TY_SHIFT)
|
||||
# define SSD1289_ENTRY_TY_B (1 << SSD1289_ENTRY_TY_SHIFT)
|
||||
# define SSD1289_ENTRY_TY_C (2 << SSD1289_ENTRY_TY_SHIFT)
|
||||
#define SSD1289_ENTRY_DMODE_SHIFT (8) /* Data display mode */
|
||||
#define SSD1289_ENTRY_DMODE_MASK (3 << SSD1289_ENTRY_DMODE_SHIFT)
|
||||
# define SSD1289_ENTRY_DMODE_RAM (0 << SSD1289_ENTRY_DMODE_SHIFT)
|
||||
# define SSD1289_ENTRY_DMODE_GENERIC (1 << SSD1289_ENTRY_DMODE_SHIFT)
|
||||
# define SSD1289_ENTRY_DMODE_RAMGEN (2 << SSD1289_ENTRY_DMODE_SHIFT)
|
||||
# define SSD1289_ENTRY_DMODE_GENRAM (3 << SSD1289_ENTRY_DMODE_SHIFT)
|
||||
#define SSD1289_ENTRY_WMODE (1 << 10) /* Select source of data in RAM */
|
||||
#define SSD1289_ENTRY_OEDEF (1 << 11) /* Define display window */
|
||||
#define SSD1289_ENTRY_TRANS (1 << 12) /* Transparent display */
|
||||
#define SSD1289_ENTRY_DFM_SHIFT (13) /* Color display mode */
|
||||
#define SSD1289_ENTRY_DFM_MASK (3 << SSD1289_ENTRY_DFM_SHIFT)
|
||||
# define SSD1289_ENTRY_DFM_262K (2 << SSD1289_ENTRY_DFM_SHIFT)
|
||||
# define SSD1289_ENTRY_DFM_65K (3 << SSD1289_ENTRY_DFM_SHIFT)
|
||||
#define SSD1289_ENTRY_VSMODE (1 << 15) /* Frame frequency depends on VSYNC */
|
||||
|
||||
/* Generic Interface Control */
|
||||
|
||||
#define SSD1289_GIFCTRL_INVVS (1 << 0) /* Sets the signal polarity of DOTCLK pin */
|
||||
#define SSD1289_GIFCTRL_INVHS (1 << 1) /* Sets the signal polarity of DEN pin */
|
||||
#define SSD1289_GIFCTRL_NVDEN (1 << 2) /* Sets the signal polarity of HSYNC pin */
|
||||
#define SSD1289_GIFCTRL_INVDOT (1 << 3) /* Sets the signal polarity of VSYNC pin */
|
||||
|
||||
/* Horizontal Porch */
|
||||
|
||||
#define SSD1289_HPORCH_HBP_SHIFT (0) /* Set delay from falling edge of HSYNC signal to data */
|
||||
#define SSD1289_HPORCH_HBP_MASK (0xff << SSD1289_HPORCH_HBP_SHIFT)
|
||||
#define SSD1289_HPORCH_XL_SHIFT (8) /* number of valid pixel per line */
|
||||
#define SSD1289_HPORCH_XL_MASK (0xff << SSD1289_HPORCH_XL_SHIFT)
|
||||
|
||||
/* Vertical Porch */
|
||||
|
||||
#define SSD1289_VPORCH_VBP_SHIFT (0) /* Set delay from falling edge of VSYNC signal to line */
|
||||
#define SSD1289_VPORCH_VBP_MASK (0xff << SSD1289_VPORCH_VBP_SHIFT)
|
||||
#define SSD1289_VPORCH_XFP_SHIFT (8) /* Delay from last line to falling edge of VSYNC of next frame */
|
||||
#define SSD1289_VPORCH_XFP_MASK (0xff << SSD1289_VPORCH_XFP_SHIFT)
|
||||
#define SSD1289_VPORCH_
|
||||
|
||||
/* Power control 5 */
|
||||
|
||||
#define SSD1289_PWRCTRL5_VCM_SHIFT (0) /* Set the VcomH voltage */
|
||||
#define SSD1289_PWRCTRL5_VCM_MASK (0x3f << SSD1289_PWRCTRL5_VCM_SHIFT)
|
||||
# define SSD1289_PWRCTRL5_VCM(n) ((n) << SSD1289_PWRCTRL5_VCM_SHIFT)
|
||||
#define SSD1289_PWRCTRL5_NOTP (1 << 7) /* 1=VCM valid */
|
||||
|
||||
/* RAM write data mask 1 */
|
||||
|
||||
#define SSD1289_WRMASK1_WMG_SHIFT (2)
|
||||
#define SSD1289_WRMASK1_WMG_MASK (0x3f << SSD1289_WRMASK1_WMG_SHIFT)
|
||||
#define SSD1289_WRMASK1_WMR_SHIFT (10)
|
||||
#define SSD1289_WRMASK1_WMR_MASK (0x3f << SSD1289_WRMASK1_WMR_SHIFT)
|
||||
|
||||
#define SSD1289_WRMASK2_WMB_SHIFT (2)
|
||||
#define SSD1289_WRMASK2_WMB_MASK (0x3f << SSD1289_WRMASK2_WMB_SHIFT)
|
||||
|
||||
/* Frame Frequency */
|
||||
|
||||
#define SSD1289_FFREQ_OSC_SHIFT (12) /* Set the frame frequency */
|
||||
#define SSD1289_FFREQ_OSC_MASK (15 << SSD1289_FFREQ_OSC_SHIFT)
|
||||
# define SSD1289_FFREQ_OSC_FF50 (0 << SSD1289_FFREQ_OSC_SHIFT)
|
||||
# define SSD1289_FFREQ_OSC_FF55 (2 << SSD1289_FFREQ_OSC_SHIFT)
|
||||
# define SSD1289_FFREQ_OSC_FF60 (5 << SSD1289_FFREQ_OSC_SHIFT)
|
||||
# define SSD1289_FFREQ_OSC_FF65 (8 << SSD1289_FFREQ_OSC_SHIFT)
|
||||
# define SSD1289_FFREQ_OSC_FF70 (10 << SSD1289_FFREQ_OSC_SHIFT)
|
||||
# define SSD1289_FFREQ_OSC_FF75 (12 << SSD1289_FFREQ_OSC_SHIFT)
|
||||
# define SSD1289_FFREQ_OSC_FF80 (14 << SSD1289_FFREQ_OSC_SHIFT)
|
||||
|
||||
/* VCOM OTP */
|
||||
|
||||
#define SSD1289_VCOMOTP1_ACTIVATE 0x0006
|
||||
#define SSD1289_VCOMOTP1_FIRE 0x000a
|
||||
#define SSD1289_VCOMOTP2_ACTIVATE 0x80c0
|
||||
|
||||
/* Optimize Access Speed 1, 2, 3 (omitted) */
|
||||
|
||||
/* Gamma control 1-10. Magic values. I won't try to represent the fields. */
|
||||
|
||||
/* Vertical scroll control 1 and 2 */
|
||||
|
||||
#define SSD1289_VSCROLL_MASK 0x1ff /* Scroll length */
|
||||
|
||||
/* Horizontal RAM address position */
|
||||
|
||||
#define SSD1289_HADDR_HSA_SHIFT (0) /* Window horizontal start address */
|
||||
#define SSD1289_HADDR_HSA_MASK (0xff << SSD1289_HADDR_HSA_SHIFT)
|
||||
#define SSD1289_HADDR_HEA_SHIFT (8) /* Window horizontal end address */
|
||||
#define SSD1289_HADDR_HEA_MASK (0xff << SSD1289_HADDR_HEA_SHIFT)
|
||||
|
||||
/* Vertical RAM address start/end position */
|
||||
|
||||
#define SSD1289_VSTART_MASK 0x1ff /* Window Vertical start address */
|
||||
#define SSD1289_VEND_MASK 0x1ff /* Window Vertical end address */
|
||||
|
||||
/* First window start/end */
|
||||
|
||||
#define SSD1289_W1START_MASK 0x1ff /* Start line for first screen */
|
||||
#define SSD1289_W1END_MASK 0x1ff /* End line for first screen */
|
||||
|
||||
/* Second window start/end */
|
||||
|
||||
#define SSD1289_W2START_MASK 0x1ff /* Start line for second screen */
|
||||
#define SSD1289_W2END_MASK 0x1ff /* End line for second screen */
|
||||
|
||||
/* Set GDDRAM X/Y address counter */
|
||||
|
||||
#define SSD1289_XADDR_MASK 0xff /* GDDRAM X address in the address counter */
|
||||
#define SSD1289_YADDR_MASK 0x1ff /* GDDRAM Y address in the address counter */
|
||||
|
||||
#endif /* CONFIG_LCD_SSD1289 */
|
||||
#endif /* __DRIVERS_LCD_SSD1289_H */
|
||||
@@ -0,0 +1,211 @@
|
||||
/**************************************************************************************
|
||||
* drivers/lcd/ssd1305.h
|
||||
* Definitions for the Solomon Systech SSD1305 132x64 Dot Matrix OLED/PLED
|
||||
* Segment/Common Driver with C
|
||||
*
|
||||
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* References: SSD1305.pdf, "Solomon Systech SSD1305 132x64 Dot Matrix OLED/PLED
|
||||
* Segment/Common Driver with Controller," Solomon Systech Limited,
|
||||
* http://www.solomon-systech.com, May, 2008.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
**************************************************************************************/
|
||||
|
||||
#ifndef __DRIVERS_LCD_SSD1305_H
|
||||
#define __DRIVERS_LCD_SSD1305_H
|
||||
|
||||
/**************************************************************************************
|
||||
* Included Files
|
||||
**************************************************************************************/
|
||||
|
||||
/**************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
**************************************************************************************/
|
||||
/* General Definitions ******************************************************/
|
||||
|
||||
#define SSD1305_COLORA 0
|
||||
#define SSD1305_COLORB 1
|
||||
#define SSD1305_COLORC 2
|
||||
#define SSD1305_COLORD 3
|
||||
|
||||
/* Fundamental Commands *****************************************************/
|
||||
#define SSD1305_SETCOLL 0x00 /* 0x00-0x0f: Set lower column address */
|
||||
# define SSD1305_COLL_MASK 0x0f
|
||||
#define SSD1305_SETCOLH 0x10 /* 0x10-0x1f: Set higher column address */
|
||||
# define SSD1305_COLH_MASK 0x0f
|
||||
#define SSD1305_ADDRMODE 0x20 /* 0x20: Set memory address mode */
|
||||
# define SSD1305_ADDRMODE_HOR 0x00 /* Data 1: Set horizontal address mode */
|
||||
# define SSD1305_ADDRMODE_VIRT 0x01 /* Data 1: Set virtal address mode */
|
||||
# define SSD1305_ADDRMODE_PAGE 0x02 /* Data 1: Set page address mode */
|
||||
#define SSD1305_SETCOLADDR 0x21 /* 0x21: Set column address */
|
||||
/* Data 1: Column start address: 0-131 */
|
||||
/* Data 2: Column end address: 0-131 */
|
||||
#define SSD1305_SETPAGEADDR 0x22 /* 0x22: Set page address */
|
||||
/* Data 1: Page start address: 0x00-0x7d */
|
||||
/* Data 2: Page end address: 0x00-0x7d */
|
||||
#define SSD1305_SETSTARTLINE 0x40 /* 0x40-7f: Set display start line */
|
||||
# define SSD1305_STARTLINE_MASK 0x3f
|
||||
|
||||
#define SSD1305_SETCONTRAST 0x81 /* 0x81: Set contrast control */
|
||||
/* Data 1: Set 1 of 256 contrast steps */
|
||||
#define SSD1305_SETBRIGHTNESS 0x82 /* 0x82: Set brightness */
|
||||
/* Data 1: Set 1 of 256 contrast steps */
|
||||
#define SSD1305_SETLUT 0x91 /* 0x01: Set lookup table */
|
||||
/* Data 1: Pulse width: 31-63 */
|
||||
/* Data 2: Color A: 31-63 */
|
||||
/* Data 3: Color B: 31-63 */
|
||||
/* Data 4: Color C: 31-63 */
|
||||
#define SSD1305_SETBANKCOLOR1 0x92 /* 0x92: Set bank 1-16 color */
|
||||
# define SSD1305_SETBANK1(c) (c) /* Data 1, Bits 0-1: Bank 1 color */
|
||||
# define SSD1305_SETBANK2(c) (c << 2) /* Data 1, Bits 2-3: Bank 2 color */
|
||||
# define SSD1305_SETBANK3(c) (c << 4) /* Data 1, Bits 4-5: Bank 3 color */
|
||||
# define SSD1305_SETBANK4(c) (c << 6) /* Data 1, Bits 6-7: Bank 4 color */
|
||||
# define SSD1305_SETBANK5(c) (c) /* Data 2, Bits 0-1: Bank 5 color */
|
||||
# define SSD1305_SETBANK6(c) (c << 2) /* Data 2, Bits 2-3: Bank 6 color */
|
||||
# define SSD1305_SETBANK7(c) (c << 4) /* Data 2, Bits 4-5: Bank 7 color */
|
||||
# define SSD1305_SETBANK8(c) (c << 6) /* Data 2, Bits 6-7: Bank 8 color */
|
||||
# define SSD1305_SETBANK9(c) (c) /* Data 3, Bits 0-1: Bank 9 color */
|
||||
# define SSD1305_SETBANK10(c) (c << 2) /* Data 3, Bits 2-3: Bank 10 color */
|
||||
# define SSD1305_SETBANK11(c) (c << 4) /* Data 3, Bits 4-5: Bank 11 color */
|
||||
# define SSD1305_SETBANK12(c) (c << 6) /* Data 3, Bits 6-7: Bank 12 color */
|
||||
# define SSD1305_SETBANK13(c) (c) /* Data 4, Bits 0-1: Bank 13 color */
|
||||
# define SSD1305_SETBANK14(c) (c << 2) /* Data 4, Bits 2-3: Bank 14 color */
|
||||
# define SSD1305_SETBANK15(c) (c << 4) /* Data 4, Bits 4-5: Bank 15 color */
|
||||
# define SSD1305_SETBANK16(c) (c << 6) /* Data 4, Bits 6-7: Bank 16 color */
|
||||
#define SSD1305_SETBANKCOLOR2 0x93 /* 0x93: Set bank 17-32 color */
|
||||
# define SSD1305_SETBANK17(c) (c) /* Data 1, Bits 0-1: Bank 17 color */
|
||||
# define SSD1305_SETBANK18(c) (c << 2) /* Data 1, Bits 2-3: Bank 18 color */
|
||||
# define SSD1305_SETBANK19(c) (c << 4) /* Data 1, Bits 4-5: Bank 19 color */
|
||||
# define SSD1305_SETBANK20(c) (c << 6) /* Data 1, Bits 6-7: Bank 20 color */
|
||||
# define SSD1305_SETBANK21(c) (c) /* Data 2, Bits 0-1: Bank 21 color */
|
||||
# define SSD1305_SETBANK22(c) (c << 2) /* Data 2, Bits 2-3: Bank 22 color */
|
||||
# define SSD1305_SETBANK23(c) (c << 4) /* Data 2, Bits 4-5: Bank 23 color */
|
||||
# define SSD1305_SETBANK24(c) (c << 6) /* Data 2, Bits 6-7: Bank 24 color */
|
||||
# define SSD1305_SETBANK25(c) (c) /* Data 3, Bits 0-1: Bank 25 color */
|
||||
# define SSD1305_SETBANK26(c) (c << 2) /* Data 3, Bits 2-3: Bank 26 color */
|
||||
# define SSD1305_SETBANK27(c) (c << 4) /* Data 3, Bits 4-5: Bank 27 color */
|
||||
# define SSD1305_SETBANK28(c) (c << 6) /* Data 3, Bits 6-7: Bank 28 color */
|
||||
# define SSD1305_SETBANK29(c) (c) /* Data 4, Bits 0-1: Bank 29 color */
|
||||
# define SSD1305_SETBANK30(c) (c << 2) /* Data 4, Bits 2-3: Bank 30 color */
|
||||
# define SSD1305_SETBANK31(c) (c << 4) /* Data 4, Bits 4-5: Bank 31 color */
|
||||
# define SSD1305_SETBANK32(c) (c << 6) /* Data 4, Bits 6-7: Bank 32 color */
|
||||
#define SSD1305_MAPCOL0 0xa0 /* 0xa0: Column address 0 is mapped to SEG0 */
|
||||
#define SSD1305_MAPCOL131 0xa1 /* 0xa1: Column address 131 is mapped to SEG0 */
|
||||
#define SSD1305_DISPRAM 0xa4 /* 0xa4: Resume to RAM content display */
|
||||
#define SSD1305_DISPENTIRE 0xa5 /* 0xa5: Entire display ON */
|
||||
#define SSD1305_DISPNORMAL 0xa6 /* 0xa6: Normal display */
|
||||
#define SSD1305_DISPINVERTED 0xa7 /* 0xa7: Inverse display */
|
||||
|
||||
#define SSD1305_SETMUX 0xa8 /* 0xa8: Set Multiplex Ratio*/
|
||||
/* Data 1: MUX ratio -1: 15-63 */
|
||||
#define SSD1305_DIMMODE 0xab /* 0xab: Dim mode setting */
|
||||
/* Data 1: Reserverd, must be zero */
|
||||
/* Data 2: Contrast for bank1: 0-255 */
|
||||
/* Data 3: Brightness for color bank: 0-255 */
|
||||
#define SSD1305_MSTRCONFIG 0xad /* 0xad: Master configuration */
|
||||
# define SSD1305_MSTRCONFIG_EXTVCC 0x8e /* Data 1: Select external Vcc */
|
||||
#define SSD1305_DISPONDIM 0xac /* 0xac: Display ON in dim mode */
|
||||
#define SSD1305_DISPOFF 0xae /* 0xae: Display OFF (sleep mode) */
|
||||
#define SSD1305_DISPON 0xaf /* 0xaf: Display ON in normal mode */
|
||||
#define SSD1305_SETPAGESTART 0xb0 /* 0xb0-b7: Set page start address */
|
||||
# define SSD1305_PAGESTART_MASK 0x07
|
||||
#define SSD1305_SETCOMNORMAL 0xc0 /* 0xc0: Set COM output, normal mode */
|
||||
#define SSD1305_SETCOMREMAPPED 0xc8 /* 0xc8: Set COM output, remapped mode */
|
||||
|
||||
#define SSD1305_SETOFFSET 0xd3 /* 0xd3: Set display offset */
|
||||
/* Data 1: Vertical shift by COM: 0-63 */
|
||||
#define SSD1305_SETDCLK 0xd5 /* 0xd5: Set display clock divide ratio/oscillator */
|
||||
# define SSD1305_DCLKDIV_SHIFT (0) /* Data 1, Bits 0-3: DCLK divide ratio/frequency*/
|
||||
# define SSD1305_DCLKDIV_MASK 0x0f
|
||||
# define SSD1305_DCLKFREQ_SHIFT (4) /* Data 1, Bits 4-7: DCLK divide oscillator frequency */
|
||||
# define SSD1305_DCLKFREQ_MASK 0xf0
|
||||
#define SSD1305_SETCOLORMODE 0xd8 /* 0xd: Set area color and low power display modes */
|
||||
# define SSD1305_COLORMODE_MONO 0x00 /* Data 1, Bits 4-5: 00=monochrome */
|
||||
# define SSD1305_COLORMODE_COLOR 0x30 /* Data 1, Bits 4-5: 11=area color enable */
|
||||
# define SSD1305_POWERMODE_NORMAL 0x00 /* Data 1, Bits 0,2: 00=normal power mode */
|
||||
# define SSD1305_POWERMODE_LOW 0x05 /* Data 1, Bits 0,2: 11=low power display mode */
|
||||
#define SSD1305_SETPRECHARGE 0xd9 /* 0xd9: Set pre-charge period */
|
||||
# define SSD1305_PHASE1_SHIFT (0) /* Data 1, Bits 0-3: Phase 1 period of up to 15 DCLK clocks */
|
||||
# define SSD1305_PHASE1_MASK 0x0f
|
||||
# define SSD1305_PHASE2_SHIFT (4) /* Data 1, Bits 4-7: Phase 2 period of up to 15 DCLK clocks */
|
||||
# define SSD1305_PHASE2_MASK 0xf0
|
||||
#define SSD1305_SETCOMCONFIG 0xda /* 0xda: Set COM configuration */
|
||||
# define SSD1305_COMCONFIG_SEQ 0x02 /* Data 1, Bit 4: 0=Sequential COM pin configuration */
|
||||
# define SSD1305_COMCONFIG_ALT 0x12 /* Data 1, Bit 4: 1=Alternative COM pin configuration */
|
||||
# define SSD1305_COMCONFIG_NOREMAP 0x02 /* Data 1, Bit 5: 0=Disable COM Left/Right remap */
|
||||
# define SSD1305_COMCONFIG_REMAP 0x22 /* Data 1, Bit 5: 1=Enable COM Left/Right remap */
|
||||
#define SSD1305_SETVCOMHDESEL 0xdb /* 0xdb: Set VCOMH delselect level */
|
||||
# define SSD1305_VCOMH_x4p3 0x00 /* Data 1: ~0.43 x Vcc */
|
||||
# define SSD1305_VCOMH_x7p7 0x34 /* Data 1: ~0.77 x Vcc */
|
||||
# define SSD1305_VCOMH_x8p3 0x3c /* Data 1: ~0.83 x Vcc */
|
||||
#define SSD1305_ENTER_RMWMODE 0xe0 /* 0xe0: Enter the Read Modify Write mode */
|
||||
#define SSD1305_NOP 0xe3 /* 0xe3: NOP Command for no operation */
|
||||
#define SSD1305_EXIT_RMWMODE 0xee /* 0xee: Leave the Read Modify Write mode */
|
||||
|
||||
/* Graphic Acceleration Commands ********************************************/
|
||||
|
||||
#define SSD1305_HSCROLL_RIGHT 0x26 /* 0x26: Right horizontal scroll */
|
||||
#define SSD1305_HSCROLL_LEFT 0x27 /* 0x27: Left horizontal scroll */
|
||||
/* Data 1, Bits 0-2: Column scroll offset: 0-4 */
|
||||
/* Data 2, Bits 0-2: Start page address: 0-7 */
|
||||
#define SSD1305_HSCROLL_FRAMES6 0x00 /* Data 3, Bits 0-2: Timer interval, 000=6 frames */
|
||||
#define SSD1305_HSCROLL_FRAMES32 0x01 /* Data 3, Bits 0-2: Timer interval, 001=32 frames */
|
||||
#define SSD1305_HSCROLL_FRAMES64 0x02 /* Data 3, Bits 0-2: Timer interval, 010=64 frames */
|
||||
#define SSD1305_HSCROLL_FRAMES128 0x03 /* Data 3, Bits 0-2: Timer interval, 011=128 frames */
|
||||
#define SSD1305_HSCROLL_FRAMES3 0x04 /* Data 3, Bits 0-2: Timer interval, 100=3 frames */
|
||||
#define SSD1305_HSCROLL_FRAMES4 0x05 /* Data 3, Bits 0-2: Timer interval, 101=4 frames */
|
||||
#define SSD1305_HSCROLL_FRAMES2 0x06 /* Data 3, Bits 0-2: Timer interval, 110=2 frames */
|
||||
/* Data 4, Bits 0-2: End page address: 0-7 */
|
||||
|
||||
#define SSD1305_VSCROLL_RIGHT 0x29 /* 0x26: Vertical and right horizontal scroll */
|
||||
#define SSD1305_VSCROLL_LEFT 0x2a /* 0x27: Vertical and left horizontal scroll */
|
||||
/* Data 1, Bits 0-2: Column scroll offset: 0-4 */
|
||||
/* Data 2, Bits 0-2: Start page address: 0-7 */
|
||||
#define SSD1305_VSCROLL_FRAMES6 0x00 /* Data 3, Bits 0-2: Timer interval, 000=6 frames */
|
||||
#define SSD1305_VSCROLL_FRAMES32 0x01 /* Data 3, Bits 0-2: Timer interval, 001=32 frames */
|
||||
#define SSD1305_VSCROLL_FRAMES64 0x02 /* Data 3, Bits 0-2: Timer interval, 010=64 frames */
|
||||
#define SSD1305_VSCROLL_FRAMES128 0x03 /* Data 3, Bits 0-2: Timer interval, 011=128 frames */
|
||||
#define SSD1305_VSCROLL_FRAMES3 0x04 /* Data 3, Bits 0-2: Timer interval, 100=3 frames */
|
||||
#define SSD1305_VSCROLL_FRAMES4 0x05 /* Data 3, Bits 0-2: Timer interval, 101=4 frames */
|
||||
#define SSD1305_VSCROLL_FRAMES2 0x06 /* Data 3, Bits 0-2: Timer interval, 110=2 frames */
|
||||
/* Data 4, Bits 0-2: End page address: 0-7 */
|
||||
/* Data 5, Bits 0-5: Vertical scrolling offset: 0-63 */
|
||||
#define SSD1305_SCROLL_STOP 0x2e /* 0x2e: Deactivate scroll */
|
||||
#define SSD1305_SCROLL_START 0x2f /* 0x2f: Activate scroll */
|
||||
#define SSD1305_VSCROLL_AREA 0xa3 /* 0xa3: Set vertical scroll area */
|
||||
/* Data 1: Number of rows in the top fixed area */
|
||||
/* Data 1: Number of rows in the scroll area */
|
||||
|
||||
/* Status register bit definitions ******************************************/
|
||||
|
||||
#define SSD1305_STATUS_DISPOFF (1 << 6) /* Bit 6: 1=Display off */
|
||||
|
||||
#endif /* __DRIVERS_LCD_SSD1305_H */
|
||||
File diff suppressed because it is too large
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Reference in New Issue
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