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This directory contains header files unique to the Freescale MX1ADS evaluation board.
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/************************************************************************************
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* configs/mx1ads/include/board.h
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* include/arch/board/board.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_BOARD_BOARD_H
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#define __ARCH_BOARD_BOARD_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* Clock settings -- All clock values are precalculated */
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#define IMX_SYS_CLK_FREQ 16780000 /* Crystal frequency */
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/* MPCTL0 -- Controls the MCU clock:
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*
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* MFI + MFN / (MFD+1)
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* IMX_MCUPLL_CLK_FREQ = 2 * IMX_SYS_CLK_FREQ * --------------------
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* PD + 1
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*/
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#if 0 /* 150 MHz */
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# define IMX_MPCTL0_MFN 16
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# define IMX_MPCTL0_MFI 9
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# define IMX_MPCTL0_MFD 99
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# define IMX_MPCTL0_PD 1
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#else /* 180 MHz */
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# define IMX_MPCTL0_MFN 441
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# define IMX_MPCTL0_MFI 4
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# define IMX_MPCTL0_MFD 938
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# define IMX_MPCTL0_PD 0
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#endif
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#define IMX_MPCTL0_VALUE \
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((IMX_MPCTL0_MFN << PLL_MPCTL0_MFN_SHIFT) |\
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(IMX_MPCTL0_MFI << PLL_MPCTL0_MFI_SHIFT) |\
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(IMX_MPCTL0_MFD << PLL_MPCTL0_MFD_SHIFT) |\
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(IMX_MPCTL0_PD << PLL_MPCTL0_PD_SHIFT))
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/* This yields: */
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#if 0 /* 150 MHz */
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# define IMX_MCUPLL_CLK_FREQ 153704800
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#else /* 180 MHz */
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# define IMX_MCUPLL_CLK_FREQ 183561405
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#endif
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/* SPCTL0 -- Controls the system PLL:
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*
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* MFI + MFN / (MFD+1)
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* IMX_SYSPLL_CLK_FREQ = 2 * IMX_SYS_CLK_FREQ * --------------------
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* PD + 1
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*/
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#define IMX_SPCTL0_MFN 678
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#define IMX_SPCTL0_MFI 5
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#define IMX_SPCTL0_MFD 938
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#define IMX_SPCTL0_PD 1
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#define IMX_SPCTL0_VALUE \
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((IMX_SPCTL0_MFN << PLL_SPCTL0_MFN_SHIFT) |\
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(IMX_SPCTL0_MFI << PLL_SPCTL0_MFI_SHIFT) |\
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(IMX_SPCTL0_MFD << PLL_SPCTL0_MFD_SHIFT) |\
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(IMX_SPCTL0_PD << PLL_SPCTL0_PD_SHIFT))
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/* This yields: */
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#define IMX_SYSPLL_CLK_FREQ 96015910
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/* PDCR -- Controls peripheral clocks */
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#define IMX_PCLKDIV1 0
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#define IMX_PCLKDIV2 0
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#define IMX_PCLKDIV3 0
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#define IMX_PCDR_VALUE \
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((IMX_PCLKDIV1 << PLL_PCDR_PCLKDIV1_SHIFT) |\
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(IMX_PCLKDIV2 << PLL_PCDR_PCLKDIV2_SHIFT) |\
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(IMX_PCLKDIV3 << PLL_PCDR_PCLKDIV3_SHIFT))
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/* PERCLK1: UART, Timers, PWM */
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#define IMX_PERCLK1_FREQ (IMX_SYSPLL_CLK_FREQ/(IMX_PCLKDIV1+1))
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/* PERCLK2: CSPI, LCD, SD */
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#define IMX_PERCLK2_FREQ (IMX_SYSPLL_CLK_FREQ/(IMX_PCLKDIV2+1))
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/* PERCLK3: SSI */
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#define IMX_PERCLK3_FREQ (IMX_SYSPLL_CLK_FREQ/(IMX_PCLKDIV3+1))
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/* CSCR settings -- Controls HCLK and BCLK and USB clock.
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* HCLK: SDRAM, CSI, Memory Stick, I2C, DMA
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*/
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#define IMX_CSCR_BCLKDIV 1
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#define IMX_CSCR_USBDIV 6
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/* LED definitions ******************************************************************/
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/* The MX1ADS has only one usable LED: Port A, bit 2 */
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/* ON OFF */
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#define LED_STARTED 0 /* OFF OFF */
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#define LED_HEAPALLOCATE 1 /* OFF OFF */
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#define LED_IRQSENABLED 2 /* OFF OFF */
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#define LED_STACKCREATED 3 /* OFF OFF */
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#define LED_INIRQ 4 /* ON OFF */
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#define LED_SIGNAL 5 /* ON OFF */
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#define LED_ASSERTION 6 /* ON OFF */
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#define LED_PANIC 7 /* ON OFF */
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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#ifndef __ASSEMBLY__
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/* All i.MX architectures must provide the following entry point. This entry point
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* is called early in the intitialization -- after all memory has been configured
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* and mapped but before any devices have been initialized.
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*/
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extern void imx_boardinitialize(void);
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#endif
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#endif /* __ARCH_BOARD_BOARD_H */
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