Resync new repository with old repo r5166

git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5153 42af7a65-404d-4744-a932-0658087f49c3

nuttx/arch/sh/src/Makefile

@@ -0,0 +1,126 @@
+############################################################################
+# arch/sh/src/Makefile
+#
+#   Copyright (C) 2008, 2011-2012 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+-include $(TOPDIR)/Make.defs
+-include chip/Make.defs
+
+ARCH_SRCDIR	= $(TOPDIR)/arch/$(CONFIG_ARCH)/src
+CFLAGS		+= -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(TOPDIR)/sched
+
+HEAD_OBJ	= $(HEAD_ASRC:.S=$(OBJEXT))
+
+ASRCS		= $(CHIP_ASRCS) $(CMN_ASRCS)
+AOBJS		= $(ASRCS:.S=$(OBJEXT))
+
+CSRCS		= $(CHIP_CSRCS) $(CMN_CSRCS)
+COBJS		= $(CSRCS:.c=$(OBJEXT))
+
+SRCS		= $(ASRCS) $(CSRCS)
+OBJS		= $(AOBJS) $(COBJS)
+
+LDFLAGS		= $(ARCHSCRIPT)
+EXTRA_LIBS	?=
+
+LINKLIBS	=
+LDPATHES	= $(addprefix -L$(TOPDIR)/,$(dir $(LINKLIBS)))
+LDLIBS		= $(patsubst lib%,-l%,$(basename $(notdir $(LINKLIBS))))
+
+BOARDDIR	= $(TOPDIR)/arch/$(CONFIG_ARCH)/src/board
+
+LIBGCC		= ${shell $(CC) $(ARCHCPUFLAGS) -print-libgcc-file-name}
+
+VPATH		= chip:common
+
+all: $(HEAD_OBJ) libarch$(LIBEXT)
+
+.PHONY: board/libboard$(LIBEXT)
+
+$(AOBJS) $(HEAD_OBJ): %$(OBJEXT): %.S
+	$(call ASSEMBLE, $<, $@)
+
+$(COBJS): %$(OBJEXT): %.c
+	$(call COMPILE, $<, $@)
+
+libarch$(LIBEXT): $(OBJS)
+	@( for obj in $(OBJS) ; do \
+		$(call ARCHIVE, $@, $${obj}); \
+	done ; )
+
+board/libboard$(LIBEXT):
+	@$(MAKE) -C board TOPDIR="$(TOPDIR)" libboard$(LIBEXT) EXTRADEFINES=$(EXTRADEFINES)
+
+nuttx: $(HEAD_OBJ) board/libboard$(LIBEXT)
+	@echo "LD: nuttx"
+	@$(LD) --entry=__start $(LDFLAGS) $(LDPATHES) -L$(BOARDDIR) -o $(TOPDIR)/$@ $(HEAD_OBJ) \
+		--start-group $(LDLIBS) -lboard $(EXTRA_LIBS) $(LIBGCC) --end-group
+	@$(NM) $(TOPDIR)/$@ | \
+	grep -v '\(compiled\)\|\(\$(OBJEXT)$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
+	sort > $(TOPDIR)/System.map
+
+# This is part of the top-level export target
+
+export_head: board/libboard$(LIBEXT) $(HEAD_OBJ)
+	@if [ -d "$(EXPORT_DIR)/startup" ]; then \
+		cp -f $(HEAD_OBJ) "$(EXPORT_DIR)/startup"; \
+	 else \
+		echo "$(EXPORT_DIR)/startup does not exist"; \
+		exit 1; \
+	 fi
+
+# Dependencies
+
+.depend: Makefile chip/Make.defs $(SRCS)
+	@if [ -e board/Makefile ]; then \
+		$(MAKE) -C board TOPDIR="$(TOPDIR)" depend ; \
+	fi
+	@$(MKDEP) --dep-path chip --dep-path common $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep
+	@touch $@
+
+depend: .depend
+
+clean:
+	@if [ -e board/Makefile ]; then \
+		$(MAKE) -C board TOPDIR="$(TOPDIR)" clean ; \
+	fi
+	@rm -f libarch$(LIBEXT) *~ .*.swp
+	$(call CLEAN)
+
+distclean: clean
+	@if [ -e board/Makefile ]; then \
+		$(MAKE) -C board TOPDIR="$(TOPDIR)" distclean ; \
+	fi
+	@rm -f Make.dep .depend
+
+-include Make.dep

nuttx/arch/sh/src/README.txt

@@ -0,0 +1,7 @@
+This directory provides a build area for all SH architectures.
+The 'common' subdirectory contains source files shared by all SH
+architectures; Source files unique to a specific SH chip
+architecture are contained in a subdirectory named after the chip.
+At configuration time, additional directories will be linked here:
+'build' will be a link to the configs/*/src directory; 'chip' will
+be a link to the SH chip sub-directory.

nuttx/arch/sh/src/common/Kconfig

@@ -0,0 +1,7 @@
+#
+# For a description of the syntax of this configuration file,
+# see misc/tools/kconfig-language.txt.
+#
+
+if ARCH_SH
+endif

nuttx/arch/sh/src/common/README.txt

@@ -0,0 +1,2 @@
+This directory contains source files that are common to all
+SH architectures.

nuttx/arch/sh/src/common/up_allocateheap.c

@@ -0,0 +1,82 @@
+/****************************************************************************
+ * arch/sh/src/common/up_allocateheap.c
+ *
+ *   Copyright (C) 2008 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+
+/****************************************************************************
+ * Private Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_allocate_heap
+ *
+ * Description:
+ *   The heap may be statically allocated by
+ *   defining CONFIG_HEAP_BASE and CONFIG_HEAP_SIZE.  If these
+ *   are not defined, then this function will be called to
+ *   dynamically set aside the heap region.
+ *
+ ****************************************************************************/
+
+void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
+{
+  up_ledon(LED_HEAPALLOCATE);
+  *heap_start = (FAR void*)g_heapbase;
+  *heap_size = CONFIG_DRAM_END - g_heapbase;
+}

nuttx/arch/sh/src/common/up_arch.h

@@ -0,0 +1,70 @@
+/****************************************************************************
+ * arch/sh/src/common/up_arch.h
+ *
+ *   Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_SH_SRC_COMMON_UP_ARCH_H
+#define ___ARCH_SH_SRC_COMMON_UP_ARCH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+#include <arch/board/board.h>
+#include "chip.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+# define getreg8(a)           (*(volatile uint8_t *)(a))
+# define putreg8(v,a)         (*(volatile uint8_t *)(a) = (v))
+# define getreg16(a)          (*(volatile uint16_t *)(a))
+# define putreg16(v,a)        (*(volatile uint16_t *)(a) = (v))
+# define getreg32(a)          (*(volatile uint32_t *)(a))
+# define putreg32(v,a)        (*(volatile uint32_t *)(a) = (v))
+
+#endif
+
+#endif  /* ___ARCH_SH_SRC_COMMON_UP_ARCH_H */

nuttx/arch/sh/src/common/up_assert.c

@@ -0,0 +1,148 @@
+/****************************************************************************
+ * arch/sh/src/common/up_assert.c
+ *
+ *   Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+
+#include "up_arch.h"
+#include "os_internal.h"
+#include "up_internal.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/* Output debug info if stack dump is selected -- even if 
+ * debug is not selected.
+ */
+
+#ifdef CONFIG_ARCH_STACKDUMP
+# undef  lldbg
+# define lldbg lib_lowprintf
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: _up_assert
+ ****************************************************************************/
+
+static void _up_assert(int errorcode) /* __attribute__ ((noreturn)) */
+{
+  /* Are we in an interrupt handler or the idle task? */
+
+  if (current_regs || ((_TCB*)g_readytorun.head)->pid == 0)
+    {
+       (void)irqsave();
+        for(;;)
+          {
+#ifdef CONFIG_ARCH_LEDS
+            up_ledon(LED_PANIC);
+            up_mdelay(250);
+            up_ledoff(LED_PANIC);
+            up_mdelay(250);
+#endif
+          }
+    }
+  else
+    {
+      exit(errorcode);
+    }
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_assert
+ ****************************************************************************/
+
+void up_assert(const uint8_t *filename, int lineno)
+{
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG)
+  _TCB *rtcb = (_TCB*)g_readytorun.head;
+#endif
+
+  up_ledon(LED_ASSERTION);
+#if CONFIG_TASK_NAME_SIZE > 0
+  lldbg("Assertion failed at file:%s line: %d task: %s\n",
+        filename, lineno, rtcb->name);
+#else
+  lldbg("Assertion failed at file:%s line: %d\n",
+        filename, lineno);
+#endif
+  up_dumpstate();
+  _up_assert(EXIT_FAILURE);
+}
+
+/****************************************************************************
+ * Name: up_assert_code
+ ****************************************************************************/
+
+void up_assert_code(const uint8_t *filename, int lineno, int errorcode)
+{
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG)
+  _TCB *rtcb = (_TCB*)g_readytorun.head;
+#endif
+
+  up_ledon(LED_ASSERTION);
+#if CONFIG_TASK_NAME_SIZE > 0
+  lldbg("Assertion failed at file:%s line: %d task: %s error code: %d\n",
+        filename, lineno, rtcb->name, errorcode);
+#else
+  lldbg("Assertion failed at file:%s line: %d error code: %d\n",
+        filename, lineno, errorcode);
+#endif
+  up_dumpstate();
+  _up_assert(errorcode);
+}

nuttx/arch/sh/src/common/up_blocktask.c

@@ -0,0 +1,166 @@
+/****************************************************************************
+ * arch/sh/src/common/up_blocktask.c
+ *
+ *   Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+#include <sched.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+
+#include "os_internal.h"
+#include "up_internal.h"
+
+/****************************************************************************
+ * Private Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_block_task
+ *
+ * Description:
+ *   The currently executing task at the head of
+ *   the ready to run list must be stopped.  Save its context
+ *   and move it to the inactive list specified by task_state.
+ *
+ * Inputs:
+ *   tcb: Refers to a task in the ready-to-run list (normally
+ *     the task at the head of the list).  It most be
+ *     stopped, its context saved and moved into one of the
+ *     waiting task lists.  It it was the task at the head
+ *     of the ready-to-run list, then a context to the new
+ *     ready to run task must be performed.
+ *   task_state: Specifies which waiting task list should be
+ *     hold the blocked task TCB.
+ *
+ ****************************************************************************/
+
+void up_block_task(_TCB *tcb, tstate_t task_state)
+{
+  /* Verify that the context switch can be performed */
+
+  if ((tcb->task_state < FIRST_READY_TO_RUN_STATE) ||
+      (tcb->task_state > LAST_READY_TO_RUN_STATE))
+    {
+      PANIC(OSERR_BADBLOCKSTATE);
+    }
+  else
+    {
+      _TCB *rtcb = (_TCB*)g_readytorun.head;
+      bool switch_needed;
+
+      /* Remove the tcb task from the ready-to-run list.  If we
+       * are blocking the task at the head of the task list (the
+       * most likely case), then a context switch to the next
+       * ready-to-run task is needed. In this case, it should
+       * also be true that rtcb == tcb.
+       */
+
+      switch_needed = sched_removereadytorun(tcb);
+
+      /* Add the task to the specified blocked task list */
+
+      sched_addblocked(tcb, (tstate_t)task_state);
+
+      /* If there are any pending tasks, then add them to the g_readytorun
+       * task list now
+       */
+
+      if (g_pendingtasks.head)
+        {
+          switch_needed |= sched_mergepending();
+        }
+
+      /* Now, perform the context switch if one is needed */
+
+      if (switch_needed)
+        {
+          /* Are we in an interrupt handler? */
+
+          if (current_regs)
+            {
+              /* Yes, then we have to do things differently.
+               * Just copy the current_regs into the OLD rtcb.
+               */
+
+               up_copystate(rtcb->xcp.regs, current_regs);
+
+              /* Restore the exception context of the rtcb at the (new) head 
+               * of the g_readytorun task list.
+               */
+
+              rtcb = (_TCB*)g_readytorun.head;
+
+              /* Then switch contexts */
+
+              current_regs = rtcb->xcp.regs;
+            }
+
+          /* Copy the user C context into the TCB at the (old) head of the
+           * g_readytorun Task list. if up_saveusercontext returns a non-zero
+           * value, then this is really the previously running task restarting!
+           */
+
+          else if (!up_saveusercontext(rtcb->xcp.regs))
+            {
+              /* Restore the exception context of the rtcb at the (new) head 
+               * of the g_readytorun task list.
+               */
+
+              rtcb = (_TCB*)g_readytorun.head;
+
+              /* Then switch contexts */
+
+              up_fullcontextrestore(rtcb->xcp.regs);
+            }
+        }
+    }
+}

nuttx/arch/sh/src/common/up_createstack.c

@@ -0,0 +1,132 @@
+/****************************************************************************
+ * arch/sh/src/common/up_createstack.c
+ *
+ *   Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <sched.h>
+#include <debug.h>
+
+#include <nuttx/kmalloc.h>
+#include <nuttx/arch.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Global Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_create_stack
+ *
+ * Description:
+ *   Allocate a stack for a new thread and setup
+ *   up stack-related information in the TCB.
+ *
+ *   The following TCB fields must be initialized:
+ *   adj_stack_size: Stack size after adjustment for hardware,
+ *     processor, etc.  This value is retained only for debug
+ *     purposes.
+ *   stack_alloc_ptr: Pointer to allocated stack
+ *   adj_stack_ptr: Adjusted stack_alloc_ptr for HW.  The
+ *     initial value of the stack pointer.
+ *
+ * Inputs:
+ *   tcb: The TCB of new task
+ *   stack_size:  The requested stack size.  At least this much
+ *     must be allocated.
+ ****************************************************************************/
+
+int up_create_stack(_TCB *tcb, size_t stack_size)
+{
+  if (tcb->stack_alloc_ptr &&
+      tcb->adj_stack_size != stack_size)
+    {
+      sched_free(tcb->stack_alloc_ptr);
+      tcb->stack_alloc_ptr = NULL;
+    }
+
+   if (!tcb->stack_alloc_ptr)
+     {
+       tcb->stack_alloc_ptr = (uint32_t*)kzalloc(stack_size);
+     }
+
+   if (tcb->stack_alloc_ptr)
+     {
+       size_t top_of_stack;
+       size_t size_of_stack;
+
+       /* The Arm7Tdmi uses a push-down stack:  the stack grows
+	* toward loweraddresses in memory.  The stack pointer
+	* register, points to the lowest, valid work address
+	* (the "top" of the stack).  Items on the stack are
+	* referenced as positive word offsets from sp.
+	*/
+
+       top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4;
+
+       /* The Arm7Tdmi stack must be aligned at word (4 byte)
+	* boundaries. If necessary top_of_stack must be rounded
+	* down to the next boundary
+	*/
+
+       top_of_stack &= ~3;
+       size_of_stack = top_of_stack - (uint32_t)tcb->stack_alloc_ptr + 4;
+
+       /* Save the adjusted stack values in the _TCB */
+
+       tcb->adj_stack_ptr  = (uint32_t*)top_of_stack;
+       tcb->adj_stack_size = size_of_stack;
+
+       up_ledon(LED_STACKCREATED);
+       return OK;
+     }
+
+   return ERROR;
+}

nuttx/arch/sh/src/common/up_doirq.c

@@ -0,0 +1,124 @@
+/****************************************************************************
+ * arch/sh/src/common/up_doirq.c
+ *
+ *   Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <assert.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+
+#include "up_arch.h"
+#include "os_internal.h"
+#include "up_internal.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+uint32_t *up_doirq(int irq, uint32_t* regs)
+{
+  up_ledon(LED_INIRQ);
+#ifdef CONFIG_SUPPRESS_INTERRUPTS
+  PANIC(OSERR_ERREXCEPTION);
+#else
+  if ((unsigned)irq < NR_IRQS)
+    {
+       uint32_t *savestate;
+
+       /* Current regs non-zero indicates that we are processing
+        * an interrupt; current_regs is also used to manage
+        * interrupt level context switches.
+        */
+
+       savestate    = (uint32_t*)current_regs;
+       current_regs = regs;
+
+       /* Mask and acknowledge the interrupt (if supported by the chip) */
+
+#ifndef CONFIG_ARCH_NOINTC
+       up_maskack_irq(irq);
+#endif
+
+       /* Deliver the IRQ */
+
+       irq_dispatch(irq, regs);
+
+       /* Get the current value of regs... it may have changed because
+        * of a context switch performed during interrupt processing.
+        */
+
+       regs = current_regs;
+
+       /* Restore the previous value of current_regs.  NULL would indicate that
+        * we are no longer in an interrupt handler.  It will be non-NULL if we
+        * are returning from a nested interrupt.
+        */
+
+       current_regs = savestate;
+
+       /* Unmask the last interrupt (global interrupts are still
+        * disabled.
+        */
+
+#ifndef CONFIG_ARCH_NOINTC
+       up_enable_irq(irq);
+#endif
+    }
+  up_ledoff(LED_INIRQ);
+#endif
+  return regs;
+}

nuttx/arch/sh/src/common/up_exit.c

@@ -0,0 +1,174 @@
+/****************************************************************************
+ * common/up_exit.c
+ *
+ *   Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sched.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+
+#include "os_internal.h"
+#include "up_internal.h"
+
+#ifdef CONFIG_DUMP_ON_EXIT
+#include <nuttx/fs/fs.h>
+#endif
+
+/****************************************************************************
+ * Private Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: _up_dumponexit
+ *
+ * Description:
+ *   Dump the state of all tasks whenever on task exits.  This is debug
+ *   instrumentation that was added to check file-related reference counting
+ *   but could be useful again sometime in the future.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG)
+static void _up_dumponexit(FAR _TCB *tcb, FAR void *arg)
+{
+#if CONFIG_NFILE_DESCRIPTORS > 0 || CONFIG_NFILE_STREAMS > 0
+  int i;
+#endif
+
+  sdbg("  TCB=%p name=%s\n", tcb, tcb->argv[0]);
+
+#if CONFIG_NFILE_DESCRIPTORS > 0
+  if (tcb->filelist)
+    {
+      sdbg("    filelist refcount=%d\n",
+           tcb->filelist->fl_crefs);
+
+      for (i = 0; i < CONFIG_NFILE_DESCRIPTORS; i++)
+        {
+          struct inode *inode = tcb->filelist->fl_files[i].f_inode;
+          if (inode)
+            {
+              sdbg("      fd=%d refcount=%d\n",
+                   i, inode->i_crefs);
+            }
+        }
+    }
+#endif
+
+#if CONFIG_NFILE_STREAMS > 0
+  if (tcb->streams)
+    {
+      sdbg("    streamlist refcount=%d\n",
+           tcb->streams->sl_crefs);
+
+      for (i = 0; i < CONFIG_NFILE_STREAMS; i++)
+        {
+          struct file_struct *filep = &tcb->streams->sl_streams[i];
+          if (filep->fs_filedes >= 0)
+            {
+#if CONFIG_STDIO_BUFFER_SIZE > 0
+              sdbg("      fd=%d nbytes=%d\n",
+                   filep->fs_filedes,
+                  filep->fs_bufpos - filep->fs_bufstart);
+#else
+              sdbg("      fd=%d\n", filep->fs_filedes);
+#endif
+            }
+        }
+    }
+#endif
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: _exit
+ *
+ * Description:
+ *   This function causes the currently executing task to cease
+ *   to exist.  This is a special case of task_delete() where the task to
+ *   be deleted is the currently executing task.  It is more complex because
+ *   a context switch must be perform to the next ready to run task.
+ *
+ ****************************************************************************/
+
+void _exit(int status)
+{
+  _TCB* tcb;
+
+  /* Disable interrupts.  They will be restored when the next
+   * task is started.
+   */
+
+  (void)irqsave();
+
+  slldbg("TCB=%p exitting\n", g_readytorun.head);
+
+#if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG)
+  slldbg("Other tasks:\n");
+  sched_foreach(_up_dumponexit, NULL);
+#endif
+
+  /* Destroy the task at the head of the ready to run list. */
+
+  (void)task_deletecurrent();
+
+  /* Now, perform the context switch to the new ready-to-run task at the
+   * head of the list.
+   */
+
+  tcb = (_TCB*)g_readytorun.head;
+
+  /* Then switch contexts */
+
+  up_fullcontextrestore(tcb->xcp.regs);
+}
+

nuttx/arch/sh/src/common/up_idle.c

@@ -0,0 +1,87 @@
+/****************************************************************************
+ *  arch/sh/src/common/up_idle.c
+ *
+ *   Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+
+#include "up_internal.h"
+
+/****************************************************************************
+ * Private Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_idle
+ *
+ * Description:
+ *   up_idle() is the logic that will be executed when their
+ *   is no other ready-to-run task.  This is processor idle
+ *   time and will continue until some interrupt occurs to
+ *   cause a context switch from the idle task.
+ *
+ *   Processing in this state may be processor-specific. e.g.,
+ *   this is where power management operations might be
+ *   performed.
+ *
+ ****************************************************************************/
+
+void up_idle(void)
+{
+#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
+  /* If the system is idle and there are no timer interrupts,
+   * then process "fake" timer interrupts. Hopefully, something
+   * will wake up.
+   */
+
+  sched_process_timer();
+#endif
+}
+

nuttx/arch/sh/src/common/up_initialize.c

@@ -0,0 +1,172 @@
+/****************************************************************************
+ * arch/sh/src/common/up_initialize.c
+ *
+ *   Copyright (C) 2008-2010, 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/fs/fs.h>
+#include <nuttx/ramlog.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/* Define to enable timing loop calibration */
+
+#undef CONFIG_ARCH_CALIBRATION
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_calibratedelay
+ *
+ * Description:
+ *   Delay loops are provided for short timing loops.  This function, if
+ *   enabled, will just wait for 100 seconds.  Using a stopwatch, you can
+ *   can then determine if the timing loops are properly calibrated.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_ARCH_CALIBRATION) & defined(CONFIG_DEBUG)
+static void up_calibratedelay(void)
+{
+  int i;
+  slldbg("Beginning 100s delay\n");
+  for (i = 0; i < 100; i++)
+    {
+      up_mdelay(1000);
+    }
+  slldbg("End 100s delay\n");
+}
+#else
+# define up_calibratedelay()
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_initialize
+ *
+ * Description:
+ *   up_initialize will be called once during OS initialization after the
+ *   basic OS services have been initialized.  The architecture specific
+ *   details of initializing the OS will be handled here.  Such things as
+ *   setting up interrupt service routines, starting the clock, and
+ *   registering device drivers are some of the things that are different
+ *   for each processor and hardware platform.
+ *
+ *   up_initialize is called after the OS initialized but before the user
+ *   initialization logic has been started and before the libraries have
+ *   been initialized.  OS services and driver services are available.
+ *
+ ****************************************************************************/
+
+void up_initialize(void)
+{
+  /* Initialize global variables */
+
+  current_regs = NULL;
+
+  /* Calibrate the timing loop */
+
+  up_calibratedelay();
+
+  /* Initialize the interrupt subsystem */
+
+  up_irqinitialize();
+
+  /* Initialize the system timer interrupt */
+
+#if !defined(CONFIG_SUPPRESS_INTERRUPTS) && !defined(CONFIG_SUPPRESS_TIMER_INTS)
+  up_timerinit();
+#endif
+
+  /* Register devices */
+
+#if CONFIG_NFILE_DESCRIPTORS > 0
+  devnull_register();   /* Standard /dev/null */
+#endif
+
+  /* Initialize the console device driver.  NOTE that the naming
+   * implies that the console is a serial driver.  That is usually the case,
+   * however, if no UARTs are enabled, the console could als be provided
+   * through some other device, such as an LCD.  Architecture-specific logic
+   * will have to detect that case.
+   */
+
+#if defined(USE_SERIALDRIVER)
+  up_consoleinit();
+#elif defined(CONFIG_DEV_LOWCONSOLE)
+  lowconsole_init();
+#elif defined(CONFIG_RAMLOG_CONSOLE)
+  ramlog_consoleinit();
+#endif
+
+  /* Initialize the system logging device */
+
+#ifdef CONFIG_SYSLOG_CHAR
+  syslog_initialize();
+#endif
+#ifdef CONFIG_RAMLOG_SYSLOG
+  ramlog_sysloginit();
+#endif
+
+  /* Initialize the netwok */
+
+  up_netinitialize();
+
+  /* Initialize USB */
+
+  up_usbinitialize();
+
+  up_ledon(LED_IRQSENABLED);
+}

nuttx/arch/sh/src/common/up_internal.h

@@ -0,0 +1,253 @@
+/****************************************************************************
+ * arch/sh/src/common/up_internal.h
+ *
+ *   Copyright (C) 2008-2009, 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef ___ARCH_SH_SRC_COMMON_UP_INTERNAL_H
+#define ___ARCH_SH_SRC_COMMON_UP_INTERNAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#  include <stdint.h>
+#endif
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/* Bring-up debug configurations.  These are here (vs defconfig)
+ * because these should only be controlled during low level
+ * board bring-up and not part of normal platform configuration.
+ */
+
+#undef  CONFIG_SUPPRESS_INTERRUPTS    /* DEFINED: Do not enable interrupts */
+#undef  CONFIG_SUPPRESS_TIMER_INTS    /* DEFINED: No timer */
+#undef  CONFIG_SUPPRESS_SERIAL_INTS   /* DEFINED: Console will poll */
+#undef  CONFIG_SUPPRESS_SCI_CONFIG    /* DEFINED: Do not reconfig SCI */
+#undef  CONFIG_DUMP_ON_EXIT           /* DEFINED: Dump task state on exit */
+
+/* Determine which (if any) console driver to use.  NOTE that the naming
+ * implies that the console is a serial driver.  That is usually the case,
+ * however, if no UARTs are enabled, the console could als be provided
+ * through some other device, such as an LCD.  Architecture-specific logic
+ * will have to detect that case.
+ */
+
+#if !defined(CONFIG_DEV_CONSOLE) || CONFIG_NFILE_DESCRIPTORS <= 0
+#  undef  USE_SERIALDRIVER
+#  undef  USE_EARLYSERIALINIT
+#  undef  CONFIG_DEV_LOWCONSOLE
+#  undef  CONFIG_RAMLOG_CONSOLE
+#else
+#  if defined(CONFIG_RAMLOG_CONSOLE)
+#    undef  USE_SERIALDRIVER
+#    undef  USE_EARLYSERIALINIT
+#    undef  CONFIG_DEV_LOWCONSOLE
+#  elif defined(CONFIG_DEV_LOWCONSOLE)
+#    undef  USE_SERIALDRIVER
+#    undef  USE_EARLYSERIALINIT
+#  else
+#    define USE_SERIALDRIVER 1
+#    define USE_EARLYSERIALINIT 1
+#  endif
+#endif
+
+/* Determine which device to use as the system logging device */
+
+#ifndef CONFIG_SYSLOG
+#  undef CONFIG_SYSLOG_CHAR
+#  undef CONFIG_RAMLOG_SYSLOG
+#endif
+
+/* Check if an interrupt stack size is configured */
+
+#ifndef CONFIG_ARCH_INTERRUPTSTACK
+# define CONFIG_ARCH_INTERRUPTSTACK 0
+#endif
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*up_vector_t)(void);
+#endif
+
+/****************************************************************************
+ * Public Variables
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+/* This holds a references to the current interrupt level
+ * register storage structure.  If is non-NULL only during
+ * interrupt processing.
+ */
+
+extern volatile uint32_t *current_regs;
+
+/* This is the beginning of heap as provided from up_head.S.
+ * This is the first address in DRAM after the loaded
+ * program+bss+idle stack.  The end of the heap is
+ * CONFIG_DRAM_END
+ */
+
+extern uint32_t g_heapbase;
+#endif
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* Defined in files with the same name as the function */
+
+extern void up_boot(void);
+extern void up_copystate(uint32_t *dest, uint32_t *src);
+extern void up_dataabort(uint32_t *regs);
+extern void up_decodeirq(uint32_t *regs);
+extern uint32_t *up_doirq(int irq, uint32_t *regs);
+extern void up_fullcontextrestore(uint32_t *regs) __attribute__ ((noreturn));
+extern void up_irqinitialize(void);
+extern void up_prefetchabort(uint32_t *regs);
+extern int  up_saveusercontext(uint32_t *regs);
+extern void up_sigdeliver(void);
+extern void up_syscall(uint32_t *regs);
+extern int  up_timerisr(int irq, uint32_t *regs);
+extern void up_undefinedinsn(uint32_t *regs);
+extern void up_lowputc(char ch);
+extern void up_puts(const char *str);
+extern void up_lowputs(const char *str);
+
+/* Defined in up_vectors.S */
+
+extern void up_vectorundefinsn(void);
+extern void up_vectorswi(void);
+extern void up_vectorprefetch(void);
+extern void up_vectordata(void);
+extern void up_vectoraddrexcptn(void);
+extern void up_vectorirq(void);
+extern void up_vectorfiq(void);
+
+/* Defined in up_serial.c */
+
+#if CONFIG_NFILE_DESCRIPTORS > 0
+extern void up_earlyconsoleinit(void);
+extern void up_consoleinit(void);
+#else
+# define up_earlyconsoleinit()
+# define up_consoleinit()
+#endif
+
+/* Defined in drivers/lowconsole.c */
+
+#ifdef CONFIG_DEV_LOWCONSOLE
+extern void lowconsole_init(void);
+#else
+# define lowconsole_init()
+#endif
+
+/* Defined in up_watchdog.c */
+
+extern void up_wdtinit(void);
+
+/* Defined in up_timerisr.c */
+
+extern void up_timerinit(void);
+
+/* Defined in chip-specific logic if CONFIG_ARCH_NOINTC is not set */
+
+#ifndef CONFIG_ARCH_NOINTC
+extern void up_maskack_irq(int irq);
+#else
+#  define up_maskack_irq(irq)
+#endif
+
+/* Defined in board/up_leds.c */
+
+#ifdef CONFIG_ARCH_LEDS
+extern void up_ledinit(void);
+extern void up_ledon(int led);
+extern void up_ledoff(int led);
+#else
+# define up_ledinit()
+# define up_ledon(led)
+# define up_ledoff(led)
+#endif
+
+/* Defined in board/up_lcd.c */
+
+#ifdef CONFIG_ARCH_LCD
+extern void up_lcdinit(void);
+extern void up_lcdputc(char ch);
+#else
+# define up_lcdinit()
+# define up_lcdputc(ch)
+#endif
+
+/* Defined in board/up_network.c */
+
+#ifdef CONFIG_NET
+extern void up_netinitialize(void);
+#else
+# define up_netinitialize()
+#endif
+
+/* USB */
+
+#ifdef CONFIG_USBDEV
+extern void up_usbinitialize(void);
+extern void up_usbuninitialize(void);
+#else
+# define up_usbinitialize()
+# define up_usbuninitialize()
+#endif
+
+/* Defined in chip-specific logic */
+
+#ifdef CONFIG_ARCH_STACKDUMP
+extern void up_dumpstate(void);
+#else
+#  define up_dumpstate()
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif  /* ___ARCH_SH_SRC_COMMON_UP_INTERNAL_H */

nuttx/arch/sh/src/common/up_interruptcontext.c

@@ -0,0 +1,70 @@
+/****************************************************************************
+ *  arch/sh/src/common/up_interruptcontext.c
+ *
+ *   Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include "up_internal.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Global Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_interrupt_context
+ *
+ * Description: Return true is we are currently executing in
+ * the interrupt handler context.
+ ****************************************************************************/
+
+bool up_interrupt_context(void)
+{
+   return current_regs != NULL;
+}

nuttx/arch/sh/src/common/up_lowputs.c

@@ -0,0 +1,74 @@
+/****************************************************************************
+ * arch/sh/src/common/up_lowputs.c
+ *
+ *   Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "up_internal.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_lowputs
+ *
+ * Description:
+ *   This is a low-level helper function used to support debug.
+ *
+ ****************************************************************************/
+
+void up_lowputs(const char *str)
+{
+  while(*str)
+    {
+      up_lowputc(*str++);
+    }
+}

nuttx/arch/sh/src/common/up_mdelay.c

@@ -0,0 +1,90 @@
+/****************************************************************************
+ *  arch/sh/src/common/up_mdelay.c
+ *
+ *   Copyright (C) 2008 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_mdelay
+ *
+ * Description:
+ *   Delay inline for the requested number of milliseconds.
+ *   *** NOT multi-tasking friendly ***
+ *
+ * ASSUMPTIONS:
+ *   The setting CONFIG_BOARD_LOOPSPERMSEC has been calibrated
+ *
+ ****************************************************************************/
+
+void up_mdelay(unsigned int milliseconds)
+{
+  volatile int i;
+  volatile int j;
+
+  for (i = 0; i < milliseconds; i++)
+    {
+        for (j = 0; j < CONFIG_BOARD_LOOPSPERMSEC; j++)
+          {
+          }
+    }
+}

nuttx/arch/sh/src/common/up_puts.c

@@ -0,0 +1,75 @@
+/****************************************************************************
+ * arch/sh/src/common/up_puts.c
+ *
+ *   Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+
+#include "up_internal.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_puts
+ *
+ * Description:
+ *   This is a low-level helper function used to support debug.
+ *
+ ****************************************************************************/
+
+void up_puts(const char *str)
+{
+  while(*str)
+    {
+      up_putc(*str++);
+    }
+}

nuttx/arch/sh/src/common/up_releasepending.c

@@ -0,0 +1,132 @@
+/****************************************************************************
+ *  arch/sh/src/common/up_releasepending.c
+ *
+ *   Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sched.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+
+#include "os_internal.h"
+#include "up_internal.h"
+
+/****************************************************************************
+ * Private Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_release_pending
+ *
+ * Description:
+ *   Release and ready-to-run tasks that have
+ *   collected in the pending task list.  This can call a
+ *   context switch if a new task is placed at the head of
+ *   the ready to run list.
+ *
+ ****************************************************************************/
+
+void up_release_pending(void)
+{
+  _TCB *rtcb = (_TCB*)g_readytorun.head;
+
+  slldbg("From TCB=%p\n", rtcb);
+
+  /* Merge the g_pendingtasks list into the g_readytorun task list */
+
+  /* sched_lock(); */
+  if (sched_mergepending())
+    {
+      /* The currently active task has changed!  We will need to
+       * switch contexts.  First check if we are operating in
+       * interrupt context:
+       */
+
+      if (current_regs)
+        {
+          /* Yes, then we have to do things differently.
+           * Just copy the current_regs into the OLD rtcb.
+           */
+
+           up_copystate(rtcb->xcp.regs, current_regs);
+
+          /* Restore the exception context of the rtcb at the (new) head 
+           * of the g_readytorun task list.
+           */
+
+          rtcb = (_TCB*)g_readytorun.head;
+          slldbg("New Active Task TCB=%p\n", rtcb);
+
+          /* Then switch contexts */
+
+          current_regs = rtcb->xcp.regs;
+        }
+
+      /* Copy the exception context into the TCB of the task that
+       * was currently active. if up_saveusercontext returns a non-zero
+       * value, then this is really the previously running task 
+       * restarting!
+       */
+
+      else if (!up_saveusercontext(rtcb->xcp.regs))
+        {
+          /* Restore the exception context of the rtcb at the (new) head 
+           * of the g_readytorun task list.
+           */
+
+          rtcb = (_TCB*)g_readytorun.head;
+          slldbg("New Active Task TCB=%p\n", rtcb);
+
+           /* Then switch contexts */
+
+          up_fullcontextrestore(rtcb->xcp.regs);
+        }
+    }
+}

nuttx/arch/sh/src/common/up_releasestack.c

@@ -0,0 +1,79 @@
+/****************************************************************************
+ *  arch/sh/src/common/up_releasestack.c
+ *
+ *   Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sched.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+
+#include "os_internal.h"
+#include "up_internal.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Global Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_release_stack
+ *
+ * Description:
+ *   A task has been stopped. Free all stack
+ *   related resources retained int the defunct TCB.
+ *
+ ****************************************************************************/
+
+void up_release_stack(_TCB *dtcb)
+{
+  if (dtcb->stack_alloc_ptr)
+    {
+      sched_free(dtcb->stack_alloc_ptr);
+      dtcb->stack_alloc_ptr = NULL;
+    }
+
+  dtcb->adj_stack_size = 0;
+}

nuttx/arch/sh/src/common/up_reprioritizertr.c

@@ -0,0 +1,182 @@
+/****************************************************************************
+ *  arch/sh/src/common/up_reprioritizertr.c
+ *
+ *   Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <sched.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+
+#include "os_internal.h"
+#include "up_internal.h"
+
+/****************************************************************************
+ * Private Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_reprioritize_rtr
+ *
+ * Description:
+ *   Called when the priority of a running or
+ *   ready-to-run task changes and the reprioritization will 
+ *   cause a context switch.  Two cases:
+ *
+ *   1) The priority of the currently running task drops and the next
+ *      task in the ready to run list has priority.
+ *   2) An idle, ready to run task's priority has been raised above the
+ *      the priority of the current, running task and it now has the
+ *      priority.
+ *
+ * Inputs:
+ *   tcb: The TCB of the task that has been reprioritized
+ *   priority: The new task priority
+ *
+ ****************************************************************************/
+
+void up_reprioritize_rtr(_TCB *tcb, uint8_t priority)
+{
+  /* Verify that the caller is sane */
+
+  if (tcb->task_state < FIRST_READY_TO_RUN_STATE ||
+      tcb->task_state > LAST_READY_TO_RUN_STATE ||
+      priority < SCHED_PRIORITY_MIN || 
+      priority > SCHED_PRIORITY_MAX)
+    {
+       PANIC(OSERR_BADREPRIORITIZESTATE);
+    }
+  else
+    {
+      _TCB *rtcb = (_TCB*)g_readytorun.head;
+      bool switch_needed;
+
+      slldbg("TCB=%p PRI=%d\n", tcb, priority);
+
+      /* Remove the tcb task from the ready-to-run list.
+       * sched_removereadytorun will return true if we just
+       * remove the head of the ready to run list.
+       */
+
+      switch_needed = sched_removereadytorun(tcb);
+
+      /* Setup up the new task priority */
+
+      tcb->sched_priority = (uint8_t)priority;
+
+      /* Return the task to the specified blocked task list.
+       * sched_addreadytorun will return true if the task was
+       * added to the new list.  We will need to perform a context
+       * switch only if the EXCLUSIVE or of the two calls is non-zero
+       * (i.e., one and only one the calls changes the head of the
+       * ready-to-run list).
+       */
+
+      switch_needed ^= sched_addreadytorun(tcb);
+
+      /* Now, perform the context switch if one is needed */
+
+      if (switch_needed)
+        {
+          /* If we are going to do a context switch, then now is the right
+           * time to add any pending tasks back into the ready-to-run list.
+           * task list now
+           */
+
+          if (g_pendingtasks.head)
+            {
+              sched_mergepending();
+            }
+
+         /* Are we in an interrupt handler? */
+
+          if (current_regs)
+            {
+              /* Yes, then we have to do things differently.
+               * Just copy the current_regs into the OLD rtcb.
+               */
+
+               up_copystate(rtcb->xcp.regs, current_regs);
+
+              /* Restore the exception context of the rtcb at the (new) head 
+               * of the g_readytorun task list.
+               */
+
+              rtcb = (_TCB*)g_readytorun.head;
+              slldbg("New Active Task TCB=%p\n", rtcb);
+
+              /* Then switch contexts */
+
+              current_regs = rtcb->xcp.regs;
+            }
+
+          /* Copy the exception context into the TCB at the (old) head of the
+           * g_readytorun Task list. if up_saveusercontext returns a non-zero
+           * value, then this is really the previously running task restarting!
+           */
+
+          else if (!up_saveusercontext(rtcb->xcp.regs))
+            {
+              /* Restore the exception context of the rtcb at the (new) head 
+               * of the g_readytorun task list.
+               */
+
+              rtcb = (_TCB*)g_readytorun.head;
+              slldbg("New Active Task TCB=%p\n", rtcb);
+
+              /* Then switch contexts */
+
+              up_fullcontextrestore(rtcb->xcp.regs);
+            }
+        }
+    }
+}

nuttx/arch/sh/src/common/up_udelay.c

@@ -0,0 +1,129 @@
+/****************************************************************************
+ *  arch/sh/src/common/up_udelay.c
+ *
+ *   Copyright (C) 2008 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <nuttx/arch.h>
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+#define CONFIG_BOARD_LOOPSPER100USEC ((CONFIG_BOARD_LOOPSPERMSEC+5)/10)
+#define CONFIG_BOARD_LOOPSPER10USEC  ((CONFIG_BOARD_LOOPSPERMSEC+50)/100)
+#define CONFIG_BOARD_LOOPSPERUSEC    ((CONFIG_BOARD_LOOPSPERMSEC+500)/1000)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_udelay
+ *
+ * Description:
+ *   Delay inline for the requested number of microseconds.  NOTE:  Because
+ *   of all of the setup, several microseconds will be lost before the actual
+ *   timing looop begins.  Thus, the delay will always be a few microseconds
+ *   longer than requested.
+ *
+ *   *** NOT multi-tasking friendly ***
+ *
+ * ASSUMPTIONS:
+ *   The setting CONFIG_BOARD_LOOPSPERMSEC has been calibrated
+ *
+ ****************************************************************************/
+
+void up_udelay(useconds_t microseconds)
+{
+  volatile int i;
+
+  /* We'll do this a little at a time because we expect that the
+   * CONFIG_BOARD_LOOPSPERUSEC is very inaccurate during to truncation in
+   * the divisions of its calculation.  We'll use the largest values that
+   * we can in order to prevent significant error buildup in the loops.
+   */
+
+  while (microseconds > 1000)
+    {
+      for (i = 0; i < CONFIG_BOARD_LOOPSPERMSEC; i++)
+        {
+        }
+      microseconds -= 1000;
+    }
+
+  while (microseconds > 100)
+    {
+      for (i = 0; i < CONFIG_BOARD_LOOPSPER100USEC; i++)
+        {
+        }
+      microseconds -= 100;
+    }
+
+  while (microseconds > 10)
+    {
+      for (i = 0; i < CONFIG_BOARD_LOOPSPER10USEC; i++)
+        {
+        }
+      microseconds -= 10;
+    }
+
+  while (microseconds > 0)
+    {
+      for (i = 0; i < CONFIG_BOARD_LOOPSPERUSEC; i++)
+        {
+        }
+      microseconds--;
+    }
+}

nuttx/arch/sh/src/common/up_unblocktask.c

@@ -0,0 +1,159 @@
+/****************************************************************************
+ *  arch/sh/src/common/up_unblocktask.c
+ *
+ *   Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sched.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+
+#include "os_internal.h"
+#include "clock_internal.h"
+#include "up_internal.h"
+
+/****************************************************************************
+ * Private Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_unblock_task
+ *
+ * Description:
+ *   A task is currently in an inactive task list
+ *   but has been prepped to execute.  Move the TCB to the
+ *   ready-to-run list, restore its context, and start execution.
+ *
+ * Inputs:
+ *   tcb: Refers to the tcb to be unblocked.  This tcb is
+ *     in one of the waiting tasks lists.  It must be moved to
+ *     the ready-to-run list and, if it is the highest priority
+ *     ready to run taks, executed.
+ *
+ ****************************************************************************/
+
+void up_unblock_task(_TCB *tcb)
+{
+  /* Verify that the context switch can be performed */
+
+  if ((tcb->task_state < FIRST_BLOCKED_STATE) ||
+      (tcb->task_state > LAST_BLOCKED_STATE))
+    {
+      PANIC(OSERR_BADUNBLOCKSTATE);
+    }
+  else
+    {
+      _TCB *rtcb = (_TCB*)g_readytorun.head;
+
+      /* Remove the task from the blocked task list */
+
+      sched_removeblocked(tcb);
+
+      /* Reset its timeslice.  This is only meaningful for round
+       * robin tasks but it doesn't here to do it for everything
+       */
+
+#if CONFIG_RR_INTERVAL > 0
+      tcb->timeslice = CONFIG_RR_INTERVAL / MSEC_PER_TICK;
+#endif
+
+      /* Add the task in the correct location in the prioritized
+       * g_readytorun task list
+       */
+
+      if (sched_addreadytorun(tcb))
+        {
+          /* The currently active task has changed! We need to do
+           * a context switch to the new task.
+           *
+           * Are we in an interrupt handler? 
+           */
+
+          if (current_regs)
+            {
+              /* Yes, then we have to do things differently.
+               * Just copy the current_regs into the OLD rtcb.
+               */
+
+               up_copystate(rtcb->xcp.regs, current_regs);
+
+              /* Restore the exception context of the rtcb at the (new) head 
+               * of the g_readytorun task list.
+               */
+
+              rtcb = (_TCB*)g_readytorun.head;
+
+              /* Then switch contexts */
+
+              current_regs = rtcb->xcp.regs;
+            }
+
+          /* We are not in an interrupt handler.  Copy the user C context
+           * into the TCB of the task that was previously active.  if 
+           * up_saveusercontext returns a non-zero value, then this is really the
+           * previously running task restarting!
+           */
+
+          else if (!up_saveusercontext(rtcb->xcp.regs))
+            {
+              /* Restore the exception context of the new task that is ready to
+               * run (probably tcb).  This is the new rtcb at the head of the
+               * g_readytorun task list.
+               */
+
+              rtcb = (_TCB*)g_readytorun.head;
+
+              /* Then switch contexts */
+
+              up_fullcontextrestore(rtcb->xcp.regs);
+            }
+        }
+    }
+}

nuttx/arch/sh/src/common/up_usestack.c

@@ -0,0 +1,122 @@
+/****************************************************************************
+ * arch/sh/src/common/up_usestack.c
+ *
+ *   Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <sched.h>
+#include <debug.h>
+
+#include <nuttx/kmalloc.h>
+#include <nuttx/arch.h>
+
+#include "up_internal.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Global Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_use_stack
+ *
+ * Description:
+ *   Setup up stack-related information in the TCB
+ *   using pre-allocated stack memory
+ *
+ *   The following TCB fields must be initialized:
+ *   adj_stack_size: Stack size after adjustment for hardware,
+ *     processor, etc.  This value is retained only for debug
+ *     purposes.
+ *   stack_alloc_ptr: Pointer to allocated stack
+ *   adj_stack_ptr: Adjusted stack_alloc_ptr for HW.  The
+ *     initial value of the stack pointer.
+ *
+ * Inputs:
+ *   tcb: The TCB of new task
+ *   stack_size:  The allocated stack size.
+ *
+ ****************************************************************************/
+
+int up_use_stack(_TCB *tcb, void *stack, size_t stack_size)
+{
+  size_t top_of_stack;
+  size_t size_of_stack;
+
+  if (tcb->stack_alloc_ptr)
+    {
+      sched_free(tcb->stack_alloc_ptr);
+    }
+
+  /* Save the stack allocation */
+
+  tcb->stack_alloc_ptr = stack;
+
+  /* The Arm7Tdmi uses a push-down stack:  the stack grows
+   * toward loweraddresses in memory.  The stack pointer
+   * register, points to the lowest, valid work address
+   * (the "top" of the stack).  Items on the stack are
+   * referenced as positive word offsets from sp.
+   */
+
+  top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4;
+
+  /* The Arm7Tdmi stack must be aligned at word (4 byte)
+   * boundaries. If necessary top_of_stack must be rounded
+   * down to the next boundary
+   */
+
+  top_of_stack &= ~3;
+  size_of_stack = top_of_stack - (uint32_t)tcb->stack_alloc_ptr + 4;
+
+  /* Save the adjusted stack values in the _TCB */
+
+  tcb->adj_stack_size = top_of_stack;
+  tcb->adj_stack_size = size_of_stack;
+
+  return OK;
+}

nuttx/arch/sh/src/m16c/Kconfig

@@ -0,0 +1,9 @@
+#
+# For a description of the syntax of this configuration file,
+# see misc/tools/kconfig-language.txt.
+#
+
+if ARCH_M16C
+comment "M16C Configuration Options"
+
+endif

nuttx/arch/sh/src/m16c/Make.defs

@@ -0,0 +1,53 @@
+##############################################################################
+# arch/sh/src/m16c/Make.defs
+#
+#   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+##############################################################################
+
+HEAD_ASRC	= m16c_head.S
+
+CMN_ASRCS	= 
+CMN_CSRCS	= up_allocateheap.c up_assert.c up_blocktask.c \
+		  up_createstack.c up_doirq.c up_exit.c up_idle.c up_initialize.c \
+		  up_interruptcontext.c up_lowputs.c up_mdelay.c up_puts.c \
+		  up_releasepending.c up_releasestack.c up_reprioritizertr.c \
+		  up_udelay.c up_unblocktask.c up_usestack.c
+
+CHIP_ASRCS	= m16c_vectors.S
+CHIP_CSRCS	= m16c_initialstate.c m16c_copystate.c m16c_lowputc.c m16c_irq.c \
+		  m16c_timerisr.c m16c_serial.c m16c_dumpstate.c
+
+ifneq ($(CONFIG_DISABLE_SIGNALS),y)
+CHIP_CSRCS	+= m16c_schedulesigaction.c m16c_sigdeliver.c
+endif
+
+

nuttx/arch/sh/src/m16c/README.txt

@@ -0,0 +1,2 @@
+This directory contains source files that are unique to the M16C
+chip architecture.

nuttx/arch/sh/src/m16c/chip.h

@@ -0,0 +1,281 @@
+/************************************************************************************
+ * arch/sh/src/m16c/chip.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_SH_SRC_M16C_CHIP_H
+#define __ARCH_SH_SRC_M16C_CHIP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#ifndef __ASSEMBLY__
+#  include <stdint.h>
+#endif
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* FLG register bits */
+
+#define M16C_FLG_C         0x0001    /* Bit 0: Carry flag */
+#define M16C_FLG_D         0x0002    /* Bit 1: Debug flag */
+#define M16C_FLG_Z         0x0004    /* Bit 2: Zero flag */
+#define M16C_FLG_S         0x0008    /* Bit 3: Sign flag */
+#define M16C_FLG_B         0x0010    /* Bit 4: Register bank flag */
+#define M16C_FLG_O         0x0020    /* Bit 5: Overflow flag */
+#define M16C_FLG_I         0x0040    /* Bit 6: Interrupt enable flag */
+#define M16C_FLG_U         0x0080    /* Bit 7: Stack pointer select flag */
+                                     /* Bits 8-11: Reserved */
+#define M16C_FLG_IPLMASK   0x7000    /* Bits 12:14: Processor interrupt priority level */
+                                     /* Bit 15: Reserved */
+/* Memory Map */
+
+/* Memory-mapped special function registers begin at address 0x00000 */
+
+#define M16C_SFR_BASE      0x00000   /* 00000-003ff: Special Function Registers */
+
+/* Internal, on-chip SRAM begins at address 0x00400 for all chips, regardless of the
+ * size of the on-chip SRAM.
+ */
+
+#define M16C_IRAM_BASE     0x00400   /* 00400-00xxx: Internal RAM */
+#if defined(CONFIG_ARCH_CHIP_M30262F3) || defined(CONFIG_ARCH_CHIP_M30262F4)
+#  define M16C_IRAM_END    0x007ff   /*              End+1 address of internal RAM */
+                                     /* 00800-0efff: Reserved */
+#elif defined(CONFIG_ARCH_CHIP_M30262F6) || defined(CONFIG_ARCH_CHIP_M30262F8)
+#  define M16C_IRAM_END    0x00bff   /*              End+1 address of internal RAM */
+                                     /* 00c00-0efff: Reserved */
+#endif
+
+/* Two banks of virtual EEPROM (all parts) */
+
+#define M16C_VEEPROM1_BASE 0x0f000   /* 0f000-0f7fff: Virtual EEPPROM block 1 */
+#define M16C_VEEPROM2_BASE 0x0f800   /* 0f800-0fffff: Virtual EEPPROM block 2 */
+
+/* If there were external, "far" RAM, it would be begin at 0x10000.  However, these
+ * specific chips do not support external RAM.
+ */
+
+/* Each part has a different amount on on-chip FLASH.  The ending FLASH address is
+ * 0xfffff for all chips, but the starting address varies depening on the amount
+ * of on-chip FLASH.
+ */
+
+#if defined(CONFIG_ARCH_CHIP_M30262F3)
+                                     /* 10000-f9ffff: Reserved */
+#  define M16C_FLASH_BASE    0xfa000 /* fa000-ffffff: Flash ROM (M30262F8) */
+#elif defined(CONFIG_ARCH_CHIP_M30262F4)
+                                     /* 10000-f7ffff: Reserved */
+#  define M16C_FLASH_BASE    0xf8000 /* f8000-ffffff: Flash ROM (M30262F8) */
+#elif defined(CONFIG_ARCH_CHIP_M30262F6)
+                                     /* 10000-f3ffff: Reserved */
+#  define M16C_FLASH_BASE    0xf4000 /* f4000-ffffff: Flash ROM (M30262F8) */
+#elif defined(CONFIG_ARCH_CHIP_M30262F8)
+                                     /* 10000-efffff: Reserved */
+#  define M16C_FLASH_BASE    0xf0000 /* f0000-ffffff: Flash ROM (M30262F8) */
+#endif
+
+/* Special Function Register Addresses */
+
+#define M16C_PM0           0x00004    /* Processor mode 0 */
+#define M16C_PM1           0x00005    /* Processor mode 1 */
+#define M16C_CM0           0x00006    /* System clock control 0 */
+#define M16C_CM1           0x00007    /* System clock control 1 */
+#define M16C_AIER          0x00009    /* Addrese match interrupt enable */
+#define M16C_PRCR          0x0000a    /* Protect */
+#define M16C_CM2           0x0000c    /* Oscillation stop detection */
+#define M16C_WDTS          0x0000e    /* Watchdog timer start */
+#define M16C_WDC           0x0000f    /* Watchdog timer control */
+#define M16C_RMAD0         0x00010    /* Address match interrupt 0 */
+#define M16C_RMAD1         0x00014    /* Address match interrupt 1 */
+#define M16C_VCR1          0x00019    /* Power supply detection 1 */
+#define M16C_VCR2          0x0001a    /* Power supply detection 2 */
+#define M16C_PM2           0x0001e    /* Processor mode 2 */
+#define M16C_D4INT         0x0001f    /* Power supply 4V detection */
+#define M16C_SAR0          0x00020    /* DMA0 source pointer */
+#define M16C_DAR0          0x00024    /* DMA0 destination pointer */
+#define M16C_TCR0          0x00028    /* DMA0 transfer counter */
+#define M16C_DM0CON        0x0002c    /* DMA0 control */
+#define M16C_SAR1          0x00030    /* DMA1 source pointer */
+#define M16C_DAR1          0x00034    /* DMA1 destination pointer */
+#define M16C_TCR1          0x00038    /* DMA1 transfer counter */
+#define M16C_DM1CON        0x0003c    /* DMA1 control */
+#define M16C_INT3IC        0x00044    /* INT3 interrupt control */
+#define M16C_INT5IC        0x00048    /* INT5 interrupt control */
+#define M16C_INT4IC        0x00049    /* INT4 interrupt control */
+#define M16C_BCNIC         0x0004a    /* Bus collision detection interrupt control */
+#define M16C_DM0IC         0x0004b    /* DMA0 interrupt control */
+#define M16C_DM1IC         0x0004c    /* DMA1 interrupt control */
+#define M16C_KUPIC         0x0004d    /* Key input interrupt control */
+#define M16C_ADIC          0x0004e    /* A-D conversion interrupt control */
+#define M16C_S2TIC         0x0004f    /* UART2 transmit interrupt control */
+#define M16C_S2RIC         0x00050    /* UART2 receive interrupt control */
+#define M16C_S0TIC         0x00051    /* UART0 transmit interrupt control */
+#define M16C_S0RIC         0x00052    /* UART0 receive interrupt control */
+#define M16C_S1TIC         0x00053    /* UART1 transmit interrupt control */
+#define M16C_S1RIC         0x00054    /* UART1 receive interrupt control */
+#define M16C_TA0IC         0x00055    /* Timer A0 interrupt control */
+#define M16C_TA1IC         0x00056    /* Timer A1 interrupt control */
+#define M16C_TA2IC         0x00057    /* Timer A2 interrupt control */
+#define M16C_TA3IC         0x00058    /* Timer A3 interrupt control */
+#define M16C_TA4IC         0x00059    /* Timer A4 interrupt control */
+#define M16C_TB0IC         0x0005a    /* Timer B0 interrupt control */
+#define M16C_TB1IC         0x0005b    /* Timer B1 interrupt control */
+#define M16C_TB2IC         0x0005c    /* Timer B2 interrupt control */
+#define M16C_INT0IC        0x0005d    /* INT0 interrupt control */
+#define M16C_INT1IC        0x0005e    /* INT1 interrupt control */
+#define M16C_FMR4          0x001b3    /* Flash Control 4 */
+#define M16C_FMR1          0x001b5    /* Flash Control 1 */
+#define M16C_FMR0          0x001b7    /* Flash Control 0 */
+#define M16C_PCLKR         0x0025e    /* Peripheral Clock Select */
+#define M16C_TA11          0x00342    /* Timer A1-1 */
+#define M16C_TA21          0x00344    /* Timer A2-1 */
+#define M16C_TA41          0x00346    /* Timer A4-1 */
+#define M16C_INVC0         0x00348    /* Three-phase PWM control 0 */
+#define M16C_INVC1         0x00349    /* Three-phase PWM control 1 */
+#define M16C_IDB0          0x0034a    /* Three-phase output buffer 0 */
+#define M16C_IDB1          0x0034b    /* Three-phase output buffer 1 */
+#define M16C_DTT           0x0034c    /* Dead time timer */
+#define M16C_ICTB2         0x0034d    /* Timer B2 interrupt occurences frequency set counter */
+#define M16C_IFSR          0x0035f    /* Interrupt request cause select */
+#define M16C_U2SMR4        0x00374    /* UART2 special mode register4 */
+#define M16C_U2SMR3        0x00375    /* UART2 special mode register3 */
+#define M16C_U2SMR2        0x00376    /* UART2 special mode register2 */
+#define M16C_U2SMR         0x00377    /* UART2 special mode */
+#define M16C_U2MR          0x00378    /* UART2 transmit/receive mode */
+#define M16C_U2BRG         0x00379    /* UART2 bit rate generator */
+#define M16C_U2TB          0x0037a    /* UART2 transmit buffer */
+#define M16C_U2C0          0x0037c    /* UART2 transmit/receive control 0 */
+#define M16C_U2C1          0x0037d    /* UART2 transmit/receive control 1 */
+#define M16C_U2RB          0x0037e    /* UART2 receive buffer */
+#define M16C_TABSR         0x00380    /* Count start flag */
+#define M16C_CPSRF         0x00381    /* Clock prescaler reset flag */
+#define M16C_ONSF          0x00382    /* One-shot start flag */
+#define M16C_TRGSR         0x00383    /* Trigger select */
+#define M16C_UDF           0x00384    /* Up-down flag */
+#define M16C_TA0           0x00386    /* Timer A0 */
+#define M16C_TA1           0x00388    /* Timer A1 */
+#define M16C_TA2           0x0038a    /* Timer A2 */
+#define M16C_TA3           0x0038c    /* Timer A3 */
+#define M16C_TA4           0x0038e    /* Timer A4 */
+#define M16C_TB0           0x00390    /* Timer B0 */
+#define M16C_TB1           0x00392    /* Timer B1 */
+#define M16C_TB2           0x00394    /* Timer B2 */
+#define M16C_TA0MR         0x00396    /* Timer A0 mode */
+#define M16C_TA1MR         0x00397    /* Timer A1 mode */
+#define M16C_TA2MR         0x00398    /* Timer A2 mode */
+#define M16C_TA3MR         0x00399    /* Timer A3 mode */
+#define M16C_TA4MR         0x0039a    /* Timer A4 mode */
+#define M16C_TB0MR         0x0039b    /* Timer B0 mode */
+#define M16C_TB1MR         0x0039c    /* Timer B1 mode */
+#define M16C_TB2MR         0x0039d    /* Timer B2 mode */
+#define M16C_TB2SC         0x0039e    /* Timer B2 special mode */
+#define M16C_U0MR          0x003a0    /* UART0 transmit/receive mode */
+#define M16C_U0BRG         0x003a1    /* UART0 bit rate generator */
+#define M16C_U0TB          0x003a2    /* UART0 transmit buffer */
+#define M16C_U0C0          0x003a4    /* UART0 transmit/receive control 0 */
+#define M16C_U0C1          0x003a5    /* UART0 transmit/receive control 1 */
+#define M16C_U0RB          0x003a6    /* UART0 receive buffer */
+#define M16C_U1MR          0x003a8    /* UART1 transmit/receive mode */
+#define M16C_U1BRG         0x003a9    /* UART1 bit rate generator */
+#define M16C_U1TB          0x003aa    /* UART1 transmit buffer */
+#define M16C_U1C0          0x003ac    /* UART1 transmit/receive control 0 */
+#define M16C_U1C1          0x003ad    /* UART1 transmit/receive control 1 */
+#define M16C_U1RB          0x003ae    /* UART1 receive buffer */
+#define M16C_UCON          0x003b0    /* UART2 transmit/receive control 2 */
+#define M16C_DM0SL         0x003b8    /* DMA0 cause select */
+#define M16C_DM1SL         0x003ba    /* DMA1 cause select */
+#define M16C_AD0           0x003c0    /* A-D 0 */
+#define M16C_AD1           0x003c2    /* A-D 1 */
+#define M16C_AD2           0x003c4    /* A-D 2 */
+#define M16C_AD3           0x003c6    /* A-D 3 */
+#define M16C_AD4           0x003c8    /* A-D 4 */
+#define M16C_AD5           0x003ca    /* A-D 5 */
+#define M16C_AD6           0x003cc    /* A-D 6 */
+#define M16C_AD7           0x003ce    /* A-D 7 */
+#define M16C_ADCON2        0x003d4    /* A-D control 2 */
+#define M16C_ADCON0        0x003d6    /* A-D control 0 */
+#define M16C_ADCON1        0x003d7    /* A-D control 1 */
+#define M16C_P1            0x003e1    /* Port P1 */
+#define M16C_PD1           0x003e3    /* Port P1 direction */
+#define M16C_P6            0x003ec    /* Port P6 */
+#define M16C_P7            0x003ed    /* Port P7 */
+#define M16C_PD6           0x003ee    /* Port P6 direction */
+#define M16C_PD7           0x003ef    /* Port P7 direction */
+#define M16C_P8            0x003f0    /* Port P8 */
+#define M16C_P9            0x003f1    /* Port P9 */
+#define M16C_PD8           0x003f2    /* Port P8 direction */
+#define M16C_PD9           0x003f3    /* Port P9 direction */
+#define M16C_P10           0x003f4    /* Port P10 */
+#define M16C_PD10          0x003f6    /* Port P10 direction */
+#define M16C_PUR0          0x003fc    /* Pull-up control 0 */
+#define M16C_PUR1          0x003fd    /* Pull-up control 1 */
+#define M16C_PUR2          0x003fe    /* Pull-up control 2 */
+#define M16C_PCR           0x003ff    /* Port control */
+
+/************************************************************************************
+ * Global Data
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+extern uint16_t g_snbss;		/* Start of near .bss */
+extern uint16_t g_enbss;		/* End+1 of near .bss */
+extern uint16_t g_sndata;		/* Start of near .data */
+extern uint16_t g_endata;		/* End+1 of near .data */
+extern uint32_t g_enronly;		/* Start of relocated read-only data in FLASH */
+#ifdef CONFIG_M16C_HAVEFARRAM
+  extern uint32_t g_sfbss;		/* Start of far .bss */
+  extern uint32_t g_efbss;		/* End+1 of far .bss */
+  extern uint32_t g_sfdata;		/* Start of far .data */
+  extern uint32_t g_efdata;		/* End_1 of far .data */
+  extern uint32_t g_efronly;	/* Start of relocated read-only data in FLASH */
+#endif
+extern uint32_t g_svarvect;		/* Start of variable vectors */
+extern uint32_t g_heapbase;		/* Start of the heap */
+
+/* Address of the saved user stack pointer */
+
+#ifndef __ASSEMBLY__
+#  if CONFIG_ARCH_INTERRUPTSTACK > 3
+     extern uint16_t g_userstack;
+#  endif
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ARCH_SH_SRC_M16C_CHIP_H */

nuttx/arch/sh/src/m16c/m16c_copystate.c

@@ -0,0 +1,74 @@
+/****************************************************************************
+ * arch/sh/src/m16c/up_copystate.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <string.h>
+
+#include "os_internal.h"
+#include "up_internal.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_copystate
+ ****************************************************************************/
+
+/* A little faster than most memcpy's */
+
+void up_copystate(uint32_t *dest, uint32_t *src)
+{
+  memcpy(dest, src, XCPTCONTEXT_SIZE);
+}
+

nuttx/arch/sh/src/m16c/m16c_dumpstate.c

@@ -0,0 +1,251 @@
+/****************************************************************************
+ * arch/sh/src/m16c/m16c_assert.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+#include "os_internal.h"
+#include "chip.h"
+
+#ifdef CONFIG_ARCH_STACKDUMP
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/* Output debug info if stack dump is selected -- even if  debug is not
+ * selected.
+ */
+
+#ifdef CONFIG_ARCH_STACKDUMP
+# undef  lldbg
+# define lldbg lib_lowprintf
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: m16c_getsp
+ ****************************************************************************/
+
+static inline uint16_t m16c_getsp(void)
+{
+  uint16_t sp;
+
+  __asm__ __volatile__
+    (
+      "\tstc sp, %0\n\t"
+      : "=r" (sp)
+      :
+      : "memory"
+    );
+  return sp;
+}
+
+/****************************************************************************
+ * Name: m16c_getusersp
+ ****************************************************************************/
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+static inline uint16_t m16c_getusersp(void)
+{
+  uint8_t *ptr = (uint8_t*) current_regs;
+  return (uint16_t)ptr[REG_SP] << 8 | ptr[REG_SP+1];
+}
+#endif
+
+/****************************************************************************
+ * Name: m16c_stackdump
+ ****************************************************************************/
+
+static void m16c_stackdump(uint16_t sp, uint16_t stack_base)
+{
+  uint16_t stack;
+
+  for (stack = sp & ~7; stack < stack_base; stack += 8)
+    {
+      uint8_t *ptr = (uint8_t*)stack;
+      lldbg("%04x: %02x %02x %02x %02x %02x %02x %02x %02x\n",
+             stack, ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5], ptr[6], ptr[7]);
+    }
+}
+
+/****************************************************************************
+ * Name: m16c_registerdump
+ ****************************************************************************/
+
+static inline void m16c_registerdump(void)
+{
+  uint8_t *ptr = (uint8_t*) current_regs;
+
+  /* Are user registers available from interrupt processing? */
+
+  if (ptr)
+    {
+      /* Yes.. dump the interrupt registers */
+
+      lldbg("PC: %02x%02x%02x FLG: %02x00%02x FB: %02x%02x SB: %02x%02x SP: %02x%02x\n",
+            ptr[REG_FLGPCHI] & 0xff, ptr[REG_PC], ptr[REG_PC+1],
+            ptr[REG_FLGPCHI] >> 8, ptr[REG_FLG],
+            ptr[REG_FB], ptr[REG_FB+1],
+            ptr[REG_SB], ptr[REG_SB+1],
+            ptr[REG_SP], ptr[REG_SP+1]);
+
+      lldbg("R0: %02x%02x R1: %02x%02x R2: %02x%02x A0: %02x%02x A1: %02x%02x\n",
+            ptr[REG_R0], ptr[REG_R0+1], ptr[REG_R1], ptr[REG_R1+1],
+            ptr[REG_R2], ptr[REG_R2+1], ptr[REG_R3], ptr[REG_R3+1],
+            ptr[REG_A0], ptr[REG_A0+1], ptr[REG_A1], ptr[REG_A1+1]);
+
+    }
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_dumpstate
+ ****************************************************************************/
+
+void up_dumpstate(void)
+{
+  _TCB    *rtcb = (_TCB*)g_readytorun.head;
+  uint16_t sp   = m16c_getsp();
+  uint16_t ustackbase;
+  uint16_t ustacksize;
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+  uint16_t istackbase;
+  uint16_t istacksize;
+#endif
+
+  /* Get the limits on the user stack memory */
+
+  if (rtcb->pid == 0)
+    {
+      ustackbase = g_heapbase - 1;
+      ustacksize = CONFIG_IDLETHREAD_STACKSIZE;
+    }
+  else
+    {
+      ustackbase = (uint16_t)rtcb->adj_stack_ptr;
+      ustacksize = (uint16_t)rtcb->adj_stack_size;
+    }
+
+  /* Get the limits on the interrupt stack memory. The near RAM memory map is as follows:
+   * 
+   * 0x00400 - DATA		Size: Determined by linker
+   *           BSS		Size: Determined by linker
+   *           Interrupt stack	Size: CONFIG_ARCH_INTERRUPTSTACK
+   *           Idle stack		Size: CONFIG_IDLETHREAD_STACKSIZE
+   *           Heap		Size: Everything remaining
+   * 0x00bff - (end+1)
+   */
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+  istackbase = g_enbss;
+  istacksize = CONFIG_ARCH_INTERRUPTSTACK;
+
+  /* Show interrupt stack info */
+
+  lldbg("sp:     %04x\n", sp);
+  lldbg("IRQ stack:\n");
+  lldbg("  base: %04x\n", istackbase);
+  lldbg("  size: %04x\n", istacksize);
+
+  /* Does the current stack pointer lie within the interrupt
+   * stack?
+   */
+
+  if (sp <= istackbase && sp > istackbase - istacksize)
+    {
+      /* Yes.. dump the interrupt stack */
+
+      m16c_stackdump(sp, istackbase);
+
+      /* Extract the user stack pointer from the register area */
+
+      sp = m16c_getusersp();
+      lldbg("sp:     %04x\n", sp);
+    }
+
+  /* Show user stack info */
+
+  lldbg("User stack:\n");
+  lldbg("  base: %04x\n", ustackbase);
+  lldbg("  size: %04x\n", ustacksize);
+#else
+  lldbg("sp:         %04x\n", sp);
+  lldbg("stack base: %04x\n", ustackbase);
+  lldbg("stack size: %04x\n", ustacksize);
+#endif
+
+  /* Dump the user stack if the stack pointer lies within the allocated user
+   * stack memory.
+   */
+
+  if (sp > ustackbase || sp <= ustackbase - ustacksize)
+    {
+#if !defined(CONFIG_ARCH_INTERRUPTSTACK) || CONFIG_ARCH_INTERRUPTSTACK < 4
+      lldbg("ERROR: Stack pointer is not within allocated stack\n");
+#endif
+    }
+  else
+    {
+      m16c_stackdump(sp, ustackbase);
+    }
+
+  /* Then dump the registers (if available) */
+
+  m16c_registerdump();
+}
+
+#endif /* CONFIG_ARCH_STACKDUMP */

nuttx/arch/sh/src/m16c/m16c_head.S

@@ -0,0 +1,278 @@
+/************************************************************************************
+ * arch/sh/src/m16c/m16c_head.S
+ *
+ *	 Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
+ *	 Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *		notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *		notice, this list of conditions and the following disclaimer in
+ *		the documentation and/or other materials provided with the
+ *		distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *		used to endorse or promote products derived from this software
+ *		without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip.h"
+#include "up_internal.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Macro Definitions
+ ************************************************************************************/
+
+/*****************************************************************************
+ * Name: showprogress
+ *
+ * Description:
+ *   Print a character on the UART to show boot status.
+ *
+ *****************************************************************************/
+
+	.macro	showprogress, code
+#ifdef CONFIG_DEBUG
+	.globl	_up_lowputc
+	mov.b	r#\code1l		/* Character to print */
+	jsr.a	_up_lowputc		/* Print it */
+#endif
+	.endm
+
+/************************************************************************************
+ * Data
+ ************************************************************************************/
+
+/* The near RAM memory map is as follows:
+ * 
+ * 0x00400 - DATA		Size: Determined by linker
+ *           BSS		Size: Determined by linker
+ *           Interrupt stack	Size: CONFIG_ARCH_INTERRUPTSTACK
+ *           Idle stack		Size: CONFIG_IDLETHREAD_STACKSIZE
+ *           Heap		Size: Everything remaining
+ * 0x00bff - (end+1)
+ */
+
+	.section .rodata
+	.globl	_g_snbss
+	.type	_g_snbss, object
+_g_snbss:
+	.word	_g_snbss
+	.size	_g_snbss, .-_g_snbss
+
+	.globl	_g_enbss
+	.type	_g_enbss, object
+_g_enbss:
+	.word	_g_enbss
+	.size	_g_enbss, .-_g_enbss
+
+	.globl	_g_sndata
+	.type	_g_sndata, object
+_g_sndata:
+	.word	_g_sndata
+	.size	_g_sndata, .-_g_sndata
+
+	.globl	_g_endata
+	.type	_g_endata, object
+_g_endata:
+	.word	_g_endata
+	.size	_g_endata, .-_g_endata
+
+	.globl	_g_enronly
+	.type	_g_enronly, object
+_g_enronly:
+	.long	_g_enronly
+	.size	_g_enronly, .-_g_efronly
+
+#ifdef CONFIG_M16C_HAVEFARRAM
+	.globl	_g_sfbss
+	.type	_g_sfbss, object
+_g_sfbss:
+	.long	_g_sfbss
+	.size	_g_sfbss, .-_g_sfbss
+
+	.globl	_g_efbss
+	.type	_g_efbss, object
+_g_efbss:
+	.long	_g_efbss
+	.size	_g_efbss, .-_g_efbss
+
+	.globl	_g_sfdata
+	.type	_g_sfdata, object
+_g_sfdata:
+	.long	_g_sfdata
+	.size	_g_sfdata, .-_g_sfdata
+
+	.globl	_g_efdata
+	.type	_g_efdata, object
+_g_efdata:
+	.long	_g_efdata
+	.size	_g_efdata, .-_g_efdata
+
+	.globl	_g_efronly
+	.type	_g_efronly, object
+_g_efronly:
+	.long	_g_efronly
+	.size	_g_efronly, .-_g_efronly
+#endif
+	.globl	_g_svarvect
+	.type	_g_svarvect, object
+_g_svarvect:
+	.long	_svarvect
+	.size	_g_svarvect, .-_g_svarvect
+
+	.globl	_g_heapbase
+	.type	_g_heapbase, object
+_g_heapbase:
+	.long	_enbss+CONFIG_ARCH_INTERRUPTSTACK+CONFIG_IDLETHREAD_STACKSIZE
+	.size	_g_heapbase, .-_g_heapbase
+
+/************************************************************************************
+ * Code
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: __start
+ *
+ * Description:
+ *   After reset, program execution starts here.
+ *
+ ************************************************************************************/
+
+ 	.text
+	.globl	__start
+	.globl	_enbss
+	.type	__start, #function
+__start:
+
+/* Set the interrupt and user stack pointers */
+
+	mov.w	#_enbss, R0
+	ldc	R0, isp			/* Set the interrupt stack pointer to the end of BSS */
+	add.w	#CONFIG_IDLETHREAD_STACKSIZE, R0
+	fset	U			/* Set bit 7 (U) to select the user stack pointer */
+	ldc	R0, sp			/* Set the user stack pointer */
+
+/* Set BCLK speed. At reset, the processor clock  (BLCK) defaults to a divisor of 8.
+ * This sets clock to F1 (divide by 1) on XIN: BCLK = XIN frequency.
+ */
+
+ 	mov.b	#0x01, M16C_PRCR	/* Unprotect CM0 to change clock setting */
+	mov.b	#0x08, M16C_CM0		/* enable CM17 and CM16 to set BCLK to F1
+					 * CM17 & CM16 defaults to 0 after reset and
+					 * so we only need to reset CM06 to 0 */
+	mov.b	#0x00,M16C_PRCR		/* protect CM0 */
+
+/* The two MS bits of the interrupt cause select register must be set to
+ * enable the use of INT4 and INT5
+ */
+
+ 	mov.b	#0xc0, M16C_IFSR	/* Set b7 & b6 if application will use INT4 & INT5 */
+	ldc	#M16C_IRAM_BASE, sb	/* Set sb register (to what?) */
+
+/* Set up INTB to point to location of variable vector table */
+
+	mov.w	_g_svarvect, r0		/* R0 = lower 16-bits */
+	mov.w	_g_svarvect+2, r1	/* R1 = upper 4-bits */
+	ldc	r1, intbh
+	ldc	r0, intbl
+
+/* Configure the uart so that we can get debug output as soon as possible. */
+
+	.globl	_up_lowsetup		/* Early initialization of UART */
+	jsr.a	_up_lowsetup
+	showprogress 'A'
+
+/* Clear near .bss sections */
+
+	mov.b	#0x00, r0l		/* r0l: 0 */
+	mov.w	_g_snbss, a1		/* a1: start of near .bss */
+	mov.w	_g_enbss, r3		/* r3: end of near .bss */
+	sub.w	a1, r3			/* r3: size of near .bss */
+	sstr.b				/* Clear near .bss */
+
+/* Clear far .bss sections */
+
+	showprogress 'B'
+
+#ifdef CONFIG_M16C_HAVEFARRAM
+# warning "Far RAM support not implemented"
+#endif
+
+/* Initialize near .data sections (.rodata is not moved) */
+
+	mov.w	_g_enronly, a0		/* a0: Low 16 bits of source address */
+	mov.b	_g_enronly+2, r1h	/* 4 MS of 20-bit source address */
+	mov.w	_g_sndata, a1		/* a1: start of near .data */
+	mov.w	_g_endata, r3		/* r3: end of near .data */
+	sub.w	a1, r3			/* r3: size of near .data */
+	smovf.b				/* Copy source to near .data */
+
+/* Initialize far .data sections (.rodata is not moved) */
+
+	showprogress 'C'
+
+#ifdef CONFIG_M16C_HAVEFARRAM
+# warning "Far RAM support not implemented"
+#endif
+
+/* Perform early console initialization */
+
+#ifdef USE_EARLYSERIALINIT
+	.globl	_up_earlyconsoleinit	/* Early initialization of console driver */
+	jsr.a	 _up_earlyconsoleinit	/* Call it */
+	showprogress 'D'
+#endif
+
+/* Call C++ constructors */
+
+#ifdef CONFIG_CPLUSPLUS
+#  warning "No C++ support yet"
+	showprogress 'E'
+#endif
+
+/* Initialize onboard LEDs */
+
+#ifdef CONFIG_ARCH_LEDS
+	.globl	_up_ledinit		/* Boot LED setup */
+	jsr.a	_up_ledinit		/* Call it */
+#endif
+	showprogress '\n'
+
+/* Pass control to NuttX */
+
+	.globl	_os_start
+	jsr.a	_os_start
+
+/* NuttX will not return, but just in case... */
+
+_os_exit:
+	jmp.s	_os_exit
+	.size	__start, .-__start
+	.end

nuttx/arch/sh/src/m16c/m16c_initialstate.c

@@ -0,0 +1,111 @@
+/****************************************************************************
+ *  arch/sh/src/m16c/m16c_initialstate.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <string.h>
+
+#include <nuttx/arch.h>
+#include <arch/board/board.h>
+
+#include "up_internal.h"
+#include "up_arch.h"
+
+/****************************************************************************
+ * Preprocessor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_initial_state
+ *
+ * Description:
+ *   A new thread is being started and a new TCB has been created. This
+ *   function is called to initialize the processor specific portions of the
+ *   new TCB.
+ *
+ *   This function must setup the intial architecture registers and/or stack
+ *   so that execution will begin at tcb->start on the next context switch.
+ *
+ ****************************************************************************/
+
+void up_initial_state(FAR _TCB *tcb)
+{
+  FAR struct xcptcontext *xcp  = &tcb->xcp;
+  FAR uint8_t            *regs = xcp->regs;
+
+  /* Initialize the initial exception register context structure */
+
+  memset(xcp, 0, sizeof(struct xcptcontext));
+
+  /* Offset 0: FLG (bits 12-14) PC (bits 16-19) as would be present by an interrupt */
+
+  *regs++ = ((M16C_DEFAULT_IPL << 4) | ((uint32_t)tcb->start >> 16));
+
+  /* Offset 1: FLG (bits 0-7) */
+
+#ifdef CONFIG_SUPPRESS_INTERRUPTS
+  *regs++ = M16C_FLG_U;
+#else
+  *regs++ = M16C_FLG_U | M16C_FLG_I;
+#endif
+
+  /* Offset 2-3: 16-bit PC [0]:bits8-15 [1]:bits 0-7 */
+
+  *regs++ = (uint32_t)tcb->start >> 8;  /* Bits 8-15 of PC */
+  *regs++ = (uint32_t)tcb->start;       /* Bits 0-7 of PC */
+
+  /* Offset 18-20: User stack pointer */
+
+   regs   = &xcp->regs[REG_SP];
+  *regs++ = (uint32_t)tcb->adj_stack_ptr >> 8;  /* Bits 8-15 of SP */
+  *regs   = (uint32_t)tcb->adj_stack_ptr;       /* Bits 0-7 of SP */
+}

nuttx/arch/sh/src/m16c/m16c_irq.c

@@ -0,0 +1,127 @@
+/****************************************************************************
+ * arch/sh/src/m16c/m16c_irq.c
+ *
+ *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include "up_internal.h"
+
+/****************************************************************************
+ * Private Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* This holds a references to the current interrupt level register storage
+ * structure.  If is non-NULL only during interrupt processing.
+ */
+
+volatile uint32_t *current_regs; /* Actually a pointer to the beginning of a uint8_t array */
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_irqinitialize
+ ****************************************************************************/
+
+void up_irqinitialize(void)
+{
+  current_regs = NULL;
+  
+  /* And finally, enable interrupts */
+
+#ifndef CONFIG_SUPPRESS_INTERRUPTS
+  asm("fset i");
+#endif
+}
+
+/****************************************************************************
+ * Name: up_disable_irq
+ *
+ * Description:
+ *   On many architectures, there are three levels of interrupt enabling: (1)
+ *   at the global level, (2) at the level of the interrupt controller,
+ *   and (3) at the device level.  In order to receive interrupts, they
+ *   must be enabled at all three levels.
+ *
+ *   This function implements disabling of the device specified by 'irq'
+ *   at the interrupt controller level if supported by the architecture
+ *   (irqsave() supports the global level, the device level is hardware
+ *   specific).
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_ARCH_NOINTC
+void up_disable_irq(int irq)
+{
+  /* There are no ez80 interrupt controller settings to disable IRQs */
+}
+
+/****************************************************************************
+ * Name: up_enable_irq
+ *
+ * Description:
+ *   This function implements enabling of the device specified by 'irq'
+ *   at the interrupt controller level if supported by the architecture
+ *   (irqsave() supports the global level, the device level is hardware
+ *   specific).
+ *
+ ****************************************************************************/
+
+void up_enable_irq(int irq)
+{
+  /* There are no ez80 interrupt controller settings to enable IRQs */
+}
+
+#endif /* CONFIG_ARCH_NOINTC */

nuttx/arch/sh/src/m16c/m16c_lowputc.c

@@ -0,0 +1,343 @@
+/**************************************************************************
+ * arch/sh/src/m16c/m16c_lowputc.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ **************************************************************************/
+
+/**************************************************************************
+ * Included Files
+ **************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <nuttx/arch.h>
+
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+#include "up_internal.h"
+#include "m16c_uart.h"
+
+/**************************************************************************
+ * Private Definitions
+ **************************************************************************/
+
+/* Configuration **********************************************************/
+
+#ifndef M16C_XIN_PRESCALER
+#  define M16C_XIN_PRESCALER 1
+#endif
+
+/* Is there any serial support?  This might be the case if the board does
+ * not have serial ports but supports stdout through, say, an LCD.
+ */
+
+#if defined(CONFIG_UART0_DISABLE) || defined(CONFIG_UART1_DISABLE) || defined(CONFIG_UART2_DISABLE)
+#  define HAVE_SERIAL
+#else
+#  undef HAVE_SERIAL
+#endif
+
+/* Is one of the serial ports a console? */
+
+#if defined(CONFIG_UART0_SERIAL_CONSOLE) && !defined(CONFIG_UART0_DISABLE)
+#  define HAVE_SERIALCONSOLE 1
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && !defined(CONFIG_UART1_DISABLE)
+#  define HAVE_SERIALCONSOLE 1
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
+#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && !defined(CONFIG_UART2_DISABLE)
+#  define HAVE_SERIALCONSOLE 1
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#else
+#  if defined(CONFIG_UART0_SERIAL_CONSOLE) || defined(CONFIG_UART1_SERIAL_CONSOLE)|| defined(CONFIG_UART2_SERIAL_CONSOLE)
+#    error "A serial console selected, but corresponding UART not enabled"
+#  endif
+#  undef HAVE_SERIALCONSOLE
+#endif
+
+#if defined(HAVE_SERIALCONSOLE) && defined(CONFIG_LCD_CONSOLE)
+#  error "Both serial and LCD consoles are defined"
+#elif !defined(HAVE_SERIALCONSOLE) && !defined(CONFIG_LCD_CONSOLE)
+#  warning "No console is defined"
+#endif
+
+/* Select UART parameters for the selected console */
+
+#ifdef HAVE_SERIALCONSOLE
+#if defined(CONFIG_UART0_SERIAL_CONSOLE)
+#  define M16C_UART_BASE     M16C_UART0_BASE
+#  define M16C_UART_BAUD     CONFIG_UART0_BAUD
+#  define M16C_UART_BITS     CONFIG_UART0_BITS
+#  define M16C_UART_PARITY   CONFIG_UART0_PARITY
+#  define M16C_UART_2STOP    CONFIG_UART0_2STOP
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+#  define M16C_UART_BASE     M16C_UART1_BASE
+#  define M16C_UART_BAUD     CONFIG_UART1_BAUD
+#  define M16C_UART_BITS     CONFIG_UART1_BITS
+#  define M16C_UART_PARITY   CONFIG_UART1_PARITY
+#  define M16C_UART_2STOP    CONFIG_UART1_2STOP
+#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
+#  define M16C_UART_BASE     M16C_UART2_BASE
+#  define M16C_UART_BAUD     CONFIG_UART2_BAUD
+#  define M16C_UART_BITS     CONFIG_UART2_BITS
+#  define M16C_UART_PARITY   CONFIG_UART2_PARITY
+#  define M16C_UART_2STOP    CONFIG_UART2_2STOP
+#else
+#  error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
+#endif
+
+/* Get mode setting */
+
+#if M16C_UART_BITS == 7
+#  define M16C_MR_SMDBITS UART_MR_SMD7BITS
+#elif M16C_UART_BITS == 8
+#  define M16C_MR_SMDBITS UART_MR_SMD8BITS
+#elif M16C_UART_BITS == 8
+#  define M16C_MR_SMDBITS UART_MR_SMD9BITS
+#else
+#  error "Number of bits not supported"
+#endif
+
+#if M16C_UART_PARITY == 0
+#  define M16C_MR_PARITY (0)
+#elif M16C_UART_PARITY == 1
+#  define M16C_MR_PARITY UART_MR_PRYE
+#elif M16C_UART_PARITY == 2
+#  define M16C_MR_PARITY (UART_MR_PRYE|UART_MR_PRY)
+#else
+#  error "Invalid parity selection"
+#endif
+
+#if M16C_UART_2STOP != 0
+#  define M16C_MR_STOPBITS UART_MR_STPS
+#else
+#  define M16C_MR_STOPBITS (0)
+#endif
+
+/* The full MR setting: */
+
+#define M16C_MR_VALUE (M16C_MR_SMDBITS|M16C_MR_PARITY|M16C_MR_STOPBITS)
+
+/* Clocking ***************************************************************/
+
+/* The Bit Rate Generator (BRG) value can be calculated by:
+ *
+ * BRG = source-frequency / prescaler / 16 / baud rate - 1
+ *
+ * Example:
+ *  source-frequency = 20,000,000 (20MHz)
+ *  prescaler = 1
+ *  baud rate = 19200
+ *  BRG = 20,000,000/1/16/19200 - 1 = 64
+ */
+
+#define M16C_UART_BRG_VALUE \
+	((M16C_XIN_FREQ / (16 * M16C_XIN_PRESCALER * M16C_UART_BAUD)) - 1)
+
+#endif /* HAVE_SERIALCONSOLE */
+
+/**************************************************************************
+ * Private Types
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Function Prototypes
+ **************************************************************************/
+
+/**************************************************************************
+ * Global Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Name: up_txready
+ *
+ * Description:
+ *   Return TRUE of the Transmit Data Register is empty
+ *
+ **************************************************************************/
+
+#ifdef HAVE_SERIALCONSOLE
+static inline int up_txready(void)
+{
+  /* Check the TI bit in the CI register.  1=Transmit buffer empty */
+
+  return ((getreg8(M16C_UART_BASE + M16C_UART_C1) & UART_C1_TI) != 0);
+}
+#endif /* HAVE_SERIALCONSOLE */
+
+/**************************************************************************
+ * Name: up_lowserialsetup
+ *
+ * Description:
+ *   This performs basic initialization of the UART used for the serial
+ *   console.  Its purpose is to get the console output availabe as soon
+ *   as possible.
+ *
+ **************************************************************************/
+
+#if defined(HAVE_SERIALCONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
+static inline void up_lowserialsetup(void)
+{
+  uint8_t regval;
+
+  /* Set the baud rate generator */
+
+  putreg8(M16C_UART_BRG_VALUE, M16C_UART_BASE + M16C_UART_BRG);
+
+  /* Disable CTS/RTS */
+
+  putreg8(UART_C0_CRD, M16C_UART_BASE + M16C_UART_C0);
+
+  /* Disable RX/TX interrupts */
+
+#if 0
+  putreg8(0, M16C_UCON);
+#endif
+
+/* Set interrupt cause=TX complete and continuous receive mode */
+
+#if defined(CONFIG_UART0_SERIAL_CONSOLE)
+  regval  = getreg8(M16C_UCON);
+  regval |= (UART_CON_U0IRS|UART_CON_U0RRM);
+  putreg8(regval, M16C_UCON);
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+  regval = getreg8(M16C_UCON);
+  regval |= (UART_CON_U1IRS|UART_CON_U1RRM);
+  putreg8(regval, M16C_UCON);
+#else
+  regval = getreg8(M16C_U2C1);
+  regval |= (UART_C1_U2IRS|UART_C1_U2RRM);
+  putreg8(regval, M16C_U2C1);
+#endif
+
+  /* Set UART transmit/receive control register 1 to enable transmit and receive */
+
+  putreg8(UART_C1_TE|UART_C1_RE, M16C_UART_BASE + M16C_UART_C1);
+	
+  /* Set UART transmit/receive mode register data bits, stop bits, parity */
+
+  putreg8(M16C_MR_VALUE, M16C_UART_BASE + M16C_UART_MR);
+
+  /* Set port direction registers for Rx/TX pins */
+
+ #if defined(CONFIG_UART0_SERIAL_CONSOLE)
+  regval  = getreg8(M16C_PD6);
+  regval &= ~(1 << 2);                         /* PD6-2:RxD1 */
+  regval |=  (1 << 3);                         /* PD6-3:TxD1 */
+  putreg8(regval, M16C_PD6);
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+  regval = getreg8(M16C_PD6);
+  regval &= ~(1 << 6);                         /* PD6-6:RxD1 */
+  regval |=  (1 << 7);                         /* PD6-7:TxD1 */
+  putreg8(regval, M16C_PD6);
+#else
+  regval = getreg8(M16C_PD7);
+  regval &= ~(1 << 1);                         /* PD7-1:RxD1 */
+  regval &=  (1 << 0);                         /* PD7-0:TxD1 */
+  putreg8(regval, M16C_PD7);
+#endif
+
+  /* Read any data left in the RX fifo */
+
+  regval = (uint8_t)getreg16(M16C_UART_BASE + M16C_UART_RB);
+}
+#endif /* HAVE_SERIALCONFIG && !CONFIG_SUPPRESS_UART_CONFIG */
+
+/**************************************************************************
+ * Public Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Name: up_lowputc
+ *
+ * Description:
+ *   Output one byte on the serial console.
+ *
+ **************************************************************************/
+
+#if defined(HAVE_SERIAL) && !defined(CONFIG_LCD_CONSOLE)
+void up_lowputc(char ch)
+{
+#ifdef HAVE_SERIALCONSOLE
+  /* Wait until the transmit buffer is empty */
+
+  while (!up_txready());
+
+  /* Write the data to the transmit buffer */
+
+  putreg16((uint16_t)ch, M16C_UART_BASE + M16C_UART_TB);
+#endif
+}
+#endif
+
+/**************************************************************************
+ * Name: up_lowsetup
+ *
+ * Description:
+ *   This performs basic initialization of the UART used for the serial
+ *   console.  Its purpose is to get the console output availabe as soon
+ *   as possible.
+ *
+ **************************************************************************/
+
+void up_lowsetup(void)
+{
+  /* Here we initialize the serial console early so that it can be used
+   * for bring-up debugging.
+   */
+
+#if defined(HAVE_SERIALCONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
+  up_lowserialsetup()
+#endif
+
+  /* The LCD is initialized here to because it may be that the LCD is
+   * used for console output.
+   */
+
+#ifdef CONFIG_ARCH_LCD
+  up_lcdinit();
+#endif
+}

nuttx/arch/sh/src/m16c/m16c_schedulesigaction.c

@@ -0,0 +1,201 @@
+/****************************************************************************
+ * arch/sh/src/m16c/m16c_schedulesigaction.c
+ *
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <sched.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+
+#include "os_internal.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+#ifndef CONFIG_DISABLE_SIGNALS
+
+/****************************************************************************
+ * Private Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Funictions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_schedule_sigaction
+ *
+ * Description:
+ *   This function is called by the OS when one or more
+ *   signal handling actions have been queued for execution.
+ *   The architecture specific code must configure things so
+ *   that the 'igdeliver' callback is executed on the thread
+ *   specified by 'tcb' as soon as possible.
+ *
+ *   This function may be called from interrupt handling logic.
+ *
+ *   This operation should not cause the task to be unblocked
+ *   nor should it cause any immediate execution of sigdeliver.
+ *   Typically, a few cases need to be considered:
+ *
+ *   (1) This function may be called from an interrupt handler
+ *       During interrupt processing, all xcptcontext structures
+ *       should be valid for all tasks.  That structure should
+ *       be modified to invoke sigdeliver() either on return
+ *       from (this) interrupt or on some subsequent context
+ *       switch to the recipient task.
+ *   (2) If not in an interrupt handler and the tcb is NOT
+ *       the currently executing task, then again just modify
+ *       the saved xcptcontext structure for the recipient
+ *       task so it will invoke sigdeliver when that task is
+ *       later resumed.
+ *   (3) If not in an interrupt handler and the tcb IS the
+ *       currently executing task -- just call the signal
+ *       handler now.
+ *
+ ****************************************************************************/
+
+void up_schedule_sigaction(_TCB *tcb, sig_deliver_t sigdeliver)
+{
+  /* Refuse to handle nested signal actions */
+
+  sdbg("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
+
+  if (!tcb->xcp.sigdeliver)
+    {
+      irqstate_t flags;
+
+      /* Make sure that interrupts are disabled */
+
+      flags = irqsave();
+
+      /* First, handle some special cases when the signal is
+       * being delivered to the currently executing task.
+       */
+
+      sdbg("rtcb=0x%p current_regs=0x%p\n", g_readytorun.head, current_regs);
+
+      if (tcb == (_TCB*)g_readytorun.head)
+        {
+          /* CASE 1:  We are not in an interrupt handler and
+           * a task is signalling itself for some reason.
+           */
+
+          if (!current_regs)
+            {
+              /* In this case just deliver the signal now. */
+
+              sigdeliver(tcb);
+            }
+
+          /* CASE 2:  We are in an interrupt handler AND the
+           * interrupted task is the same as the one that
+           * must receive the signal, then we will have to modify
+           * the return state as well as the state in the TCB.
+           */
+
+          else
+            {
+              /* Save the return PC and SR and one scratch register
+               * These will be restored by the signal trampoline after
+               * the signals have been delivered.
+               */
+
+              tcb->xcp.sigdeliver    = sigdeliver;
+              tcb->xcp.saved_pc[0]   = current_regs[REG_PC];
+              tcb->xcp.saved_pc[1]   = current_regs[REG_PC+1];
+              tcb->xcp.saved_flg     = current_regs[REG_FLG];
+
+              /* Then set up to vector to the trampoline with interrupts
+               * disabled
+               */
+
+              current_regs[REG_PC]   = (uint32_t)up_sigdeliver >> 8;
+              current_regs[REG_PC+1] = (uint32_t)up_sigdeliver;
+              current_regs[REG_FLG] &= ~M16C_FLG_I;
+
+              /* And make sure that the saved context in the TCB
+               * is the same as the interrupt return context.
+               */
+
+              up_copystate(tcb->xcp.regs, current_regs);
+            }
+        }
+
+      /* Otherwise, we are (1) signaling a task is not running
+       * from an interrupt handler or (2) we are not in an
+       * interrupt handler and the running task is signalling
+       * some non-running task.
+       */
+
+      else
+        {
+          /* Save the return PC and SR and one scratch register
+           * These will be restored by the signal trampoline after
+           * the signals have been delivered.
+           */
+
+          tcb->xcp.sigdeliver     = sigdeliver;
+          tcb->xcp.saved_pc[0]    = tcb->xcp.regs[REG_PC];
+          tcb->xcp.saved_pc[1]    = tcb->xcp.regs[REG_PC+1];
+          tcb->xcp.saved_flg      = tcb->xcp.regs[REG_FLG];
+
+          /* Then set up to vector to the trampoline with interrupts
+           * disabled
+           */
+
+          tcb->xcp.regs[REG_PC]   = (uint32_t)up_sigdeliver >> 8;
+          tcb->xcp.regs[REG_PC+1] = (uint32_t)up_sigdeliver;
+          tcb->xcp.regs[REG_FLG] &= ~M16C_FLG_I;
+        }
+
+      irqrestore(flags);
+    }
+}
+
+#endif /* !CONFIG_DISABLE_SIGNALS */

nuttx/arch/sh/src/m16c/m16c_sigdeliver.c

@@ -0,0 +1,144 @@
+/****************************************************************************
+ * arch/sh/src/m16c/m16c_sigdeliver.c
+ *
+ *   Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <sched.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+
+#include "os_internal.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+#ifndef CONFIG_DISABLE_SIGNALS
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_sigdeliver
+ *
+ * Description:
+ *   This is the a signal handling trampoline.  When a signal action was
+ *   posted.  The task context was mucked with and forced to branch to this
+ *   location with interrupts disabled.
+ *
+ ****************************************************************************/
+
+void up_sigdeliver(void)
+{
+#ifndef CONFIG_DISABLE_SIGNALS
+  _TCB  *rtcb = (_TCB*)g_readytorun.head;
+  uint8_t regs[XCPTCONTEXT_SIZE];
+  sig_deliver_t sigdeliver;
+
+  /* Save the errno.  This must be preserved throughout the signal handling
+   * so that the user code final gets the correct errno value (probably
+   * EINTR).
+   */
+
+  int saved_errno = rtcb->pterrno;
+
+  up_ledon(LED_SIGNAL);
+
+  sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
+        rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
+  ASSERT(rtcb->xcp.sigdeliver != NULL);
+
+  /* Save the real return state on the stack. */
+
+  up_copystate(regs, rtcb->xcp.regs);
+  regs[REG_PC]   = rtcb->xcp.saved_pc[0];
+  regs[REG_PC+1] = rtcb->xcp.saved_pc[1];
+  regs[REG_FLG]  = rtcb->xcp.saved_flg;
+
+  /* Get a local copy of the sigdeliver function pointer.  We do this so
+   * that we can nullify the sigdeliver function pointer in the TCB and
+   * accept more signal deliveries while processing the current pending
+   * signals.
+   */
+
+  sigdeliver           = rtcb->xcp.sigdeliver;
+  rtcb->xcp.sigdeliver = NULL;
+
+  /* Then restore the task interrupt state. */
+
+  irqrestore(rtcb->xcp.saved_flg);
+
+  /* Deliver the signals */
+
+  sigdeliver(rtcb);
+
+  /* Output any debug messages BEFORE restoring errno (because they may
+   * alter errno), then disable interrupts again and restore the original
+   * errno that is needed by the user logic (it is probably EINTR).
+   */
+
+  sdbg("Resuming\n");
+  (void)irqsave();
+  rtcb->pterrno = saved_errno;
+
+  /* Then restore the correct state for this thread of
+   * execution.
+   */
+
+  up_ledoff(LED_SIGNAL);
+  up_fullcontextrestore(regs);
+#endif
+}
+
+#endif /* !CONFIG_DISABLE_SIGNALS */
+

nuttx/arch/sh/src/m16c/m16c_timer.h

@@ -0,0 +1,226 @@
+/************************************************************************************
+ * arch/sh/src/m16c/m16c_timer.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_SH_SRC_M16C_M16C_TIMER_H
+#define __ARCH_SH_SRC_M16C_M16C_TIMER_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Register Bit Definitions *********************************************************/
+
+#define M16C_TA0IC         0x00055    /* Timer A0 interrupt control */
+#define M16C_TA1IC         0x00056    /* Timer A1 interrupt control */
+#define M16C_TA2IC         0x00057    /* Timer A2 interrupt control */
+#define M16C_TA3IC         0x00058    /* Timer A3 interrupt control */
+#define M16C_TA4IC         0x00059    /* Timer A4 interrupt control */
+
+/* Count Start Flag Register (8-bit access) Register */
+
+#define TABSR_TA0S         0x01       /* Bit 0: Timer A0 count start */
+#define TABSR_TA1S         0x02       /* Bit 1: Timer A1 count start */
+#define TABSR_TA2S         0x04       /* Bit 2: Timer A2 count start */
+#define TABSR_TA3S         0x08       /* Bit 3: Timer A3 count start */
+#define TABSR_TA4S         0x10       /* Bit 4: Timer A4 count start */
+#define TABSR_TB0S         0x20       /* Bit 5: Timer B0 count start */
+#define TABSR_TB1S         0x40       /* Bit 6: Timer B1 count start */
+#define TABSR_TB2S         0x80       /* Bit 7: Timer B2 count start */
+
+/* Clock Prescaler Reset Flag Register */
+                                      /* Bits 0-6: Not used */
+#define CPSRF_CPSR         0x80       /* Bit 7: 1=Prescaler is reset */
+
+/* On-Shot Start Flag Register (8-bit access) */
+
+#define ONSF_TA0OS         0x01       /* Bit 0: Timer A0 one shot start */
+#define ONSF_TA1OS         0x02       /* Bit 1: Timer A1 one shot start */
+#define ONSF_TA2OS         0x04       /* Bit 2: Timer A2 one shot start */
+#define ONSF_TA3OS         0x08       /* Bit 3: Timer A3 one shot start */
+#define ONSF_TA4OS         0x10       /* Bit 4: Timer A4 one shot start */
+                                      /* Bit 5: Reserved */
+#define ONSF_TA0TG_MASK    0xc0       /* Bit 6-7: Timer A0 event trigger select bits */
+#define ONSF_TAOTG_INTAON  0x00       /*   00 : Input on TA0IN is selected */
+#define ONSF_TAOTG_TB2OVF  0x40       /*   01 : TB2 overflow is selected */
+#define ONSF_TAOTG_TB4OVF  0x80       /*   10 : TB4 overflow is selected */
+#define ONSF_TAOTG_TB1OVF  0xc0       /*   11 : TB1 overflow is selected */
+
+/* Trigger Select Register */
+
+#define TRGSR_TA1TG_MASK   0x03       /* Bit 0-1: Timer A1 event trigger select bits */
+#define TRGSR_TA1TG_INTAON 0x00       /*   00 : Input on TA1IN is selected */
+#define TRGSR_TA1TG_TB2OVF 0x01       /*   01 : TB2 overflow is selected */
+#define TRGSR_TA1TG_TB4OVF 0x02       /*   10 : TB4 overflow is selected */
+#define TRGSR_TA1TG_TB1OVF 0x03       /*   11 : TB1 overflow is selected */
+#define TRGSR_TA2TG_MASK   0x0c       /* Bit 2-3: Timer A2 event trigger select bits */
+#define TRGSR_TA2TG_INTAON 0x00       /*   00 : Input on TA2IN is selected */
+#define TRGSR_TA2TG_TB2OVF 0x04       /*   01 : TB2 overflow is selected */
+#define TRGSR_TA2TG_TB4OVF 0x08       /*   10 : TB4 overflow is selected */
+#define TRGSR_TA2TG_TB1OVF 0x0c       /*   11 : TB1 overflow is selected */
+#define TRGSR_TA3TG_MASK   0x30       /* Bit 4-5: Timer A3 event trigger select bits */
+#define TRGSR_TA3TG_INTAON 0x00       /*   00 : Input on TA3IN is selected */
+#define TRGSR_TA3TG_TB2OVF 0x10       /*   01 : TB2 overflow is selected */
+#define TRGSR_TA3TG_TB4OVF 0x20       /*   10 : TB4 overflow is selected */
+#define TRGSR_TA3TG_TB1OVF 0x30       /*   11 : TB1 overflow is selected */
+#define TRGSR_TA4TG_MASK   0xc0       /* Bit 6-7: Timer A4 event trigger select bits */
+#define TRGSR_TA4TG_INTAON 0x00       /*   00 : Input on TA4IN is selected */
+#define TRGSR_TA4TG_TB2OVF 0x40       /*   01 : TB2 overflow is selected */
+#define TRGSR_TA4TG_TB4OVF 0x80       /*   10 : TB4 overflow is selected */
+#define TRGSR_TA4TG_TB1OVF 0xc0       /*   11 : TB1 overflow is selected */
+
+/* Up-Down Flag Register */
+
+#define UDF_TA0UD          0x01       /* Bit 0: 1=Timer A0 up count */
+#define UDF_TA1UD          0x02       /* Bit 1: 1=Timer A1 up count */
+#define UDF_TA2UD          0x04       /* Bit 2: 1=Timer A2 up count */
+#define UDF_TA3UD          0x08       /* Bit 3: 1=Timer A3 up count */
+#define UDF_TA4UD          0x10       /* Bit 4: 1=Timer A4 up count */
+#define UDF_TA2P           0x20       /* Bit 5: Timer A2 two-phase pulse signal processing select */
+#define UDF_TA3P           0x40       /* Bit 5: Timer A3 two-phase pulse signal processing select */
+#define UDF_TA4P           0x80       /* Bit 5: Timer A4 two-phase pulse signal processing select */
+
+/* Timer A Registers (16-bit access), simple value range 0000-ffff
+ *                                    (except in PWM mode)
+ */
+
+/* Timer B Registers (16-bit access), simple value range 0000-ffff
+ *                                    (except in Pulse period/pulse width measurement mode)
+ */
+
+/* Timer A Mode Register (8-bit access) */
+
+#define TAnMR_TMOD_MASK    0x03       /* Bits 0-1: Operation mode select */
+#define TAnMR_TMOD_TIMER   0x00       /*   00 : Timer mode */
+#define TAnMR_TMOD_EVENT   0x01       /*   01 : Event counter mode */
+#define TAnMR_TMOD_ONESHOT 0x02       /*   10 : One-shot timer mode */
+#define TAnMR_TMOD_PWM     0x03       /*   11 : Pulse width modulation (PWM) mode */
+#define TAnMR_MR_MASK      0x3c       /* Bits 2-5: Mode function values */
+                                      /* Timer Mode: */
+#define TAnMR_MR_TMNOOUT   0x00       /*   0xx0 : No output */
+#define TAnMR_MR_TMOUT     0x04       /*   0xx1 : Pulse is output */
+#define TAnMR_MR_TMNOGATE  0x00       /*   00xx : Gate function not available */
+#define TAnMR_MR_TMTAINLO  0x10       /*   010x : Timer counts when TAiIN pin is L */
+#define TAnMR_MR_TMTAINHI  0x18       /*   011x : Timer counts when TAiIN pin is H */
+                                      /* Event Counter Mode: */
+#define TAnMR_MR_EC2PHASE  0x10       /*   0100 : Settings required for 2-phase mode */
+#define TAnMR_MR_ECNOOUT   0x00       /*   0xx0 : No output */
+#define TAnMR_MR_ECOUT     0x04       /*   0xx1 : 1=Pulse is output */
+#define TAnMR_MR_ECFALLING 0x00       /*   0x0x : Count polarity falling edge */
+#define TAnMR_MR_ECRISING  0x08       /*   0x1x : Count polarity rising edge */
+#define TAnMR_MR_ECUDC     0x00       /*   00xx : Up/down switching on up/down content */
+#define TAnMR_MR_ECINP     0x10       /*   01xx : Up/down switching on TAnOUT input signal */
+                                      /* One Shot Mode: */
+#define TAnMR_MR_OSNOOUT   0x00       /*   0xx0 : No output */
+#define TAnMR_MR_OSOUT     0x04       /*   0xx1 : Pulse is output */
+#define TAnMR_MR_OSFALLING 0x00       /*   0x0x : TAin falling edge */
+#define TAnMR_MR_OSRISING  0x08       /*   0x1x : TAin rising edge */
+#define TAnMR_MR_OSSFLAG   0x00       /*   00xx : Trigger select one-shot start flag */
+#define TAnMR_MR_OSSTRIG   0x10       /*   01xx : Trigger Selected by event/trigger select bits */
+                                      /* PWM Mode: */
+#define TAnMR_MR_PMFALLING 0x00       /*   xx00 : TAin falling edge */
+#define TAnMR_MR_PMRISING  0x08       /*   xx10 : TAin rising edge */
+#define TAnMR_MR_PMSFLAG   0x00       /*   x0x0 : Trigger select one-shot start flag */
+#define TAnMR_MR_PMTRIG    0x10       /*   x1x0 : Trigger Selected by event/trigger select bits */
+#define TAnMR_MR_PM16BIT   0x00       /*   0xx0 : Functions as a 16-bit pulse width modulator */
+#define TAnMR_MR_PM8BIT    0x20       /*   1xx0 : Functions as an 8-bit pulse width modul */
+#define TAnMR_TCK_MASK     0xc0       /* Bits 6-7: Count source select */
+                                      /* Timer Mode: */
+#define TAnMR_TCK_TMF1     0x00       /*   00: f1 or f2 */
+#define TAnMR_TCK_TMF8     0x40       /*   01: f8 */
+#define TAnMR_TCK_TMF32    0x80       /*   10: f32 */
+#define TAnMR_TCK_TMFC32   0xc0       /*   11: fc32 */
+                                      /* Event Counter Mode: */
+#define TAnMR_TCK_ECRELOAD 0x00       /*   x0: Reload count operation*/
+#define TAnMR_TCK_ECFRUN   0x40       /*   x1: Free run count operation*/
+#define TAnMR_TCK_ECNORMAL 0x00       /*   0x: Normal processing operation */
+#define TAnMR_TCK_ECMUL4   0x80       /*   1x: Multiply-by-4 processing operation */
+                                      /* One Shot Mode: */
+#define TAnMR_TCK_OSF1     0x00       /*   00: f1 or f2 */
+#define TAnMR_TCK_OSF8     0x40       /*   01: f8 */
+#define TAnMR_TCK_OSF32    0x80       /*   10: f32 */
+#define TAnMR_TCK_OSFC32   0xc0       /*   11: fc32 */
+                                      /* PWM Mode: */
+#define TAnMR_TCK_PMF1     0x00       /*   00: f1 or f2 */
+#define TAnMR_TCK_PMF8     0x40       /*   01: f8 */
+#define TAnMR_TCK_PMF32    0x80       /*   10: f32 */
+#define TAnMR_TCK_PMFC32   0xc0       /*   11: fc32 */
+
+/* Timer B Mode Register (8-bit access) */
+
+#define TBnMR_TMOD_MASK    0x03       /* Bits 0-1: Operation mode select */
+#define TBnMR_TMOD_TIMER   0x00       /*   00 : Timer mode */
+#define TBnMR_TMOD_EVENT   0x01       /*   01 : Event counter mode */
+#define TBnMR_TMOD_PWM     0x02       /*   10 : Pulse period/pulse width measurement mode */
+#define TBnMR_MR_MASK      0x3c       /* Bits 2-5: Mode function values */
+                                      /* Timer Mode: */
+#define TBnMR_MR_TM        0x00       /*   0000 : Required bit settings for timer mode */
+                                      /* Event Counter Mode: */
+#define TBnMR_MR_ECFALLING 0x00       /*   0000 : Counts external signal's falling edges */
+#define TBnMR_MR_ECRISING  0x04       /*   0001 : Counts external signal's rising edges */
+#define TBnMR_MR_ECXTFALL  0x00       /*   0010 : Counts external signal's falling and rising edges */
+                                      /* Pulse period/pulse width measurement mode: */
+#define TBnMR_MR_PMFALLING 0x00       /*   0000 : Period between falling edge to falling edge */
+#define TBnMR_MR_PMRISING  0x08       /*   0001 : Period between rising edge to rising edge */
+#define TBnMR_MR_PMSVAL    0x00       /*   0010 : Width between edge(s) to edge(s) */
+#define TBnMR_TCK_MASK     0xc0       /* Bits 6-7: Count source select */
+                                      /* Timer Mode: */
+#define TBnMR_TCK_TMF1     0x00       /*   00: f1 or f2 */
+#define TBnMR_TCK_TMF8     0x40       /*   01: f8 */
+#define TBnMR_TCK_TMF32    0x80       /*   10: f32 */
+#define TBnMR_TCK_TMFC32   0xc0       /*   11: fc32 */
+                                      /* Event Counter Mode: */
+#define TBnMR_TCK_ECTBIN   0x00       /*   00: Input from TBnIN pin */
+#define TBnMR_TCK_ECTBOVF  0x80       /*   10: TBj overflow */
+                                      /* Pulse period/pulse width measurement mode: */
+#define TBnMR_TCK_PMF1     0x00       /*   00: f1 or f2 */
+#define TBnMR_TCK_PMF8     0x40       /*   01: f8 */
+#define TBnMR_TCK_PMF32    0x80       /*   10: f32 */
+#define TBnMR_TCK_PMFC32   0xc0       /*   11: fc32 */
+
+/************************************************************************************
+ * Global Data
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ARCH_SH_SRC_M16C_M16C_TIMER_H */

nuttx/arch/sh/src/m16c/m16c_timerisr.c

@@ -0,0 +1,186 @@
+/****************************************************************************
+ * arch/sh/src/m16c/m16c_timerisr.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <time.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <arch/board/board.h>
+
+#include "clock_internal.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+#include "m16c_timer.h"
+
+/****************************************************************************
+ * Preprocessor Definitions
+ ****************************************************************************/
+/* Configuration */
+
+#ifndef M16C_TA0_PRIO              /* Timer A0 interrupt priority */
+#  define M16C_TA0_PRIO   5
+#endif
+
+/* Determine the ideal preload value for the timer.
+ *
+ * For example, given a 20MHz input frequency and a desired 100 Hz, clock,
+ * the ideal reload value would be:
+ *
+ *  20,000,000 / 100 = 200,000
+ *
+ * The ideal prescaler value would be the one, then that drops this to exactly
+ * 66535:
+ *
+ *  M16C_IDEAL_PRESCALER = 200,000 / 65535 = 3.05
+ *
+ * And any value greater than 3.05 would also work with less and less precision.
+ * The following calculation will produce the ideal prescaler as the next integer
+ * value above any fractional values:
+ */
+
+#define M16C_DIVISOR (65535 * CLK_TCK)
+#define M16C_IDEAL_PRESCALER \
+	((M16C_XIN_FREQ + M16C_DIVISOR - 1) / M16C_DIVISOR)
+
+/* Now, given this idel prescaler value, pick between available choices: 1, 8, and 32 */
+
+#if M16C_IDEAL_PRESCALER > 8
+#  define M16C_PRESCALE_VALUE 32
+#  define M16C_PRESCALE_BITS TAnMR_TCK_TMF32
+#elif M16C_IDEL_PRESCALER > 1
+#  define M16C_PRESCALE_VALUE 8
+#  define M16C_PRESCALE_BITS TAnMR_TCK_TMF8
+#else
+#  define M16C_PRESCALE_VALUE 1
+#  define M16C_PRESCALE_BITS TAnMR_TCK_TMF1
+#endif
+
+/* Timer 0 Mode Settings */
+
+#define M16C_TA0MODE_CONFIG \
+	(TAnMR_TMOD_TIMER|TAnMR_MR_TMNOOUT|TAnMR_MR_TMNOGATE|M16C_PRESCALE_BITS)
+
+/* The actual reload value matching the selected prescaler value */
+
+#define M16C_RELOAD_VALUE \
+	((M16C_XIN_FREQ / M16C_PRESCALE_VALUE / CLK_TCK)  - 1)
+
+/****************************************************************************
+ * Private Type Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Global Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function:  up_timerisr
+ *
+ * Description:
+ *   The timer ISR will perform a variety of services for various portions
+ *   of the systems.
+ *
+ ****************************************************************************/
+
+int up_timerisr(int irq, uint32_t *regs)
+{
+   /* Process timer interrupt */
+
+   sched_process_timer();
+   return 0;
+}
+
+/****************************************************************************
+ * Function:  up_timerinit
+ *
+ * Description:
+ *   This function is called during start-up to initialize
+ *   the timer interrupt.
+ *
+ ****************************************************************************/
+
+void up_timerinit(void)
+{
+  /* Make sure that no timers are running and that all timer interrupts are
+   * disabled.
+   */
+
+  putreg8(0, M16C_TABSR);
+  putreg8(0, M16C_TA0IC);
+  putreg8(0, M16C_TA1IC);
+  putreg8(0, M16C_TA2IC);
+  putreg8(0, M16C_TA3IC);
+  putreg8(0, M16C_TA4IC);
+  putreg8(0, M16C_TB0IC);
+  putreg8(0, M16C_TB1IC);
+  putreg8(0, M16C_TB2IC);
+
+  /* Set up timer 0 mode register for timer mode with the calculated prescaler value */
+ 
+  putreg8(M16C_TA0MODE_CONFIG, M16C_TA0MR);
+
+  /* Set the calculated reload value */
+
+  putreg16(M16C_RELOAD_VALUE, M16C_TA0);
+ 
+  /* Attach the interrupt handler */
+
+  irq_attach(M16C_SYSTIMER_IRQ, (xcpt_t)up_timerisr);
+
+  /* Enable timer interrupts */
+
+  putreg8(1, M16C_TA0IC);
+  
+  /* Set the interrupt priority */
+
+  putreg8(M16C_TA0_PRIO, M16C_TA0IC);
+
+  /* Start the timer */
+
+  putreg8(TABSR_TA0S, M16C_TABSR);
+}

nuttx/arch/sh/src/m16c/m16c_uart.h

@@ -0,0 +1,145 @@
+/************************************************************************************
+ * arch/sh/src/m16c/m16c_uart.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_SH_SRC_M16C_M16C_UART_H
+#define __ARCH_SH_SRC_M16C_M16C_UART_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* UART Register Block Base Addresses ***********************************************/
+
+#define M16C_UART0_BASE    0x003a0    /* First UART0 register */
+#define M16C_UART1_BASE    0x003a8    /* First UART1 register */
+#define M16C_UART2_BASE    0x00378    /* First UART2 register (ignoring special regs) */
+
+/* UART Register Offsets ************************************************************/
+
+#define M16C_UART_MR       0x00       /*  8-bit UART transmit/receive mode  */
+#define M16C_UART_BRG      0x01       /*  8-bit UART bit rate generator    */
+#define M16C_UART_TB       0x02       /* 16-bit UART transmit buffer  */
+#define M16C_UART_C0       0x04       /*  8-bit UART transmit/receive control 0  */
+#define M16C_UART_C1       0x05       /*  8-bit UART transmit/receive control 1  */
+#define M16C_UART_RB       0x06       /* 16-bit UART receive buffer  */
+
+/* UART Register Bit Definitions ****************************************************/
+
+/* UART transmit/receive mode */
+
+#define UART_MR_SMDMASK    0x07       /* Serial I/O mode select */
+#define UART_MR_SMDINVALID 0x00       /*  000: Serial I/O invalid */
+#define UART_MR_SMDSYNCH   0x01       /*  001: Required in Sync Mode (UART0/1) Serial I/O (UART2) */
+#define UART_MR_SMDINHIB1  0x02       /*  010: Inhibited (UART0/1) I2C mode (UART2) */
+#define UART_MR_SMDINHIB2  0x03       /*  011: Inhibited */
+#define UART_MR_SMD7BITS   0x04       /*  100: Transfer data 7 bits long */
+#define UART_MR_SMD8BITS   0x05       /*  101: Transfer data 8 bits long */
+#define UART_MR_SMD9BITS   0x06       /*  110: Transfer data 9 bits long */
+#define UART_MR_SMDINHIB3  0x07       /*  111: Inhibited */
+#define UART_MR_CKDIR      0x08       /* Bit 3: Internal/external clock select 1=external */
+#define UART_MR_STPS       0x10       /* Bit 4: Stop bit length select 1=2 stop bits */
+#define UART_MR_PRY        0x20       /* Bit 5: Odd/even parity select bit 1=Even parity */
+#define UART_MR_PRYE       0x40       /* Bit 6: Parity enable 1=enabled */
+#define UART_MR_IOPOL      0x80       /* Bit 7: Reserved (UART0/1) Tx/Rx polarity reverse (UART2) */
+
+/* UART receive buffer register (16-bit) */
+
+#define UART_RB_DATAMASK   0x01ff     /* Bits 0-8: Receive data */
+                                      /* Bits 9-10: Reserved */
+#define UART_RB_ABT        0x0800     /* Bit 11: Arbitration lost detecting flag */
+#define UART_RB_OER        0x1000     /* Bit 12: Overrun error flag */
+#define UART_RB_FER        0x2000     /* Bit 13: Framing error flag */
+#define UART_RB_PER        0x4000     /* Bit 14: Parity error flag */
+#define UART_RB_SUM        0x8000     /* Bit 15: Error sum flag */
+
+/* UART Transmit/Receive Control 0 */
+
+#define UART_C0_CLKMASK    0x02       /* Bits 0-1: BRG count source select */
+#define UART_C0_F1SIO      0x00       /*   00 : f1SIO or f2SIO is selected */
+#define UART_C0_F8SIO      0x01       /*   01 : f8SIO is selected */
+#define UART_C0_F32SIO     0x02       /*   10 : f32SIO is selected */
+#define UART_C0_INHIB      0x03       /*   11 : Inhibited */
+#define UART_C0_CRS        0x04       /* Bit 2: CTS/RTS function select 1=RTS */
+#define UART_C0_TXEPT      0x08       /* Bit 3: Transmit register empty 1=empty */
+#define UART_C0_CRD        0x10       /* Bit 4: CTS/RTS disable bit 1=CTS/RTS disabled */
+#define UART_C0_NCH        0x20       /* Bit 5: Data output select 1=TxDi is N-channel open drain output */
+#define UART_C0_CKPOL      0x40       /* Bit 6: CLK polarity select 1=XMT rising, recieve falling */
+#define UART_C0_UFORM      0x80       /* Bit 7: Transfer format select 1=MSB first */
+
+/* UART Transmit/Receive Control 1 */
+
+#define UART_C1_TE         0x01       /* Bit 0: Transmit enable 1=enable */
+#define UART_C1_TI         0x02       /* Bit 1: Transmit buffer empty 1=empty */
+#define UART_C1_RE         0x04       /* Bit 2: Receive enable 1=enable */
+#define UART_C1_RI         0x08       /* Bit 3: Receive complete 1=data in read buffer */
+                                      /* The following are only defined for UART2: */
+#define UART_C1_U2IRS      0x10       /* Bit 4: UART2 transmit interrupt cause select */
+#define UART_C1_U2RRM      0x20       /* Bit 5: UART2 continuous receive mode enable */
+#define UART_C1_U2LCH      0x40       /* Bit 6: UART2 Data logic select */
+#define UART_C1_U2ERE      0x80       /* Bit 7: UART2 Error signal output enable */
+
+/* UART2 Transmit/Receive Control 2 */
+
+#define UART_CON_U0IRS      0x01       /* Bit 0: UART0 transmit interrupt cause select */
+#define UART_CON_U1IRS      0x02       /* Bit 1: UART1 transmit interrupt cause select */
+#define UART_CON_U0RRM      0x04       /* Bit 2: UART0 continuous receive mode enable */
+#define UART_CON_U1RRM      0x08       /* Bit 3: UART1 continuous receive mode enable */
+#define UART_CON_CLKMD0     0x10       /* Bit 4: CLK/CLKS select bit 0 */
+#define UART_CON_CLKMD1     0x20       /* Bit 5: CLK/CLKS select bit  */
+#define UART_CON_RCSP       0x40       /* Bit 6: Separate CTS/RTS bit */
+                                       /* Bit 7: Reserved */
+/* UART2 special mode register 1 (to be provided) */
+
+/* UART2 special mode register 2 (to be provided) */
+
+/* UART2 special mode register 3 (to be provided) */
+
+/* UART2 special mode register 4 (to be provided) */
+
+/************************************************************************************
+ * Global Data
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ARCH_SH_SRC_M16C_M16C_UART_H */

nuttx/arch/sh/src/m16c/m16c_vectors.S

@@ -0,0 +1,523 @@
+/************************************************************************************
+ * arch/sh/src/m16c/m16c_vectors.S
+ *
+ *	 Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *	 Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *		notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *		notice, this list of conditions and the following disclaimer in
+ *		the documentation and/or other materials provided with the
+ *		distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *		used to endorse or promote products derived from this software
+ *		without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/irq.h>
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Macro Definitions
+ ************************************************************************************/
+
+/* Select register bank 1, and pass the IRQ number to _m16c_commonvector */
+
+	.macro	m16c_vector, label, irqno
+\label:
+	fset	b
+	mov.w	#\irqno, r1
+	jmp.w	_m16c_commonvector
+	.endm
+
+/* Special page vectors. This macro puts the jump address of	
+ * functions defined as special page into the special page vector table.
+ * See example calls below and see the M16C Software Manual or NC30
+ * manual for more information on special page vectors.
+ */
+#if 0
+ 	.macro	m16c_special, num
+	.org	0x0ffffe-(\num*2)
+	.globl	__SPECIAL_\num
+	.word	__SPECIAL_\num	& 0x0ffff
+	.endm
+#endif
+
+/************************************************************************************
+ * Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Interrupt Vectors
+ ************************************************************************************/
+
+/* Variable vector section */
+
+	.section varvects			/* Variable vector table */
+	.long	_m16c_brk_isr			/* ffd00: BRK instruction */
+	.long	0xffffffff			/* ffd04 */
+	.long	0xffffffff			/* ffd08 */
+	.long	0xffffffff			/* ffd0c */
+	.long	_m16c_int3_isr			/* ffd10: INT3 */
+	.long	_m16c_contextsave		/* ffd14: Reserved -- SWINT5 used by NuttX */
+#ifdef CONFIG_M16C_SWINTS
+	.long	_m16c_swint6_isr		/* ffd18: S/W interrupt 7 */
+	.long	_m16c_swint7_isr		/* ffd1c: S/W interrupt 7 */
+#else
+	.long	_m16c_unexpected_isr		/* ffd1c: Reserved */
+	.long	_m16c_unexpected_isr		/* ffd1c: Reserved */
+#endif
+	.long	_m16c_int5_isr			/* ffd20: INT5 */
+	.long	_m16c_int4_isr			/* ffd24: INT4 */
+	.long	_m16c_uart2bcd_isr		/* ffd28: UART2 bus collision detection */
+	.long	_m16c_dma0_isr			/* ffd2c: DMA0 */
+	.long	_m16c_dma1_isr			/* ffd30: DMA1 */
+	.long	_m16c_keyinp_isr		/* ffd34: Key input interrupt */
+	.long	_m16c_adc_isr			/* ffd38: A-D */
+	.long	_m16c_uart2xmitnack2_isr	/* ffd3c UART2 transmit/NACK2 */
+	.long	_m16c_uart2rcvack2_isr		/* ffd40: UART2 receive/ACK2 */
+	.long	_m16c_uart0xmit_isr		/* ffd44: UART0 transmit */
+	.long	_m16c_uart0rcv_isr		/* ffd48: UART0 receive */
+	.long	_m16c_uart1xmit_isr		/* ffd4c: UART1 transmit */
+	.long	_m16c_uart1rcv_isr		/* ffd50: UART1 receive */
+	.long	_m16c_tmra0_isr			/* ffd54: Timer A0 */
+	.long	_m16c_tmra1_isr			/* ffd58: Timer A1 */
+	.long	_m16c_tmra2_isr			/* ffd5c: Timer A2 */
+	.long	_m16c_tmra3_isr			/* ffd60: Timer A3 */
+	.long	_m16c_tmra4_isr			/* ffd64: Timer A4 */
+	.long	_m16c_tmrb0_isr			/* ffd68: Timer B0 */
+	.long	_m16c_tmrb1_isr			/* ffd6c: Timer B1 */
+	.long	_m16c_tmrb2_isr			/* ffd70: Timer B2 */
+	.long	_m16c_int0_isr			/* ffd74: INT0 */
+	.long	_m16c_int1_isr			/* ffd78: INT1 */
+#ifdef CONFIG_M16C_SWINTS
+	.long	_m16c_swint31_isr		/* ffd7c: S/W interrupt 31 */
+	.long	_m16c_contextrestore		/* ffd80: S/W interrupt 32 by NuttX */
+	.long	_m16c_swint33_isr		/* ffd84: S/W interrupt 33 */
+	.long	_m16c_swint34_isr		/* ffd88: S/W interrupt 34 */
+	.long	_m16c_swint35_isr		/* ffd8c: S/W interrupt 35 */
+	.long	_m16c_swint36_isr		/* ffd90: S/W interrupt 36 */
+	.long	_m16c_swint37_isr		/* ffd94: S/W interrupt 37 */
+	.long	_m16c_swint38_isr		/* ffd98: S/W interrupt 38 */
+	.long	_m16c_swint39_isr		/* ffd9c: S/W interrupt 39 */
+	.long	_m16c_swint40_isr		/* ffda0: S/W interrupt 40 */
+	.long	_m16c_swint41_isr		/* ffda4: S/W interrupt 41 */
+	.long	_m16c_swint42_isr		/* ffda8: S/W interrupt 42 */
+	.long	_m16c_swint43_isr		/* ffdac: S/W interrupt 43 */
+	.long	_m16c_swint44_isr		/* ffdb0: S/W interrupt 44 */
+	.long	_m16c_swint45_isr		/* ffdb4: S/W interrupt 45 */
+	.long	_m16c_swint46_isr		/* ffdb8: S/W interrupt 46 */
+	.long	_m16c_swint47_isr		/* ffdbc: S/W interrupt 47 */
+	.long	_m16c_swint48_isr		/* ffdc0: S/W interrupt 48 */
+	.long	_m16c_swint49_isr		/* ffdc4: S/W interrupt 49 */
+	.long	_m16c_swint50_isr		/* ffdc8: S/W interrupt 50 */
+	.long	_m16c_swint51_isr		/* ffdcc: S/W interrupt 51 */
+	.long	_m16c_swint52_isr		/* ffdd0: S/W interrupt 52 */
+	.long	_m16c_swint53_isr		/* ffdd4: S/W interrupt 53 */
+	.long	_m16c_swint54_isr		/* ffdd8: S/W interrupt 54 */
+	.long	_m16c_swint55_isr		/* ffddc: S/W interrupt 55 */
+	.long	_m16c_swint56_isr		/* ffde0: S/W interrupt 56 */
+	.long	_m16c_swint57_isr		/* ffde4: S/W interrupt 57 */
+	.long	_m16c_swint58_isr		/* ffde8: S/W interrupt 58 */
+	.long	_m16c_swint59_isr		/* ffdec: S/W interrupt 59 */
+	.long	_m16c_swint60_isr		/* ffdf0: S/W interrupt 60 */
+	.long	_m16c_swint61_isr		/* ffdf4: S/W interrupt 61 */
+	.long	_m16c_swint62_isr		/* ffdf8: S/W interrupt 62 */
+	.long	_m16c_swint63_isr		/* ffdfc: S/W interrupt 63 */
+#else
+	.long	_m16c_unexpected_isr		/* ffd7c: Reserved */
+	.long	_m16c_contextrestore		/* ffd80: S/W interrupt 32 by NuttX */
+	.long	_m16c_unexpected_isr		/* ffd84: Not supported */
+	.long	_m16c_unexpected_isr		/* ffd88: Not supported */
+	.long	_m16c_unexpected_isr		/* ffd8c: Not supported */
+	.long	_m16c_unexpected_isr		/* ffd90: Not supported */
+	.long	_m16c_unexpected_isr		/* ffd94: Not supported */
+	.long	_m16c_unexpected_isr		/* ffd98: Not supported */
+	.long	_m16c_unexpected_isr		/* ffd9c: Not supported */
+	.long	_m16c_unexpected_isr		/* ffda0: Not supported */
+	.long	_m16c_unexpected_isr		/* ffda4: Not supported1 */
+	.long	_m16c_unexpected_isr		/* ffda8: Not supported */
+	.long	_m16c_unexpected_isr		/* ffdac: Not supported */
+	.long	_m16c_unexpected_isr		/* ffdb0: Not supported */
+	.long	_m16c_unexpected_isr		/* ffdb4: Not supported */
+	.long	_m16c_unexpected_isr		/* ffdb8: Not supported */
+	.long	_m16c_unexpected_isr		/* ffdbc: Not supported */
+	.long	_m16c_unexpected_isr		/* ffdc0: Not supported */
+	.long	_m16c_unexpected_isr		/* ffdc4: Not supported */
+	.long	_m16c_unexpected_isr		/* ffdc8: Not supported */
+	.long	_m16c_unexpected_isr		/* ffdcc: Not supported */
+	.long	_m16c_unexpected_isr		/* ffdd0: Not supported */
+	.long	_m16c_unexpected_isr		/* ffdd4: Not supported */
+	.long	_m16c_unexpected_isr		/* ffdd8: Not supported */
+	.long	_m16c_unexpected_isr		/* ffddc: Not supported */
+	.long	_m16c_unexpected_isr		/* ffde0: Not supported */
+	.long	_m16c_unexpected_isr		/* ffde4: Not supported */
+	.long	_m16c_unexpected_isr		/* ffde8: Not supported */
+	.long	_m16c_unexpected_isr		/* ffdec: Not supported */
+	.long	_m16c_unexpected_isr		/* ffdf0: Not supported */
+	.long	_m16c_unexpected_isr		/* ffdf4: Not supported */
+	.long	_m16c_unexpected_isr		/* ffdf8: Not supported */
+	.long	_m16c_unexpected_isr		/* ffdfc: Not supported */
+#endif
+
+/* Fixed vector section
+ *
+ * The fixed vector table begins at address ffe00.  The firt portion
+ * of the fixed vector table is the special page table.  This table
+ * is not currently used.
+ */
+ 	.section specpg				/* Special page table */
+ /* Nothing */
+	.section fixvects			/* Fixed vector table */
+	.long	_m16c_undefinst_irq		/* fffdc: Undefined instruction */
+	.long	_m16c_overflow_irq		/* fffe0: Overflow */
+	.long	_m16c_brkinst_irq		/* fffe4: BRK instruction */
+	.long	_m16c_addrmatch_irq		/* fffe8: Address match */
+#ifdef CONFIG_M16C_DEBUGGER
+	.long	_m16c_sstep_irq			/* fffec: Single step */
+#else
+	.long	_m16c_unexpected_isr		/* fffec: Not supported */
+#endif
+	.long	_m16c_wdog_irq			/* ffff0: Watchdog timer */
+#ifdef CONFIG_M16C_DEBUGGER
+	.long	_m16c_dbc_irq			/* ffff4: DBC */
+#else
+	.long	_m16c_unexpected_isr		/* ffff4: Not supported */
+#endif
+	.long	_m16c_nmi_irq			/* ffff8: NMI */
+	.long	__start				/* ffffc: Reset */
+
+/************************************************************************************
+ * Code
+ ************************************************************************************/
+/************************************************************************************
+ * Name: m16c_*isr
+ *
+ * Description:
+ *   Handler interrupt events. The CPU performs the following actions when an
+ *   interrupt is taken:
+ *
+ *  - Save FLG register
+ *  - Clear I, D, and U flags in FLG register
+ *  - Builds stack frame like (on the push-down, interrupt stack):
+ * 
+ *    sp   -> PC bits 0-7
+ *    sp+1 -> PC bits 8-15
+ *    sp+2 -> FLG bits 0-7
+ *    sp+3 -> FLG (Bits 12-14) + PC (bits 16-19)
+ *
+ *  - Sets IPL
+ *  - Vectors to interrupt handler
+ *
+ ************************************************************************************/
+
+ 	.text
+/* The unexpected interrupt vector */
+
+ 	m16c_vector	_m16c_unexpected_isr, NR_IRQS
+
+ /* Variable vectors */
+ 
+	m16c_vector	_m16c_brk_isr, M16C_BRK_IRQ
+	m16c_vector	_m16c_int3_isr, M16C_INT3_IRQ
+	m16c_vector	_m16c_int5_isr, M16C_INT5_IRQ
+	m16c_vector	_m16c_int4_isr, M16C_INT4_IRQ
+	m16c_vector	_m16c_uart2bcd_isr, M16C_UART2BCD_IRQ
+	m16c_vector	_m16c_dma0_isr, M16C_DMA0_IRQ
+	m16c_vector	_m16c_dma1_isr, M16C_DMA1_IRQ
+	m16c_vector	_m16c_keyinp_isr, M16C_KEYINP_IRQ
+	m16c_vector	_m16c_adc_isr, M16C_ADC_IRQ
+	m16c_vector	_m16c_uart2xmitnack2_isr, M16C_UARTXNAK_IRQ
+	m16c_vector	_m16c_uart2rcvack2_isr, M16C_UARTRACK_IRQ
+	m16c_vector	_m16c_uart0xmit_isr, M16C_UART0XMT_IRQ
+	m16c_vector	_m16c_uart0rcv_isr, M16C_UART0RCV_IRQ
+	m16c_vector	_m16c_uart1xmit_isr, M16C_UART1XMT_IRQ
+	m16c_vector	_m16c_uart1rcv_isr, M16C_UART1RCV_IRQ
+	m16c_vector	_m16c_tmra0_isr, M16C_TMRA0_IRQ
+	m16c_vector	_m16c_tmra1_isr, M16C_TMRA1_IRQ
+	m16c_vector	_m16c_tmra2_isr, M16C_TMRA2_IRQ
+	m16c_vector	_m16c_tmra3_isr, M16C_TMRA3_IRQ
+	m16c_vector	_m16c_tmra4_isr, M16C_TMRA4_IRQ
+	m16c_vector	_m16c_tmrb0_isr, M16C_TMRB0_IRQ
+	m16c_vector	_m16c_tmrb1_isr, M16C_TMRB1_IRQ
+	m16c_vector	_m16c_tmrb2_isr, M16C_TMRB2_IRQ
+	m16c_vector	_m16c_int0_isr, M16C_INT0_IRQ
+	m16c_vector	_m16c_int1_isr, M16C_INT1_IRQ
+
+#ifdef CONFIG_M16C_SWINTS
+	m16c_vector	_m16c_swint5_isr, M16C_SWINT5_IRQ
+	m16c_vector	_m16c_swint6_isr, M16C_SWINT6_IRQ
+	m16c_vector	_m16c_swint7_isr, M16C_SWINT7_IRQ
+	m16c_vector	_m16c_swint31_isr, M16C_SWINT31_IRQ
+	m16c_vector	_m16c_swint32_isr, M16C_SWINT32_IRQ
+	m16c_vector	_m16c_swint33_isr, M16C_SWINT33_IRQ
+	m16c_vector	_m16c_swint34_isr, M16C_SWINT34_IRQ
+	m16c_vector	_m16c_swint35_isr, M16C_SWINT35_IRQ
+	m16c_vector	_m16c_swint36_isr, M16C_SWINT36_IRQ
+	m16c_vector	_m16c_swint37_isr, M16C_SWINT37_IRQ
+	m16c_vector	_m16c_swint38_isr, M16C_SWINT38_IRQ
+	m16c_vector	_m16c_swint39_isr, M16C_SWINT39_IRQ
+	m16c_vector	_m16c_swint40_isr, M16C_SWINT40_IRQ
+	m16c_vector	_m16c_swint41_isr, M16C_SWINT41_IRQ
+	m16c_vector	_m16c_swint42_isr, M16C_SWINT42_IRQ
+	m16c_vector	_m16c_swint43_isr, M16C_SWINT43_IRQ
+	m16c_vector	_m16c_swint44_isr, M16C_SWINT44_IRQ
+	m16c_vector	_m16c_swint45_isr, M16C_SWINT45_IRQ
+	m16c_vector	_m16c_swint46_isr, M16C_SWINT46_IRQ
+	m16c_vector	_m16c_swint47_isr, M16C_SWINT47_IRQ
+	m16c_vector	_m16c_swint48_isr, M16C_SWINT48_IRQ
+	m16c_vector	_m16c_swint49_isr, M16C_SWINT49_IRQ
+	m16c_vector	_m16c_swint50_isr, M16C_SWINT50_IRQ
+	m16c_vector	_m16c_swint51_isr, M16C_SWINT51_IRQ
+	m16c_vector	_m16c_swint52_isr, M16C_SWINT52_IRQ
+	m16c_vector	_m16c_swint53_isr, M16C_SWINT53_IRQ
+	m16c_vector	_m16c_swint54_isr, M16C_SWINT54_IRQ
+	m16c_vector	_m16c_swint55_isr, M16C_SWINT55_IRQ
+	m16c_vector	_m16c_swint56_isr, M16C_SWINT56_IRQ
+	m16c_vector	_m16c_swint57_isr, M16C_SWINT57_IRQ
+	m16c_vector	_m16c_swint58_isr, M16C_SWINT58_IRQ
+	m16c_vector	_m16c_swint59_isr, M16C_SWINT59_IRQ
+	m16c_vector	_m16c_swint60_isr, M16C_SWINT60_IRQ
+	m16c_vector	_m16c_swint61_isr, M16C_SWINT61_IRQ
+	m16c_vector	_m16c_swint62_isr, M16C_SWINT62_IRQ
+	m16c_vector	_m16c_swint63_isr, M16C_SWINT63_IRQ
+#endif
+
+/* Fixed vectors */
+
+	m16c_vector	_m16c_undefinst_irq, M16C_UNDEFINST_IRQ
+	m16c_vector	_m16c_overflow_irq, M16C_OVERFLOW_IRQ
+	m16c_vector	_m16c_brkinst_irq, M16C_BRK_IRQ
+	m16c_vector	_m16c_addrmatch_irq, M16C_ADDRMATCH_IRQ
+	m16c_vector	_m16c_wdog_irq, M16C_WDOG_IRQ
+	m16c_vector	_m16c_nmi_irq, M16C_NMI_IRQ
+#ifdef CONFIG_M16C_DEBUGGER
+	m16c_vector	_m16c_sstep_irq, M16C_SSTEP_IRQ
+	m16c_vector	_m16c_dbc_irq, M16C_DBC_IRQ
+#endif
+
+/* At this point, the stack remains as it was on interrupt.  The interrupt
+ * stack is selected, register bank 1 is selected and r1 holds the IRQ
+ * number.
+ */
+
+_m16c_commonvector:
+
+/* At this point, the interrupt stack has 4 bytes of info on it. */
+
+/* Save all registers on the interrupt stack */
+
+	fclr	b				/* Switch back to Bank 0 */
+	pushm	fb,sb,a1,a0,r3,r2,r1,r0		/* Save on interrupt stack */
+	fset	b				/* Bank to bank 1 */
+
+/* Save the user stack pointer on the interrupt stack */
+
+	fset	u				/* Switch to User stack */
+	stc	sp, r0				/* R0 = user stack pointer */
+	fclr	u				/* Back to interrupt stack */
+	push.w	r0				/* Save user sp on isp */
+
+/* Allow nested interrupts */
+
+#ifdef M16C_INTERRUPT_IPL
+	fset	i				/* Enable interrupts */
+	ldipl	#M16C_INTERRUPT_IPL		/* Set interrupt level */
+#endif
+
+/* Then call _up_doirq with r1=IRQ number, r2=address of context info.  At this
+ * point, the interrupt stack holds the address of the last byte of the context
+ * info array
+ */
+
+ 	stc	isp, r2				/* R2 = address of base of context info */
+	jsr.a	_up_doirq
+
+#ifdef M16C_INTERRUPT_IPL
+	fclr	i				/* Disable interrupts */
+#endif
+
+/* Upon return, r0 will hold address of the base of the new context info structure
+ * use for return.  Most of the time this will be the same as the address passed to
+ * to _up_doirg above, but will differ if a context switch occurs during interrupt
+ * processing.
+ *
+ * Of the ISP to the end of the context array:
+ */
+ 
+ 	ldc	r0, isp				/* ISP = address of base of new context info */
+ 
+ /* Restore the user stack pointer */
+ 
+ 	pop.w	r0				/* R0 = saved user stack pointer */
+	fset	u				/* Switch to User stack */
+	ldc	r0, sp				/* Restore the user stack pointer */
+	fclr	u				/* Back to interrupt stack */
+ 	
+/* Recover all registers and return */
+
+	fclr	b				/* Switch back to Bank 0 */
+	popm	fb,sb,a1,a0,r3,r2,r1,r0		/* Recover registers */
+	reit					/* Return from interrupt */
+
+/************************************************************************************
+ * Name: int up_saveusercontext(uint32_t *regs)
+ *
+ * Description:
+ *   Save the context of the calling function at the point of the return from the
+ *   call.  This basically a setjmp.
+ *
+ * Input Parameters:
+ *   R1 = Address of register save array
+ *
+ * Returned Value:
+ *   R0 = 0 on normal call; 1 on context switch
+ *
+ ************************************************************************************/
+
+	.globl	_up_saveusercontext
+	.type	_up_saveusercontext, #function
+
+_up_saveusercontext:
+	int	#5		/* Execute S/W interrupt 5 */
+	rts			/* Then return with the correct value in r0 */
+
+/* This the logic executes in response to S/W interrupt 5.  The 'int 5' instruction
+ * will cause the following actions:
+ *
+ *  - Save FLG register
+ *  - Clear I, D, and U flags in FLG register
+ *  - Builds stack frame like (on the push-down, interrupt stack):
+ * 
+ *    sp   -> PC bits 0-7
+ *    sp+1 -> PC bits 8-15
+ *    sp+2 -> FLG bits 0-7
+ *    sp+3 -> FLG (Bits 12-14) + PC (bits 16-19)
+ *
+ *  - Set IPL
+ *  - Vectors to this S/W interrupt handler:
+ */
+
+_m16c_contextsave:
+
+/* Save all registers on the interrupt stack */
+
+	mov.w	#1, r0				/* Return 1 on context switch */
+	pushm	fb,sb,a1,a0,r3,r2,r1,r0		/* Save on interrupt stack */
+
+/* Save the user stack pointer on the interrupt stack */
+
+	fset	u				/* Switch to User stack */
+	stc	sp, r0				/* R0 = user stack pointer */
+	fclr	u				/* Back to interrupt stack */
+	push.w	r0				/* Save user sp on isp */
+
+/* Then copy the stack content to the register context array pointed to by r1 */
+
+ 	stc	isp, a0				/* A0 = address of base of context info */
+	mov.w	r1, a1				/* A1 = address of register context array */
+	mov.b	#0, r1h				/* R1H = 4 MS of 20-bit source address */
+	mov.w	#XCPTCONTEXT_SIZE, r3		/* R3 = Number of bytes to transfer */
+	smovf.b					/* Copy ISP to near context array */
+
+/* Then return zero to indicate a normal function call return */
+
+	add.w	#(XCPTCONTEXT_SIZE - 4), sp	/* Remove stuff from stack */
+	mov.w	#0, r0				/* Return zero */
+	reit					/* Return from interrupt */
+	.size	_up_saveusercontext, .-_up_saveusercontext
+	
+/************************************************************************************
+ * Name: void up_fullcontextrestore(uint32_t *regs)
+ *
+ * Description:
+ *   Restore the context of the using the provided register save array.
+ *
+ * Input Parameters:
+ *   R1 = Address of register save array
+ *
+ * Returned Value:
+ *   None
+ *
+ ************************************************************************************/
+
+	.globl	_up_fullcontextrestore
+	.type	_up_fullcontextrestore, #function
+
+_up_fullcontextrestore:
+	int	#32		/* Execute S/W interrupt 32 */
+	rts			/* and return */
+
+/* This the logic executes in response to S/W interrupt 32.  The 'int 32' instruction
+ * will cause the following actions:
+ *
+ *  - Save FLG register
+ *  - Clear I and D flags in FLG register (U is preserved)
+ *  - Builds stack frame like (on the push-down, interrupt stack):
+ * 
+ *    sp   -> PC bits 0-7
+ *    sp+1 -> PC bits 8-15
+ *    sp+2 -> FLG bits 0-7
+ *    sp+3 -> FLG (Bits 12-14) + PC (bits 16-19)
+ *
+ *  - Set IPL
+ *  - Vectors to this S/W interrupt handler:
+ */
+
+_m16c_contextrestore:
+
+/* Set the USP to the beginning of the context save area */
+
+ 	ldc	r1, sp				/* USP = address of base of new context info */
+ 
+ /* Restore the user stack pointer */
+ 
+ 	fset	b				/* Switch to bank 1 */
+ 	pop.w	r0				/* R0 = saved user stack pointer */
+	fclr	b				/* Back to bank 0 */
+ 	
+/* Recover all registers */
+
+	popm	fb,sb,a1,a0,r3,r2,r1,r0		/* Restore from registers from user stack */
+
+/* Set the USP and return */
+
+	fset	b				/* Switch to bank 1 */
+	popm	r1,r0				/* Recover the PC and flags */
+	stc	sp, r0				/* Set the correct USP */
+	pushm	r1,r0				/* Put the PC and flags */
+	fclr	b				/* Back to bank 0 */
+
+/* The return from interrupt */
+
+	reit					/* Return from interrupt */
+	.size	_up_fullcontextrestore, .-_up_fullcontextrestore
+	.end

nuttx/arch/sh/src/sh1/Kconfig

@@ -0,0 +1,9 @@
+#
+# For a description of the syntax of this configuration file,
+# see misc/tools/kconfig-language.txt.
+#
+
+if ARCH_SH1
+comment "SH-1 Configuration Options"
+
+endif

nuttx/arch/sh/src/sh1/Make.defs

@@ -0,0 +1,56 @@
+##############################################################################
+# arch/sh/src/sh1/Make.defs
+#
+#   Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+##############################################################################
+
+HEAD_ASRC	= sh1_head.S
+
+CMN_ASRCS	= 
+CMN_CSRCS	= up_allocateheap.c up_assert.c up_blocktask.c \
+		  up_createstack.c up_doirq.c up_exit.c up_idle.c up_initialize.c \
+		  up_initialstate.c up_interruptcontext.c up_lowputs.c \
+		  up_mdelay.c up_puts.c up_releasepending.c up_releasestack.c \
+		  up_reprioritizertr.c up_udelay.c up_unblocktask.c up_usestack.c
+
+CHIP_ASRCS	= sh1_vector.S sh1_saveusercontext.S
+CHIP_CSRCS	= sh1_lowputc.c sh1_irq.c sh1_timerisr.c sh1_serial.c \
+		  sh1_initialstate.c sh1_copystate.c sh1_dumpstate.c
+
+ifneq ($(CONFIG_DISABLE_SIGNALS),y)
+CMN_CSRCS	+= sh1_schedulesigaction.c sh1_sigdeliver.c
+endif
+
+ifeq ($(CONFIG_USBDEV),y)
+CHIP_CSRCS	+= 
+endif
+

nuttx/arch/sh/src/sh1/README.txt

@@ -0,0 +1,2 @@
+This directory contains source files that are unique to the SH-1
+chip architecture.

nuttx/arch/sh/src/sh1/chip.h

@@ -0,0 +1,74 @@
+/************************************************************************************
+ * arch/sh/src/sh1/chip.h
+ *
+ *   Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_SH_SRC_SH1_CHIP_H
+#define __ARCH_SH_SRC_SH1_CHIP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+
+#ifdef CONFIG_ARCH_CHIP_SH7032
+#  include "sh1_703x.h"
+#endif
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/* Address of the saved user stack pointer */
+
+#ifndef __ASSEMBLY__
+#  if CONFIG_ARCH_INTERRUPTSTACK > 3
+     extern uint32_t g_userstack;
+#  endif
+#endif
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_SH_SRC_SH1_CHIP_H */

nuttx/arch/sh/src/sh1/sh1_703x.h

@@ -0,0 +1,475 @@
+/************************************************************************************
+ * arch/sh/src/sh1/sh1_703x.h
+ *
+ *   Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_SH_SRC_SH1_703X_H
+#define __ARCH_SH_SRC_SH1_703X_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Memory-mapped register addresses *************************************************/
+
+/* Serial Communications interface (SCI) */
+
+#define SH1_SCI0_BASE       (0x05fffec0)
+#define SH1_SCI1_BASE       (0x05fffec8)
+
+#define SH1_SCI_SMR_OFFSET  (0)  /* Serial Mode Register (8-bits wide) */
+#define SH1_SCI_BRR_OFFSET  (1)  /* Bit Rate Register (8-bits wide) */
+#define SH1_SCI_SCR_OFFSET  (2)  /* Serial Control Register (8-bits wide) */
+#define SH1_SCI_TDR_OFFSET  (3)  /* Transmit Data Register (8-bits wide) */
+#define SH1_SCI_SSR_OFFSET  (4)  /* Serial Status Register (8-bits wide) */
+#define SH1_SCI_RDR_OFFSET  (5)  /* Receive Data Register (8-bits wide) */
+
+#define SH1_SCI0_SMR        (SH1_SCI0_BASE+SH1_SCI_SMR_OFFSET)
+#define SH1_SCI0_BRR        (SH1_SCI0_BASE+SH1_SCI_BRR_OFFSET)
+#define SH1_SCI0_SCR        (SH1_SCI0_BASE+SH1_SCI_SCR_OFFSET)
+#define SH1_SCI0_TDR        (SH1_SCI0_BASE+SH1_SCI_TDR_OFFSET)
+#define SH1_SCI0_SSR        (SH1_SCI0_BASE+SH1_SCI_SSR_OFFSET)
+#define SH1_SCI0_RDR        (SH1_SCI0_BASE+SH1_SCI_RDR_OFFSET)
+
+#define SH1_SCI1_SMR        (SH1_SCI1_BASE+SH1_SCI_SMR_OFFSET)
+#define SH1_SCI1_BRR        (SH1_SCI1_BASE+SH1_SCI_BRR_OFFSET)
+#define SH1_SCI1_SCR        (SH1_SCI1_BASE+SH1_SCI_SCR_OFFSET)
+#define SH1_SCI1_TDR        (SH1_SCI1_BASE+SH1_SCI_TDR_OFFSET)
+#define SH1_SCI1_SSR        (SH1_SCI1_BASE+SH1_SCI_SSR_OFFSET)
+#define SH1_SCI1_RDR        (SH1_SCI1_BASE+SH1_SCI_RDR_OFFSET)
+
+/* A/D */
+
+#define SH1_AD_ADDRA        (0x05fffee0)  /* 16-bits wide */
+#define SH1_AD_DRAH         (0x05fffee0)  /* 8-bits wide */
+#define SH1_AD_DRAL         (0x05fffee1)  /* 8-bits wide */
+#define SH1_AD_DRB          (0x05fffee2)  /* 16-bits wide */
+#define SH1_AD_DRBH         (0x05fffee2)  /* 8-bits wide */
+#define SH1_AD_DRBL         (0x05fffee3)  /* 8-bits wide */
+#define SH1_AD_DRC          (0x05fffee4)  /* 16-bits wide */
+#define SH1_AD_DRCH         (0x05fffee4)  /* 8-bits wide */
+#define SH1_AD_DRCL         (0x05fffee5)  /* 8-bits wide */
+#define SH1_AD_DRD          (0x05fffee6)  /* 16-bits wide */
+#define SH1_AD_DRDH         (0x05fffee6)  /* 8-bits wide */
+#define SH1_AD_DRDL         (0x05fffee7)  /* 8-bits wide */
+#define SH1_AD_CSR          (0x05fffee8)  /* 8-bits wide */
+#define SH1_AD_CR           (0x05fffee9)  /* 8-bits wide */
+
+/* Integrated Timer/Pulse Unit (ITU) */
+
+/* ITU shared */
+
+#define SH1_ITU_TSTR        (0x05ffff00)  /* 8-bits wide */
+#define SH1_ITU_TSNC        (0x05ffff01)  /* 16-bits wide */
+#define SH1_ITU_TMDR        (0x05ffff02)  /* 16-bits wide */
+#define SH1_ITU_TFCR        (0x05ffff03)  /* 16-bits wide */
+
+/* ITU channel 0 */
+
+#define SH1_ITU0_TCR        (0x05ffff04)  /* 8-bits wide */
+#define SH1_ITU0_TIOR       (0x05ffff05)  /* 8-bits wide */
+#define SH1_ITU0_TIER       (0x05ffff06)  /* 8-bits wide */
+#define SH1_ITU0_TSR        (0x05ffff07)  /* 8-bits wide */
+#define SH1_ITU0_TCNT       (0x05ffff08)  /* 16-bits wide */
+#define SH1_ITU0_GRA        (0x05ffff0a)  /* 16-bits wide */
+#define SH1_ITU0_GRB        (0x05ffff0c)  /* 16-bits wide */
+
+/* ITU channel 1 */
+
+#define SH1_ITU1_TCR        (0x05ffff0e)  /* 8-bits wide */
+#define SH1_ITU1_TIOR       (0x05ffff0f)  /* 8-bits wide */
+#define SH1_ITU1_TIER       (0x05ffff10)  /* 8-bits wide */
+#define SH1_ITU1_TSR        (0x05ffff11)  /* 8-bits wide */
+#define SH1_ITU1_TCNT       (0x05ffff12)  /* 16-bits wide */
+#define SH1_ITU1_GRA        (0x05ffff14)  /* 16-bits wide */
+#define SH1_ITU1_GRB        (0x05ffff16)  /* 16-bits wide */
+
+/* ITU channel 2 */
+
+#define SH1_ITU2_TCR        (0x05ffff18)  /* 8-bits wide */
+#define SH1_ITU2_TIOR       (0x05ffff19)  /* 8-bits wide */
+#define SH1_ITU2_TIER       (0x05ffff1a)  /* 8-bits wide */
+#define SH1_ITU2_TSR        (0x05ffff1b)  /* 8-bits wide */
+#define SH1_ITU2_TCNT       (0x05ffff1c)  /* 16-bits wide */
+#define SH1_ITU2_GRA        (0x05ffff1e)  /* 16-bits wide */
+#define SH1_ITU2_GRB        (0x05ffff20)  /* 16-bits wide */
+
+/* ITU channel 3 */
+
+#define SH1_ITU3_TCR        (0x05ffff22)  /* 8-bits wide */
+#define SH1_ITU3_TIOR       (0x05ffff23)  /* 8-bits wide */
+#define SH1_ITU3_TIER       (0x05ffff24)  /* 8-bits wide */
+#define SH1_ITU3_TSR        (0x05ffff25)  /* 8-bits wide */
+#define SH1_ITU3_TCNT       (0x05ffff26)  /* 16-bits wide */
+#define SH1_ITU3_GRA        (0x05ffff28)  /* 16-bits wide */
+#define SH1_ITU3_GRB        (0x05ffff2a)  /* 16-bits wide */
+#define SH1_ITU3_BRA        (0x05ffff2c)  /* 16-bits wide */
+#define SH1_ITU3_BRB3       (0x05ffff2e)  /* 16-bits wide */
+
+/* ITU channels 0-4 shared */
+
+#define SH1_ITU_TOCR        (0x05ffff31)  /* 8-bits wide */
+
+/* ITU channel 4 */
+
+#define SH1_ITU4_TCR        (0x05ffff32)  /* 8-bits wide */
+#define SH1_ITU4_TIOR       (0x05ffff33)  /* 8-bits wide */
+#define SH1_ITU4_TIER       (0x05ffff34)  /* 8-bits wide */
+#define SH1_ITU4_TSR        (0x05ffff35)  /* 8-bits wide */
+#define SH1_ITU4_TCNT       (0x05ffff36)  /* 16-bits wide */
+#define SH1_ITU4_GRA        (0x05ffff38)  /* 16-bits wide */
+#define SH1_ITU4_GRB        (0x05ffff3a)  /* 16-bits wide */
+#define SH1_ITU4_BRA        (0x05ffff3c)  /* 16-bits wide */
+#define SH1_ITU4_BRB        (0x05ffff3e)  /* 16-bits wide */
+
+/* DMA controller (DMAC) */
+
+/* DMAC channels 0-3 shared */
+
+#define SH1_DMAOR           (0x05ffff48)  /* 16-bits wide */
+
+/* DMAC channel 0 */
+
+#define SH1_DMA0_SAR0       (0x05ffff40)  /* 32-bits wide */
+#define SH1_DMA0_DAR0       (0x05ffff44)  /* 32-bits wide */
+#define SH1_DMA0_TCR0       (0x05ffff4a)  /* 16-bits wide */
+#define SH1_DMA0_CHCR0      (0x05ffff4e)  /* 16-bits wide */
+
+/* DMAC channel 1 */
+
+#define SH1_DMA1_SAR        (0x05ffff50)  /* 32-bits wide */
+#define SH1_DMA1_DAR        (0x05ffff54)  /* 32-bits wide */
+#define SH1_DMA1_TCR        (0x05fffF5a)  /* 16-bits wide */
+#define SH1_DMA1_CHCR       (0x05ffff5e)  /* 16-bits wide */
+
+/* DMAC channel 2 */
+
+#define SH1_DMA2_SAR        (0x05ffff60)  /* 32-bits wide */
+#define SH1_DMA2_DAR        (0x05ffff64)  /* 32-bits wide */
+#define SH1_DMA2_TCR        (0x05fffF6a)  /* 16-bits wide */
+#define SH1_DMA2_CHCR       (0x05ffff6e)  /* 16-bits wide */
+
+/* DMAC channel 3 */
+
+#define SH1_DMA3_SAR        (0x05ffff70)  /* 32-bits wide */
+#define SH1_DMA3_DAR        (0x05ffff74)  /* 32-bits wide */
+#define SH1_DMA3_TCR        (0x05fffF7a)  /* 16-bits wide */
+#define SH1_DMA3_CHCR       (0x05ffff7e)  /* 16-bits wide */
+
+/* Interrupt Controller (INTC) */
+
+#define SH1_INTC_IPRA       (0x05ffff84)  /* Interrupt priority register A (16-bits wide) */
+#define SH1_INTC_IPRB       (0x05ffff86)  /* Interrupt priority register B (16-bits wide) */
+#define SH1_INTC_IPRC       (0x05ffff88)  /* Interrupt priority register C (16-bits wide) */
+#define SH1_INTC_IPRD       (0x05ffff8a)  /* Interrupt priority register D (16-bits wide) */
+#define SH1_INTC_IPRE       (0x05ffff8c)  /* Interrupt priority register E (16-bits wide) */
+#define SH1_INTC_ICR        (0x05ffff8e)  /* Interrupt control register (16-bits wide) */
+
+/* User Break Controller (UBC) */
+
+#define SH1_UBC_BARH        (0x05ffff90)  /* 16-bits wide */
+#define SH1_UBC_BARL        (0x05ffff92)  /* 16-bits wide */
+#define SH1_UBC_BAMRH       (0x05ffff94)  /* 16-bits wide */
+#define SH1_UBC_BAMRL       (0x05ffff96)  /* 16-bits wide */
+#define SH1_UBC_BBR         (0x05ffff98)  /* 16-bits wide */
+
+/* Bus State Controller (BSC) */
+
+#define SH1_BSC_BCR         (0x05ffffa0)  /* 16-bits wide */
+#define SH1_BSC_WCR1        (0x05ffffa2)  /* 16-bits wide */
+#define SH1_BSC_WCR2        (0x05ffffa4)  /* 16-bits wide */
+#define SH1_BSC_WCR3        (0x05ffffa6)  /* 16-bits wide */
+#define SH1_BSC_DCR         (0x05ffffa8)  /* 16-bits wide */
+#define SH1_BSC_PCR         (0x05ffffaa)  /* 16-bits wide */
+#define SH1_BSC_RCR         (0x05ffffac)  /* 16-bits wide */
+#define SH1_BSC_RTCSR       (0x05ffffae)  /* 16-bits wide */
+#define SH1_BSC_RTCNT       (0x05ffffb0)  /* 16-bits wide */
+#define SH1_BSC_RTCOR       (0x05ffffb2)  /* 16-bits wide */
+
+/* Watchdog Timer (WDT) */
+
+#define SH1_WDT_TCSR        (0x05ffffb8)  /* 8-bits wide */
+#define SH1_WDT_TCNT        (0x05ffffb9)  /* 8-bits wide */
+#define SH1_WDT_RSTCSR      (0x05ffffbb)  /* 8-bits wide */
+
+/* Power down state */
+
+#define SH1_PDT_SBYCR       (0x05ffffbc)  /* 8-bits wide */
+
+/* Port A */
+
+#define SH1_PORTA_DR        (0x05ffffc0)  /* 16-bits wide */
+
+/* Port B */
+
+#define SH1_PORTB_DR        (0x05ffffc2)  /* 16-bits wide */
+
+/* Pin Function Controller (PFC) */
+
+#define SH1_PFC_PAIOR       (0x05ffffc4)  /* Port B I/O register (16-bits wide) */
+#define SH1_PFC_PBIOR       (0x05ffffc6)  /* Port B I/O register (16-bits wide) */
+#define SH1_PFC_PACR1       (0x05ffffc8)  /* Port A control register 1 (16-bits wide) */
+#define SH1_PFC_PACR2       (0x05ffffca)  /* Port A control register 2 (16-bits wide) */
+#define SH1_PFC_PBCR1       (0x05ffffcc)  /* Port B control register 1 (16-bits wide) */
+#define SH1_PFC_PBCR2       (0x05ffffce)  /* Port B control register 2 )16-bits wide) */
+
+/* Port C */
+
+#define SH1_PORTC_DR        (0x05ffffd0)  /* 16-bits wide */
+
+/* Pin Function Controller (PFC, cont'd) */
+
+#define SH1_PFC_CASCR       (0x05ffffee)  /* 16-bits wide */
+
+/* Timing Pattern Controller (TPC) */
+
+#define SH1_TPC_TPMR        (0x05fffff0)  /* 16-bits wide */
+#define SH1_TPC_TPCR        (0x05fffff1)  /* 16-bits wide */
+#define SH1_TPC_NDERH       (0x05fffff2)  /* 16-bits wide */
+#define SH1_TPC_NDERL       (0x05fffff3)  /* 16-bits wide */
+#define SH1_TPC_NDRB0       (0x05fffff4)  /* 8-bits wide */
+#define SH1_TPC_NDRA0       (0x05fffff5)  /* 8-bits wide */
+#define SH1_TPC_NDRB1       (0x05fffff6)  /* 8-bits wide */
+#define SH1_TPC_NDRA1       (0x05fffff7)  /* 8-bits wide */
+
+/* Register bit definitions *********************************************************/
+
+/* Serial Communications interface (SCI) */
+
+#define SH1_SCISMR_CKSMASK  (0x03)        /* Bit 0-1: Internal clock source */
+#define SH1_SCISMR_DIV1     (0x00)        /*   System clock (phi) */
+#define SH1_SCISMR_DIV4     (0x01)        /*   phi/4 */
+#define SH1_SCISMR_DIV16    (0x02)        /*   phi/16 */
+#define SH1_SCISMR_DIV64    (0x03)        /*   phi/64 */
+#define SH1_SCISMR_MP       (0x04)        /* Bit 2: Multiprocessor select */
+#define SH1_SCISMR_STOP     (0x08)        /* Bit 3: 0:One stop bit, 1:Two stop bits */
+#define SH1_SCISMR_OE       (0x10)        /* Bit 4: 0:Even parity, 1:Odd parity */
+#define SH1_SCISMR_PE       (0x20)        /* Bit 5: Parity enable */
+#define SH1_SCISMR_CHR      (0x40)        /* Bit 6: 0:8-bit data, 1:7-bit data */
+#define SH1_SCISMR_CA       (0x80)        /* Bit 7: 0:Asynchronous, 1:clocked synchronous */
+
+#define SH1_SCISCR_CKEMASK  (0x03)        /* Bit 0-1: Internal clock source */
+                                          /* Asynchronous mode: */
+#define SH1_SCISCR_AISIN    (0x00)        /*   Internal clock, SCK pin used for input pin */
+#define SH1_SCISCR_AISOUT   (0x01)        /*   Internal clock, SCK pin used for clock output */
+#define SH1_SCISCR_AXSIN1   (0x02)        /*   External clock, SCK pin used for clock input */
+#define SH1_SCISCR_AXSIN2   (0x03)        /*   External clock, SCK pin used for clock input */
+                                          /* Synchronous mode: */
+#define SH1_SCISCR_SISOUT1  (0x00)        /*   Internal clock, SCK pin used for input pin */
+#define SH1_SCISCR_SISOUT2  (0x01)        /*   Internal clock, SCK pin used for clock output */
+#define SH1_SCISCR_SXSIN1   (0x02)        /*   External clock, SCK pin used for clock input */
+#define SH1_SCISCR_SXSIN2   (0x03)        /*   External clock, SCK pin used for clock input */
+#define SH1_SCISCR_TEIE     (0x04)        /* Bit 2: 1=Transmit end interrupt enable */
+#define SH1_SCISCR_MPIE     (0x08)        /* Bit 3: 1=Multiprocessor interrupt enable */
+#define SH1_SCISCR_RE       (0x10)        /* Bit 4: 1=Receiver enable */
+#define SH1_SCISCR_TE       (0x20)        /* Bit 5: 1=Transmitter enable */
+#define SH1_SCISCR_RIE      (0x40)        /* Bit 6: 1=Recieve-data-full interrupt enable */
+#define SH1_SCISCR_TIE      (0x80)        /* Bit 7: 1=Transmit-data-empty interrupt enable */
+#define SH1_SCISCR_ALLINTS  (0xcc)
+
+#define SH1_SCISSR_MPBT     (0x01)        /* Bit 0: Multi-processor Bit in Transmit data */
+#define SH1_SCISSR_MPB      (0x02)        /* Bit 1: Multi-processor Bit in receive data */
+#define SH1_SCISSR_TEND     (0x04)        /* Bit 2: End of transmission */
+#define SH1_SCISSR_PER      (0x08)        /* Bit 3: Receive parity error */
+#define SH1_SCISSR_FER      (0x10)        /* Bit 4: Receive framing error */
+#define SH1_SCISSR_ORER     (0x20)        /* Bit 5: Receive overrun error */
+#define SH1_SCISSR_RDRF     (0x40)        /* Bit 6: RDR contains valid received data */
+#define SH1_SCISSR_TDRE     (0x80)        /* Bit 7: TDR does not contain valid transmit data */
+
+/* Integrated Timer unit (ITU) */
+
+#define SH1_ITUTSTR_STR0    (0x01)        /* Bit 0: TCNT0 is counting */
+#define SH1_ITUTSTR_STR1    (0x02)        /* Bit 1: TCNT1 is counting */
+#define SH1_ITUTSTR_STR2    (0x04)        /* Bit 2: TCNT2 is counting */
+#define SH1_ITUTSTR_STR3    (0x08)        /* Bit 3: TCNT3 is counting */
+#define SH1_ITUTSTR_STR4    (0x10)        /* Bit 4: TCNT4 is counting */
+
+#define SH1_ITUTSNC_SYNC0   (0x01)        /* Bit 0: Channel 0 operates synchronously */
+#define SH1_ITUTSNC_SYNC1   (0x02)        /* Bit 1: Channel 1 operates synchronously */
+#define SH1_ITUTSNC_SYNC2   (0x04)        /* Bit 2: Channel 2 operates synchronously */
+#define SH1_ITUTSNC_SYNC3   (0x08)        /* Bit 3: Channel 3 operates synchronously */
+#define SH1_ITUTSNC_SYNC4   (0x10)        /* Bit 4: Channel 4 operates synchronously */
+
+#define SH1_ITUTMDR_PWM0    (0x01)        /* Bit 0: Channel 0 operated in PWM mode */
+#define SH1_ITUTMDR_PWM1    (0x02)        /* Bit 1: Channel 1 operated in PWM mode */
+#define SH1_ITUTMDR_PWM2    (0x04)        /* Bit 2: Channel 2 operated in PWM mode */
+#define SH1_ITUTMDR_PWM3    (0x08)        /* Bit 3: Channel 3 operated in PWM mode */
+#define SH1_ITUTMDR_PWM4    (0x10)        /* Bit 4: Channel 4 operated in PWM mode */
+#define SH1_ITUTMDR_FDIR    (0x20)        /* Bit 5: OVF set when TCNT2 overflows */
+#define SH1_ITUTMDR_MDF     (0x40)        /* Bit 6: Channel 2 operates in phase counting mode */
+
+#define SH1_ITUTFCR_BFA3    (0x01)        /* Bit 0: GRA3 & BRA3 operate in mode in channel 4 */
+#define SH1_ITUTFCR_BFB3    (0x02)        /* Bit 1: GRB3 & BRB3 operate in mode in channel 4 */
+#define SH1_ITUTFCR_BFA4    (0x04)        /* Bit 2: GRA4 & BRA4 operate in mode in channel 4 */
+#define SH1_ITUTFCR_BFB4    (0x08)        /* Bit 3: GRB4 & BRB4 operate in mode in channel 4 */
+#define SH1_ITUTFCR_CMDMASK (0x30)        /* Bit 4-5: Command */
+#define SH1_ITUTFCR_34NDEF  (0x00)        /*    Channels 3/4 normal (default) */
+#define SH1_ITUTFCR_34NORM  (0x10)        /*    Channels 3/4 normal */
+#define SH1_ITUTFCR_34CPWM  (0x20)        /*    Channels 3/4 in complementary PWM mode*/
+#define SH1_ITUTFCR_34RSPWN (0x30)        /*    Channels 3/4 in reset-synchronized PWM mode */
+
+#define SH1_ITUTOCR_OLS3    (0x01)        /* Bit 0: 1=TIOCA3, A4 & B4 not inverted */
+#define SH1_ITUTOCR_OLS4    (0x02)        /* Bit 1: 1=TIOCB3, XA4 & XB4 not inverted */
+
+#define SH1_ITUTCR_TPSCMSK  (0x07)        /* Bits 0-2: Clock setup, internal/external, divider */
+#define SH1_ITUTCR_DIV1     (0x00)        /*   Internal clock (phi) */
+#define SH1_ITUTCR_DIV2     (0x01)        /*   phi / 2 */
+#define SH1_ITUTCR_DIV4     (0x02)        /*   phi / 4 */
+#define SH1_ITUTCR_DIV8     (0x03)        /*   phi / 8 */
+#define SH1_ITUTCR_TCLKA    (0x04)        /*   External clock A (TCLKA) */
+#define SH1_ITUTCR_TCLKB    (0x05)        /*   External clock B (TCLKB) */
+#define SH1_ITUTCR_TCLKC    (0x06)        /*   External clock C (TCLKC) */
+#define SH1_ITUTCR_TCLKD    (0x07)        /*   External clock D (TCLKD) */
+#define SH1_ITUTCR_CKEGMSK  (0x18)        /* Bits 3-4: External clock input edge selection */
+#define SH1_ITUTCR_RISING   (0x00)        /*   Count rising edges */
+#define SH1_ITUTCR_FALLING  (0x08)        /*   Count falling edges */
+#define SH1_ITUTCR_BOTH     (0x10)        /*   Count both */
+#define SH1_ITUTCR_CCLRMSK  (0x60)        /* Bits 5-6: TCNT clear controls */
+#define SH1_ITUTCR_NCLR     (0x00)        /*   TCNT not cleared */
+#define SH1_ITUTCR_CGRA     (0x20)        /*   TCNT cleared by GRA */
+#define SH1_ITUTCR_CGRB     (0x40)        /*   TCNT cleared by GRB */
+#define SH1_ITUTCR_CSYNC    (0x60)        /*   Synchronized clear */
+
+#define SH1_ITUTIOR_IOAMSK  (0x07)        /* Bits 0-3: GRA function */
+#define SH1_ITUTIOR_OCGRAD  (0x00)        /*   GRA output comparator, disabled */
+#define SH1_ITUTIOR_OCGRA0  (0x01)        /*   GRA output comparator, 0 output at match */
+#define SH1_ITUTIOR_OCGRA1  (0x02)        /*   GRA output comparator, 1 output at match */
+#define SH1_ITUTIOR_OCATOG  (0x03)        /*   GRA output comparator, output toggles at match */
+#define SH1_ITUTIOR_ICGRAR  (0x04)        /*   GRA input capture, rising edge */
+#define SH1_ITUTIOR_ICGRAF  (0x05)        /*   GRA input capture, falling edge */
+#define SH1_ITUTIOR_ICGRAB  (0x06)        /*   GRA input capture, both edges */
+#define SH1_ITUTIOR_IOBMSK  (0x70)        /* Bits 4-6: GRB function */
+#define SH1_ITUTIOR_OCGRBD  (0x00)        /*   GRB output comparator, disabled */
+#define SH1_ITUTIOR_OCGRB0  (0x10)        /*   GRB output comparator, 0 output at match */
+#define SH1_ITUTIOR_OCGRB1  (0x20)        /*   GRB output comparator, 1 output at match */
+#define SH1_ITUTIOR_OCBTOG  (0x30)        /*   GRB output comparator, output toggles at match */
+#define SH1_ITUTIOR_ICGRBR  (0x40)        /*   GRB input capture, rising edge */
+#define SH1_ITUTIOR_ICGRBF  (0x50)        /*   GRB input capture, falling edge */
+#define SH1_ITUTIOR_ICGRBB  (0x60)        /*   GRB input capture, both edges */
+
+#define SH1_ITUTSR_IMFA     (0x01)        /* Bit 0: 0=Clearing condition, 1=setting confition */
+#define SH1_ITUTSR_IMFB     (0x02)        /* Bit 1: 0=Clearing condition, 1=setting confition */
+#define SH1_ITUTSR_OVF      (0x04)        /* Bit 2: 0=Clearing condition, 1=setting confition */
+
+#define SH1_ITUTIER_IMIEA   (0x01)        /* Bit 0: Enables interrupt request from IMFA */
+#define SH1_ITUTIER_IMIEB   (0x02)        /* Bit 1: Enables interrupt request from IMFB */
+#define SH1_ITUTIER_OVIE    (0x04)        /* Bit 2: Enables interrupt request from OVR */
+
+/* Interrupt Controller (INTC) */
+
+#define SH1_IPRA_IRQ3MASK   (0x000f)      /* Bits 0-3: IRQ3 */
+#define SH1_IPRA_IRQ3SHIFT  (0)
+#define SH1_IPRA_IRQ2MASK   (0x00f0)      /* Bits 4-7: IRQ2 */
+#define SH1_IPRA_IRQ2SHIFT  (4)
+#define SH1_IPRA_IRQ1MASK   (0x0f00)      /* Bits 8-11: IRQ1 */
+#define SH1_IPRA_IRQ1SHIFT  (8)
+#define SH1_IPRA_IRQ0MASK   (0xf000)      /* Bits 12-15: IRQ0 */
+#define SH1_IPRA_IRQ0SHIFT  (12)
+
+#define SH1_IPRB_IRQ7MASK   (0x000f)      /* Bits 0-3: IRQ7 */
+#define SH1_IPRB_IRQ7SHIFT  (0)
+#define SH1_IPRB_IRQ6MASK   (0x00f0)      /* Bits 4-7: IRQ6 */
+#define SH1_IPRB_IRQ6SHIFT  (4)
+#define SH1_IPRB_IRQ5MASK   (0x0f00)      /* Bits 8-11: IRQ5 */
+#define SH1_IPRB_IRQ5SHIFT  (8)
+#define SH1_IPRB_IRQ4MASK   (0xf000)      /* Bits 12-15: IRQ4 */
+#define SH1_IPRB_IRQ4SHIFT  (12)
+
+#define SH1_IPRC_ITU1MASK   (0x000f)      /* Bits 0-3: ITU1 */
+#define SH1_IPRC_ITU1SHIFT  (0)
+#define SH1_IPRC_ITU0MASK   (0x00f0)      /* Bits 4-7: ITU0 */
+#define SH1_IPRC_ITU0SHIFT  (4)
+#define SH1_IPRC_DM23MASK   (0x0f00)      /* Bits 8-11: DMAC2,3 */
+#define SH1_IPRC_DM23SHIFT  (8)
+#define SH1_IPRC_DM01MASK   (0xf000)      /* Bits 12-15: DMAC0,1 */
+#define SH1_IPRC_DM01SHIFT  (12)
+
+#define SH1_IPRD_SCI0MASK   (0x000f)      /* Bits 0-3: SCI0 */
+#define SH1_IPRD_SCI0SHIFT  (0)
+#define SH1_IPRD_ITU4MASK   (0x00f0)      /* Bits 4-7: ITU4 */
+#define SH1_IPRD_ITU4SHIFT  (4)
+#define SH1_IPRD_ITU3MASK   (0x0f00)      /* Bits 8-11: ITU3 */
+#define SH1_IPRD_ITU3SHIFT  (8)
+#define SH1_IPRD_ITU2MASK   (0xf000)      /* Bits 12-15: ITU2 */
+#define SH1_IPRD_ITU2SHIFT  (12)
+
+#define SH1_IPRE_WDRFMASK   (0x00f0)      /* Bits 4-7: WDT, REF */
+#define SH1_IPRE_WDRFSHIFT  (4)
+#define SH1_IPRE_PRADMASK   (0x0f00)      /* Bits 8-11: PRT, A/D */
+#define SH1_IPRE_PRADSHIFT  (8)
+#define SH1_IPRE_SCI1MASK   (0xf000)      /* Bits 12-15: SCI1 */
+#define SH1_IPRE_SCI1SHIFT  (12)
+
+#define SH1_ICR_IRQ7S       (0x0001)      /* Bits 0: Interrupt on falling edge of IRQ7 input */
+#define SH1_ICR_IRQ6S       (0x0002)      /* Bits 1: Interrupt on falling edge of IRQ6 input */
+#define SH1_ICR_IRQ5S       (0x0004)      /* Bits 2: Interrupt on falling edge of IRQ5 input */
+#define SH1_ICR_IRQ4S       (0x0008)      /* Bits 3: Interrupt on falling edge of IRQ4 input */
+#define SH1_ICR_IRQ3S       (0x0010)      /* Bits 4: Interrupt on falling edge of IRQ3 input */
+#define SH1_ICR_IRQ2S       (0x0020)      /* Bits 5: Interrupt on falling edge of IRQ2 input */
+#define SH1_ICR_IRQ1S       (0x0040)      /* Bits 6: Interrupt on falling edge of IRQ1 input */
+#define SH1_ICR_IRQ0S       (0x0080)      /* Bits 7: Interrupt on falling edge of IRQ0 input */
+#define SH1_ICR_NMIE        (0x0100)      /* Bits 8: Interupt on rising edge of NMI input */
+#define SH1_ICR_NMIL        (0x8000)      /* Bits 15: NMI input level high */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_SH_SRC_SH1_703X_H */
+
+
+
+
+
+
+
+
+
+
+
+
+

nuttx/arch/sh/src/sh1/sh1_copystate.c

@@ -0,0 +1,77 @@
+/****************************************************************************
+ * arch/sh/src/sh1/up_copystate.c
+ *
+ *   Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+#include "os_internal.h"
+#include "up_internal.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_copystate
+ ****************************************************************************/
+
+/* A little faster than most memcpy's */
+
+void up_copystate(uint32_t *dest, uint32_t *src)
+{
+  int i;
+  for (i = 0; i < XCPTCONTEXT_REGS; i++)
+    {
+      *dest++ = *src++;
+    }
+}
+

nuttx/arch/sh/src/sh1/sh1_dumpstate.c

@@ -0,0 +1,234 @@
+/****************************************************************************
+ * arch/sh/src/sh1/sh1_assert.c
+ *
+ *   Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+#include "os_internal.h"
+
+#ifdef CONFIG_ARCH_STACKDUMP
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/* Output debug info if stack dump is selected -- even if 
+ * debug is not selected.
+ */
+
+#ifdef CONFIG_ARCH_STACKDUMP
+# undef  lldbg
+# define lldbg lib_lowprintf
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sh1_getsp
+ ****************************************************************************/
+
+static inline uint32_t sh1_getsp(void)
+{
+  uint32_t sp;
+
+  __asm__ __volatile__
+    (
+      "mov   r15, %0\n\t"
+      : "=&z" (sp)
+      :
+      : "memory"
+    );
+  return sp;
+}
+
+/****************************************************************************
+ * Name: sh1_stackdump
+ ****************************************************************************/
+
+static void sh1_stackdump(uint32_t sp, uint32_t stack_base)
+{
+  uint32_t stack ;
+
+  for (stack = sp & ~0x1f; stack < stack_base; stack += 32)
+    {
+      uint32_t *ptr = (uint32_t*)stack;
+      lldbg("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+             stack, ptr[0], ptr[1], ptr[2], ptr[3],
+             ptr[4], ptr[5], ptr[6], ptr[7]);
+    }
+}
+
+/****************************************************************************
+ * Name: sh1_registerdump
+ ****************************************************************************/
+
+static inline void sh1_registerdump(void)
+{
+  uint32_t *ptr = (uint32_t*)current_regs;
+
+  /* Are user registers available from interrupt processing? */
+
+  if (ptr)
+    {
+      /* Yes.. dump the interrupt registers */
+
+      lldbg("PC: %08x SR=%08x\n",
+            ptr[REG_PC], ptr[REG_SR]);
+
+      lldbg("PR: %08x GBR: %08x MACH: %08x MACL: %08x\n",
+            ptr[REG_PR], ptr[REG_GBR], ptr[REG_MACH], ptr[REG_MACL]);
+
+      lldbg("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n", 0,
+            ptr[REG_R0], ptr[REG_R1], ptr[REG_R2], ptr[REG_R3],
+            ptr[REG_R4], ptr[REG_R5], ptr[REG_R6], ptr[REG_R7]);
+
+      lldbg("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n", 8,
+            ptr[REG_R8], ptr[REG_R9], ptr[REG_R10], ptr[REG_R11],
+            ptr[REG_R12], ptr[REG_R13], ptr[REG_R14], ptr[REG_R15]);
+    }
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_dumpstate
+ ****************************************************************************/
+
+void up_dumpstate(void)
+{
+  _TCB    *rtcb     = (_TCB*)g_readytorun.head;
+  uint32_t sp       = sh1_getsp();
+  uint32_t ustackbase;
+  uint32_t ustacksize;
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+  uint32_t istackbase;
+  uint32_t istacksize;
+#endif
+
+  /* Get the limits on the user stack memory */
+
+  if (rtcb->pid == 0)
+    {
+      ustackbase = g_heapbase - 4;
+      ustacksize = CONFIG_IDLETHREAD_STACKSIZE;
+    }
+  else
+    {
+      ustackbase = (uint32_t)rtcb->adj_stack_ptr;
+      ustacksize = (uint32_t)rtcb->adj_stack_size;
+    }
+
+  /* Get the limits on the interrupt stack memory */
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+  istackbase = (uint32_t)&g_userstack;
+  istacksize = (CONFIG_ARCH_INTERRUPTSTACK & ~3) - 4;
+
+  /* Show interrupt stack info */
+
+  lldbg("sp:     %08x\n", sp);
+  lldbg("IRQ stack:\n");
+  lldbg("  base: %08x\n", istackbase);
+  lldbg("  size: %08x\n", istacksize);
+
+  /* Does the current stack pointer lie within the interrupt
+   * stack?
+   */
+
+  if (sp <= istackbase && sp > istackbase - istacksize)
+    {
+      /* Yes.. dump the interrupt stack */
+
+      sh1_stackdump(sp, istackbase);
+
+      /* Extract the user stack pointer which should lie
+       * at the base of the interrupt stack.
+       */
+
+      sp = g_userstack;
+      lldbg("sp:     %08x\n", sp);
+    }
+
+  /* Show user stack info */
+
+  lldbg("User stack:\n");
+  lldbg("  base: %08x\n", ustackbase);
+  lldbg("  size: %08x\n", ustacksize);
+#else
+  lldbg("sp:         %08x\n", sp);
+  lldbg("stack base: %08x\n", ustackbase);
+  lldbg("stack size: %08x\n", ustacksize);
+#endif
+
+  /* Dump the user stack if the stack pointer lies within the allocated user
+   * stack memory.
+   */
+
+  if (sp > ustackbase || sp <= ustackbase - ustacksize)
+    {
+#if !defined(CONFIG_ARCH_INTERRUPTSTACK) || CONFIG_ARCH_INTERRUPTSTACK < 4
+      lldbg("ERROR: Stack pointer is not within allocated stack\n");
+#endif
+    }
+  else
+    {
+      sh1_stackdump(sp, ustackbase);
+    }
+
+  /* Then dump the registers (if available) */
+
+  sh1_registerdump();
+}
+
+#endif /* CONFIG_ARCH_STACKDUMP */

nuttx/arch/sh/src/sh1/sh1_head.S

@@ -0,0 +1,524 @@
+/*****************************************************************************
+ * arch/sh/src/sh1/sh1_head.S
+ *
+ *   Copyright (C) 2008-2009, 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/*****************************************************************************
+ * Included Files
+ *****************************************************************************/
+
+#include <nuttx/config.h>	/* NuttX configuration settings */
+#include <arch/board/board.h>	/* Board-specific settings */
+#include <arch/irq.h>		/* IRQ definitons */
+
+#include "chip.h"		/* Chip-specific settings */
+#include "up_internal.h"
+#include "up_arch.h"
+
+/*****************************************************************************
+ * Definitions
+ *****************************************************************************/
+
+/* This file holds the NuttX start logic that runs when the SH-1/US7032EVB1
+ * is reset.  This logic must be located in SRAM at 0x0a00:2000.  On that
+ * platform, the entire PROM and the first 8Kb of SRAM are reserved for CMON.
+ */
+
+/*****************************************************************************
+ * External references
+ *****************************************************************************/
+
+/* Called functions */
+
+	.globl	_up_lowsetup		/* Early initialization of UART */
+#ifdef USE_EARLYSERIALINIT
+	.globl	_up_earlyconsoleinit	/* Early initialization of console driver */
+#endif
+#ifdef CONFIG_ARCH_LEDS
+	.globl	_up_ledinit		/* Boot LED setup */
+#endif
+#ifdef CONFIG_DEBUG
+	.globl	_up_lowputc		/* Low-level debug output */
+#endif
+	.globl	_os_start		/* NuttX entry point */
+
+/* Variables set up by the linker script */
+
+	.globl	_sbss			/* Start of BSS */
+	.globl	_ebss			/* End of BSS */
+	.globl	_svect			/* Start of the new vector location */
+
+#ifdef CONFIG_BOOT_RUNFROMFLASH
+	.globl	_eronly			/* Where .data defaults are stored in FLASH */
+	.global	_sdata			/* Start of .data in RAM */
+	.globl	_edata			/* End of .data in RAM */
+#endif
+
+/* Interrupt handlers */
+	.globl	_up_invalid_handler
+#ifdef CONFIG_SH1_DMAC0
+	.globl	_up_dmac0_handler
+#endif
+#ifdef CONFIG_SH1_DMAC1
+	.globl	_up_dmac1_handler
+#endif
+#ifdef CONFIG_SH1_DMAC2
+	.globl	_up_dmac2_handler
+#endif
+#ifdef CONFIG_SH1_DMAC3
+	.globl	_up_dmac3_handler
+#endif
+	.globl	_up_imia0_handler
+	.globl	_up_imib0_handler
+	.globl	_up_ovi0_handler
+#ifdef CONFIG_SH1_ITU1
+	.globl	_up_imia1_handler
+	.globl	_up_imib1_handler
+	.globl	_up_ovi1_handler
+#endif
+#ifdef CONFIG_SH1_ITU2
+	.globl	_up_imia2_handler
+	.globl	_up_imib2_handler
+	.globl	_up_ovi2_handler
+#endif
+#ifdef CONFIG_SH1_ITU3
+	.globl	_up_imia3_handler
+	.globl	_up_imib3_handler
+	.globl	_up_ovi3_handler
+#endif
+#ifdef CONFIG_SH1_ITU4
+	.globl	_up_imia4_handler
+	.globl	_up_imib4_handler
+	.globl	_up_ovi4_handler
+#endif
+#ifdef CONFIG_SH1_SCI0
+	.globl	_up_eri0_handler
+	.globl	_up_rxi0_handler
+	.globl	_up_txi0_handler
+	.globl	_up_tei0_handler
+#endif
+#ifdef CONFIG_SH1_SCI1
+	.globl	_up_eri1_handler
+	.globl	_up_rxi1_handler
+	.globl	_up_txi1_handler
+	.globl	_up_tei1_handler
+#endif
+#ifdef CONFIG_SH1_PCU
+	.globl	_up_pei_handler
+#endif
+#ifdef CONFIG_SH1_AD
+	.globl	_up_aditi_handler
+#endif
+#ifdef CONFIG_SH1_WDT
+	.globl	_up_wdt_handler
+#endif
+#ifdef CONFIG_SH1_CMI
+	.globl	_up_cmi_handler
+#endif
+
+/*****************************************************************************
+ * Macros
+ *****************************************************************************/
+
+/*****************************************************************************
+ * Name: showprogress
+ *
+ * Description:
+ *   Print a character on the UART to show boot status. This macro will
+ *   modify r0, r1, r2 and r14
+ *
+ *****************************************************************************/
+
+	.macro	showprogress, code
+#ifdef CONFIG_DEBUG
+	mov.l   .Llowputc, r0		/* Address of up_earlyconsoleinit */
+	jsr     @r0			/* Call it */
+	mov	#\code, r4		/* Delay slot */
+#endif
+	.endm
+
+/*****************************************************************************
+ * Vectors
+ *****************************************************************************/
+
+	.section	.vects
+
+/*****************************************************************************
+ * Name: __vector_table
+ *
+ * Description:
+ *   Interrupt vector table.  The actual vectors are managed by CMON.  For
+ *   any non-zero settings in the following table, CMON will redirect interrupt
+ *   handling to that function.
+ *
+ *****************************************************************************/
+
+	.globl		__vector_table
+	.type		__vector_table, %object
+__vector_table:
+	/* All of the SH-1 common vectors are copied from the CMON vector
+	 * area to here.  As a result, CMON will continue to intercept these
+	 * vectors.
+	 */
+
+	.long	__start		/* 0-1: Power-on reset (hard, NMI high) PC & SP */
+	.long	_ebss+CONFIG_IDLETHREAD_STACKSIZE-4
+	.long	__start		/* 2-3: Manual reset (soft, NMI low) PC & SP */
+	.long	_ebss+CONFIG_IDLETHREAD_STACKSIZE-4
+
+	.rept SH1_NCMN_VECTORS-4
+	.long	_up_invalid_handler
+	.endr
+
+	/* The remaining vectors are unique to the SH-1 703x family */
+
+#ifdef CONFIG_SH1_DMAC0
+	.long	_up_dmac0_handler		/* 72: DMAC0 DEI0 */
+#else
+	.long	_up_invalid_handler		/* 72: DMAC0 DEI0 */
+#endif
+	.long	_up_invalid_handler		/* 73: Reserved */
+#ifdef CONFIG_SH1_DMAC1
+	.long	_up_dmac1_handler		/* 74: DMAC1 DEI1 */
+#else
+	.long	_up_invalid_handler		/* 74: DMAC1 DEI1 */
+#endif
+	.long	_up_invalid_handler		/* 75: Reserved */
+#ifdef CONFIG_SH1_DMAC2
+	.long	_up_dmac2_handler		/* 76: DMAC2 DEI2 */
+#else
+	.long	_up_invalid_handler		/* 76: DMAC2 DEI2 */
+#endif
+	.long	_up_invalid_handler		/* 77: Reserved */
+#ifdef CONFIG_SH1_DMAC3
+	.long	_up_dmac3_handler		/* 78: DMAC3 DEI3 */
+#else
+	.long	_up_invalid_handler		/* 78: DMAC3 DEI3 */
+#endif
+	.long	_up_invalid_handler		/* 79: Reserved */
+	.long	_up_imia0_handler		/* 80: ITU0 IMIA0 */
+	.long	_up_imib0_handler		/* 81:      IMIB0 */
+	.long	_up_ovi0_handler		/* 82:      OVI0 */
+	.long	_up_invalid_handler		/* 83: Reserved */
+#ifdef CONFIG_SH1_ITU1
+	.long	_up_imia1_handler		/* 84: ITU1 IMIA1 */
+	.long	_up_imib1_handler		/* 85:      IMIB1 */
+	.long	_up_ovi1_handler		/* 86:      OVI1 */
+#else
+	.long	_up_invalid_handler		/* 84: ITU1 IMIA1 */
+	.long	_up_invalid_handler		/* 85:      IMIB1 */
+	.long	_up_invalid_handler		/* 86:      OVI1 */
+#endif
+	.long	_up_invalid_handler		/* 87: Reserved */
+#ifdef CONFIG_SH1_ITU2
+	.long	_up_imia2_handler		/* 88: ITU2 IMIA2 */
+	.long	_up_imib2_handler		/* 89:      IMIB2 */
+	.long	_up_ovi2_handler		/* 90:      OVI2 */
+#else
+	.long	_up_invalid_handler		/* 88: ITU2 IMIA2 */
+	.long	_up_invalid_handler		/* 89:      IMIB2 */
+	.long	_up_invalid_handler		/* 90:      OVI2 */
+#endif
+	.long	_up_invalid_handler		/* 91: Reserved */
+#ifdef CONFIG_SH1_ITU3
+	.long	_up_imia3_handler		/* 92: ITU3 IMIA3 */
+	.long	_up_imib3_handler		/* 93:      IMIB3 */
+	.long	_up_ovi3_handler		/* 94:      OVI3 */
+#else
+	.long	_up_invalid_handler		/* 92: ITU3 IMIA3 */
+	.long	_up_invalid_handler		/* 93:      IMIB3 */
+	.long	_up_invalid_handler		/* 94:      OVI3 */
+#endif
+	.long	_up_invalid_handler		/* 95: Reserved */
+#ifdef CONFIG_SH1_ITU4
+	.long	_up_imia4_handler		/* 96: ITU4 IMIA4 */
+	.long	_up_imib4_handler		/* 97:      IMIB4 */
+	.long	_up_ovi4_handler		/* 98:      OVI4 */
+#else
+	.long	_up_invalid_handler		/* 96: ITU4 IMIA4 */
+	.long	_up_invalid_handler		/* 97:      IMIB4 */
+	.long	_up_invalid_handler		/* 98:      OVI4 */
+#endif
+	.long	_up_invalid_handler		/* 99: Reserved */
+#ifdef CONFIG_SH1_SCI0
+	.long	_up_eri0_handler		/* 100: SCI0 ERI0 */
+	.long	_up_rxi0_handler		/* 101:      RxI0 */
+	.long	_up_txi0_handler		/* 102:      TxI0 */
+	.long	_up_tei0_handler		/* 103:      TEI0 */
+#else
+	.long	_up_invalid_handler		/* 100: SCI0 ERI0 */
+	.long	_up_invalid_handler		/* 101:      RxI0 */
+	.long	_up_invalid_handler		/* 102:      TxI0 */
+	.long	_up_invalid_handler		/* 103:      TEI0 */
+#endif
+#ifdef CONFIG_SH1_SCI1
+	.long	_up_eri1_handler		/* 104: SCI1 ERI1 */
+	.long	_up_rxi1_handler		/* 105:      RxI1 */
+	.long	_up_txi1_handler		/* 106:      TxI1 */
+	.long	_up_tei1_handler		/* 107:      TEI1 */
+#else
+	.long	_up_invalid_handler		/* 104: SCI1 ERI1 */
+	.long	_up_invalid_handler		/* 105:      RxI1 */
+	.long	_up_invalid_handler		/* 106:      TxI1 */
+	.long	_up_invalid_handler		/* 107:      TEI1 */
+#endif
+#ifdef CONFIG_SH1_PCU
+	.long	_up_pei_handler			/* 108: Parity control unit PEI */
+#else
+	.long	_up_invalid_handler		/* 108: Parity control unit PEI */
+#endif
+#ifdef CONFIG_SH1_AD
+	.long	_up_aditi_handler		/* 109: A/D ITI */
+#else
+	.long	_up_invalid_handler		/* 109: A/D ITI */
+#endif
+	.long	_up_invalid_handler		/* 110: Reserved */
+	.long	_up_invalid_handler		/* 111: Reserved */
+#ifdef CONFIG_SH1_WDT
+	.long	_up_wdt_handler			/* 112: WDT ITI */
+#else
+	.long	_up_invalid_handler		/* 112: WDT ITI */
+#endif
+#ifdef CONFIG_SH1_CMI
+	.long	_up_cmi_handler			/* 113: REF CMI */
+#else
+	.long	_up_invalid_handler		/* 113: REF CMI */
+#endif
+	.rept (SH1_LAST_VNDX-SH1_CMI_VNDX)	/* 114-255: Reserved */
+	.long	_up_invalid_handler
+	.endr
+	.size	__vector_table, . - __vector_table
+
+/*****************************************************************************
+ * Text
+ *****************************************************************************/
+
+	.section	.reset
+
+/*****************************************************************************
+ * Name: __start
+ *
+ * Description:
+ *   Reset entry point.  This is the first function to execute when the
+ *   processor is reset.  It initializes hardware and then gives control to
+ *   NuttX.  Nearly all SH-1 resources have already been setup by CMON so all
+ *   that is necessary for us to do here is setup the stack pointer and BSS.
+ *
+ *****************************************************************************/
+
+	.global __start
+	.type	__start, #function
+
+__start:
+	/* Initialize stack pointer to the preallocated stack */
+	mov.l	.Lstack, r15
+	
+	/* set up the bus controller for the EVB */
+
+	mov.l	.Lwcr1, r0
+	sub	r1,r1
+	mov.w	r1, @r0
+
+	/* Configure the BSR to use /LBS, /HBS, /WR */
+
+	mov.l   .Lbcr, r0
+	mov.w   .Lbas, r1
+	bra     __start0
+	mov.w   r1, @r0
+	
+	.align 2
+.Lstack:
+	.long	_ebss+CONFIG_IDLETHREAD_STACKSIZE-4
+.Lwcr1:
+	.long	0x5ffffa2
+.Lbcr:
+	.long  0x5ffffa0
+.Lbas:
+	.word  0x0800
+
+__start0:
+	/* Copy the monitor vectors to a002000-a00211f */
+
+	mov	#0, r0			/* R0: Monitor vector table at address 0 in PROM */
+	mov.l	.Lsvect, r1		/* R1: Redirected vector table in SRAM */
+	mov.l	.Lvectend, r3		/* R3: Copy only up to external interrupts */
+1:
+	mov.l	@r0, r2			/* R2: Value from mnitor monitor vector table */
+	mov.l	r2, @r1			/* Write into SRAM vector table */
+	add	#4, r0			/* R0: Address of next vector to read from monitor vector table */
+	add	#4, r1			/* R1: Address of next vector to write to SRAM vector table */
+	cmp/gt	r0, r3			/* Copy only only up to external interrupts at */
+	bt	1b			/* Continue looping until all copied */
+	nop				/* Delay slot */
+
+	/* Update the VBR to show new adddress of vector table */
+
+	mov.l	.Lsvect, r0		/* R0: Address of SRAM vector table */
+	ldc	r0, vbr			/* Set VBR to start of SRAM vector table */
+
+	/* Initialize data segement */
+
+#ifdef CONFIG_BOOT_RUNFROMFLASH
+	mov.l	.Lsdata, r0		/* R0: Start of .data segment */
+	mov.l	.Ledata, r1		/* R1: End+1 of .data segment */
+	mov.l	.Leronly, r2		/* R2: Start of FLASH .data segment copy */
+2:
+	mov.l	@r2, r3			/* R3: Next byte from FLASH copy */
+	mov.l	r3, @r0			/* Copy to .data */
+	add	#4, r2			/* R2: Address of next byte to read from FLASH */
+	add	#4, r0			/* R0: Address to write next byte to .data */
+	cmp/gt	r0, r1			/* End of .data? */
+	bt	2b			/* Loop until end of data */
+	nop				/* Delay slot */
+#endif
+
+	/* Clear BSS */
+
+	mov.l   .Lsbss, r0		/* R0: Start of BSS segment */
+	mov.l   .Lebss, r1		/* R1: End+1 of BSS segment */
+	mov	#0, r2			/* R2: Value = 0 */
+3:
+	mov.l	r2, @r0			/* Clear the next word in BSS */
+	add	#4, r0			/* R0: Address of next byte to clear in BSS */
+	cmp/ge	r0, r1			/* End of BSS? */
+	bt	3b			/* Loop until the end of BSS */
+	nop				/* Delay slot */
+
+	/* Configure the uart so that we can get debug output as soon
+	 * as possible.
+	 */
+
+	mov.l   .Llowsetup, r0		/* Address of up_lowsetup */
+	jsr     @r0			/* Call it */
+	or      r0, r0			/* Delay slot */
+
+	showprogress 'A'
+
+	/* Perform early console initialization */
+
+#ifdef USE_EARLYSERIALINIT
+	mov.l   .Learlyconsole, r0	/* Address of up_earlyconsoleinit */
+	jsr     @r0			/* Call it */
+	or      r0, r0			/* Delay slot */
+#endif
+
+	showprogress 'B'
+
+	/* Call C++ constructors */
+
+#ifdef CONFIG_CPLUSPLUS
+#  warning "No C++ support yet"
+	showprogress 'C'
+#endif
+	showprogress '\n'
+
+	/* Initialize onboard LEDs */
+
+#ifdef CONFIG_ARCH_LEDS
+	mov.l   .Lledinit, r0		/* Address of up_ledinit */
+	jsr     @r0			/* Call it */
+	or      r0, r0			/* Delay slot */
+#endif
+
+	/* Then jump to NuttX entry */
+
+	mov.l   .Losstart,r0
+	jsr     @r0
+	or      r0, r0
+
+	/* Shouldn't get here */
+
+	/* Call destructors  -- never get here */
+
+#ifdef CONFIG_CPLUSPLUS
+#  warning "No C++ support yet"
+#endif
+
+4:  nop
+	bra 4b
+	nop
+
+	.align 2
+#ifdef CONFIG_BOOT_RUNFROMFLASH
+.Leronly:
+	.long   _eronly
+.Lsdata:
+	.long   _sdata
+.Ledata:
+	.long   _edata
+#endif
+.Lsbss:  
+	.long   _sbss
+.Lebss:
+	.long   _ebss
+#ifdef USE_EARLYSERIALINIT
+.Learlyconsole:
+	.long	_up_earlyconsoleinit
+#endif
+.Llowsetup:
+	.long	_up_lowsetup
+#ifdef CONFIG_DEBUG
+.Llowputc:
+	.long	_up_lowputc
+#endif
+.Lledinit:
+	.long	_up_ledinit
+.Losstart:
+	.long   _os_start
+.Lsvect:
+	.long   _svect
+.Lvectend:
+	.long   ((4*SH1_NCMN_VECTORS)-1)
+	.size	__start, .-__start
+
+/*****************************************************************************
+ * DATA
+ *****************************************************************************/
+
+	.section	.data
+
+	/* This global variable is unsigned long g_heapbase and is
+	 * exported from here only because of its coupling to the stack
+	 * above.
+	 */
+
+	.data
+	.align	4
+	.globl	_g_heapbase
+	.type	_g_heapbase, object
+_g_heapbase:
+	.long	_ebss+CONFIG_IDLETHREAD_STACKSIZE
+	.size	_g_heapbase, .-_g_heapbase
+
+	.end
+

nuttx/arch/sh/src/sh1/sh1_initialstate.c

@@ -0,0 +1,129 @@
+/****************************************************************************
+ *  arch/sh/src/sh1/sh1_initialstate.c
+ *
+ *   Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+#include <string.h>
+#include <nuttx/arch.h>
+#include "up_internal.h"
+#include "up_arch.h"
+
+/****************************************************************************
+ * Private Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_getsr
+ ****************************************************************************/
+
+static inline irqstate_t up_getsr(void)
+{
+  irqstate_t flags;
+
+  __asm__ __volatile__
+    (
+      "stc     sr, %0\n\t"
+      : "=&z" (flags)
+      :
+      : "memory"
+    );
+  return flags;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_initial_state
+ *
+ * Description:
+ *   A new thread is being started and a new TCB
+ *   has been created. This function is called to initialize
+ *   the processor specific portions of the new TCB.
+ *
+ *   This function must setup the intial architecture registers
+ *   and/or  stack so that execution will begin at tcb->start
+ *   on the next context switch.
+ *
+ ****************************************************************************/
+
+void up_initial_state(_TCB *tcb)
+{
+  struct xcptcontext *xcp = &tcb->xcp;
+
+  /* Initialize the initial exception register context structure */
+
+  memset(xcp, 0, sizeof(struct xcptcontext));
+
+  /* Set the initial stack pointer to the "base" of the allocated stack */
+
+  xcp->regs[REG_SP] = (uint32_t)tcb->adj_stack_ptr;
+
+  /* Save the task entry point */
+
+  xcp->regs[REG_PC] = (uint32_t)tcb->start;
+
+  /* Set supervisor- or user-mode, depending on how NuttX is configured and
+   * what kind of thread is being started.  Disable FIQs in any event
+   *
+   * If the kernel build is not selected, then all threads run in
+   * supervisor-mode.
+   */
+
+#ifdef CONFIG_NUTTX_KERNEL
+#  error "Missing logic for the CONFIG_NUTTX_KERNEL build"
+#endif
+
+  /* Enable or disable interrupts, based on user configuration */
+
+#ifdef CONFIG_SUPPRESS_INTERRUPTS
+  xcp->regs[REG_SR] = up_getsr() | 0x000000f0;
+#else
+  xcp->regs[REG_SR] = up_getsr() & ~0x000000f0;
+#endif
+}

nuttx/arch/sh/src/sh1/sh1_irq.c

@@ -0,0 +1,285 @@
+/****************************************************************************
+ * arch/sh/src/sh1/sh1_irq.c
+ *
+ *   Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+#include "chip.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+volatile uint32_t *current_regs;
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Funtions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_irqinitialize
+ ****************************************************************************/
+
+void up_irqinitialize(void)
+{
+  /* Currents_regs is non-NULL only while processing an interrupt */
+
+  current_regs = NULL;
+
+  /* Enable interrupts */
+
+#ifndef CONFIG_SUPPRESS_INTERRUPTS
+  irqenable();
+#endif
+}
+
+/****************************************************************************
+ * Name: up_prioritize_irq
+ *
+ * Description:
+ *   set interrupt priority
+ *
+ ****************************************************************************/
+
+void up_prioritize_irq(int irq, int priority)
+{
+  uint16_t mask;
+  uint16_t reg16;
+  uint32_t reg;
+  int      shift;
+
+#ifdef CONFIG_DEBUG
+  if ((unsigned) irq > NR_IRQS || (unsigned)priority > 15)
+    {
+      dbg("Invalid parameters\n");
+      return;
+    }
+#endif
+
+  /* Get the register to set, the mask for the bits to be set, and
+   * the shift value to position the bits in the register.
+   */
+
+  switch (irq)
+    {
+#if 0 /* Not yet supported */
+    case SH1_IRQ0_IRQ:
+      mask  = SH1_IPRA_IRQ0MASK;
+      shift = SH1_IPRA_IRQ0SHIFT;
+      goto ipra;
+
+    case SH1_IRQ1_IRQ:
+      mask  = SH1_IPRA_IRQ1MASK;
+      shift = SH1_IPRA_IRQ1SHIFT;
+      goto ipra;
+
+    case SH1_IRQ2_IRQ:
+      mask  = SH1_IPRA_IRQ2MASK;
+      shift = SH1_IPRA_IRQ2SHIFT;
+      goto ipra;
+
+    case SH1_IRQ3_IRQ:
+      mask  = SH1_IPRA_IRQ3MASK;
+      shift = SH1_IPRA_IRQ3SHIFT;
+      goto ipra;
+    ipra:
+      reg   = SH1_INTC_IPRA;
+      break;
+
+    case SH1_IRQ4_IRQ:
+      mask  = SH1_IPRB_IRQ4MASK;
+      shift = SH1_IPRB_IRQ4SHIFT;
+      goto iprb;
+
+    case SH1_IRQ5_IRQ:
+      mask  = SH1_IPRB_IRQ5MASK;
+      shift = SH1_IPRB_IRQ5SHIFT;
+      goto iprb;
+
+    case SH1_IRQ6_IRQ:
+      mask  = SH1_IPRB_IRQ6MASK;
+      shift = SH1_IPRB_IRQ6SHIFT;
+      goto iprb;
+
+    case SH1_IRQ7_IRQ:
+      mask  = SH1_IPRB_IRQ7MASK;
+      shift = SH1_IPRB_IRQ7SHIFT;
+      goto iprb;
+    iprb:
+      reg   = SH1_INTC_IPRB;
+      break;
+#endif
+
+#if defined(CONFIG_SH1_DMAC0) || defined(CONFIG_SH1_DMAC1)
+    case SH1_DEI0_IRQ:
+    case SH1_DEI1_IRQ:
+      mask  = SH1_IPRC_DM01MASK;
+      shift = SH1_IPRC_DM01SHIFT;
+      goto iprc;
+#endif
+
+#if defined(CONFIG_SH1_DMAC2) || defined(CONFIG_SH1_DMAC3)
+    case SH1_DEI2_IRQ:
+    case SH1_DEI3_IRQ:
+      mask  = SH1_IPRC_DM23MASK;
+      shift = SH1_IPRC_DM23SHIFT;
+      goto iprc;
+#endif
+
+#ifdef CONFIG_SH1_ITU1
+    case SH1_IMIA1_IRQ:
+    case SH1_IMIB1_IRQ:
+    case SH1_OVI1_IRQ:
+      mask  = SH1_IPRC_ITU1MASK;
+      shift = SH1_IPRC_ITU1SHIFT;
+      goto iprc;
+#endif
+
+    case SH1_IMIA0_IRQ:
+    case SH1_IMIB0_IRQ:
+    case SH1_OVI0_IRQ:
+      mask  = SH1_IPRC_ITU0MASK;
+      shift = SH1_IPRC_ITU0SHIFT;
+      goto iprc;
+    iprc:
+      reg   = SH1_INTC_IPRC;
+      break;
+
+#if defined(CONFIG_SH1_ITU2) || defined(CONFIG_SH1_ITU3) || \
+    defined(CONFIG_SH1_ITU4) || defined(CONFIG_SH1_SCI0)
+#ifdef CONFIG_SH1_ITU2
+    case SH1_IMIA2_IRQ:
+    case SH1_IMIB2_IRQ:
+    case SH1_OVI2_IRQ:
+      mask  = SH1_IPRD_ITU2MASK;
+      shift = SH1_IPRD_ITU2SHIFT;
+      goto iprd;
+#endif
+#ifdef CONFIG_SH1_ITU3
+    case SH1_IMIA3_IRQ:
+    case SH1_IMIB3_IRQ:
+    case SH1_OVI3_IRQ:
+      mask  = SH1_IPRD_ITU3MASK;
+      shift = SH1_IPRD_ITU3SHIFT;
+      goto iprd;
+#endif
+#ifdef CONFIG_SH1_ITU4
+    case SH1_IMIA4_IRQ:
+    case SH1_IMIB4_IRQ:
+    case SH1_OVI4_IRQ:
+      mask  = SH1_IPRD_ITU4MASK;
+      shift = SH1_IPRD_ITU4SHIFT;
+      goto iprd;
+#endif
+#ifdef CONFIG_SH1_SCI0
+    case SH1_ERI0_IRQ:
+    case SH1_RXI0_IRQ:
+    case SH1_TXI0_IRQ:
+    case SH1_TEI0_IRQ:
+      mask  = SH1_IPRD_SCI0MASK;
+      shift = SH1_IPRD_SCI0SHIFT;
+      goto iprd;
+#endif
+    iprd:
+      reg   = SH1_INTC_IPRD;
+      break;
+#endif
+
+#if defined(CONFIG_SH1_SCI1) || defined(CONFIG_SH1_PCU) || \
+    defined(CONFIG_SH1_AD) || defined(CONFIG_SH1_WDT) || defined(CONFIG_SH1_CMI)
+#ifdef CONFIG_SH1_SCI1
+    case SH1_ERI1_IRQ:
+    case SH1_RXI1_IRQ:
+    case SH1_TXI1_IRQ:
+    case SH1_TEI1_IRQ:
+      mask  = SH1_IPRE_SCI1MASK;
+      shift = SH1_IPRE_SCI1SHIFT;
+      goto ipre;
+#endif
+#if defined(CONFIG_SH1_PCU) || defined(CONFIG_SH1_AD)
+    case SH1_PEI_IRQ:
+    case SH1_ADITI_IRQ:
+      mask  = SH1_IPRE_PRADMASK;
+      shift = SH1_IPRE_PRADSHIFT;
+      goto ipre;
+#endif
+#if defined(CONFIG_SH1_WDT) || defined(CONFIG_SH1_CMI)
+    case SH1_WDTITI_IRQ:
+    case SH1_CMI_IRQ:
+      mask  = SH1_IPRE_WDRFMASK;
+      shift = SH1_IPRE_WDRFSHIFT;
+      goto ipre;
+#endif
+    ipre:
+      reg   = SH1_INTC_IPRE;
+      break;
+#endif
+
+    default:
+      dbg("Invalid irq=%d\n", irq);
+      return;
+    }
+
+  /* Then set the priority bits */
+
+  reg16  = getreg16(reg);
+  reg16 &= ~mask;
+  reg16 |= (priority << shift);
+  putreg16(reg16, reg);
+}
+

nuttx/arch/sh/src/sh1/sh1_lowputc.c

@@ -0,0 +1,265 @@
+/**************************************************************************
+ * arch/sh/src/sh1/sh1_lowputc.c
+ *
+ *   Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ **************************************************************************/
+
+/**************************************************************************
+ * Included Files
+ **************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <nuttx/arch.h>
+
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+#include "up_internal.h"
+
+/**************************************************************************
+ * Private Definitions
+ **************************************************************************/
+
+/* Configuration **********************************************************/
+
+/* Is there a serial console? */
+
+#if defined(CONFIG_SCI0_SERIAL_CONSOLE) && defined(CONFIG_SH1_SCI0)
+#  define HAVE_CONSOLE 1
+#  undef CONFIG_SCI1_SERIAL_CONSOLE
+#elif defined(CONFIG_SCI1_SERIAL_CONSOLE) && defined(CONFIG_SH1_SCI1)
+#  define HAVE_CONSOLE 1
+#  undef CONFIG_SCI0_SERIAL_CONSOLE
+#else
+#  if defined(CONFIG_SCI0_SERIAL_CONSOLE) || defined(CONFIG_SCI1_SERIAL_CONSOLE)
+#    error "Serial console selected, but corresponding SCI not enabled"
+#  endif
+#  undef HAVE_CONSOLE
+#endif
+
+/* Select UART parameters for the selected console */
+
+#if defined(CONFIG_SCI0_SERIAL_CONSOLE)
+#  define SH1_SCI_BASE     SH1_SCI0_BASE
+#  define SH1_SCI_BAUD     CONFIG_SCI0_BAUD
+#  define SH1_SCI_BITS     CONFIG_SCI0_BITS
+#  define SH1_SCI_PARITY   CONFIG_SCI0_PARITY
+#  define SH1_SCI_2STOP    CONFIG_SCI0_2STOP
+#elif defined(CONFIG_SCI1_SERIAL_CONSOLE)
+#  define SH1_SCI_BASE     SH1_SCI1_BASE
+#  define SH1_SCI_BAUD     CONFIG_SCI1_BAUD
+#  define SH1_SCI_BITS     CONFIG_SCI1_BITS
+#  define SH1_SCI_PARITY   CONFIG_SCI1_PARITY
+#  define SH1_SCI_2STOP    CONFIG_SCI1_2STOP
+#else
+#  error "No CONFIG_SCIn_SERIAL_CONSOLE Setting"
+#endif
+
+/* Get mode setting */
+
+#if SH1_SCI_BITS == 7
+#  define SH1_SMR_MODE SH1_SCISMR_CHR
+#elif SH1_SCI_BITS == 8
+#  define SH1_SMR_MODE (0)
+#else
+#  error "Number of bits not supported"
+#endif
+
+#if SH1_SCI_PARITY == 0
+#  define SH1_SMR_PARITY (0)
+#elif SH1_SCI_PARITY == 1
+#  define SH1_SMR_PARITY (SH1_SCISMR_PE|SH1_SCISMR_OE)
+#elif SH1_SCI_PARITY == 2
+#  define SH1_SMR_PARITY SH1_SCISMR_PE
+#else
+#  error "Invalid parity selection"
+#endif
+
+#if SH1_SCI_2STOP != 0
+#  define SH1_SMR_STOP SH1_SCISMR_STOP
+#else
+#  define SH1_SMR_STOP (0)
+#endif
+
+/* The full SMR setting also includes internal clocking with no divisor,
+ * aysnchronous operation and multiprocessor disabled:
+ */
+
+#define SH1_SMR_VALUE (SH1_SMR_MODE|SH1_SMR_PARITY|SH1_SMR_STOP)
+
+/* Clocking ***************************************************************/
+
+/* The calculation of the BRR to achieve the desired BAUD is given by the
+ * following formula:
+ *
+ *   brr = (f/(64*2**(2n-1)*b))-1
+ *
+ * Where:
+ *
+ *   b = bit rate
+ *   f = frequency (Hz)
+ *   n = divider setting (0, 1, 2, 3)
+ *
+ * For n == 0, this simplifies to:
+ *
+ *   brr = (f/(32*b))-1
+ *
+ * For example, if the processor is clocked at 10 MHz and 9600 is the
+ * desired BAUD:
+ *
+ *   brr = 10,000,000 / (32 * 9600) - 1 = 31.552 (or 32 after rounding)
+ */
+
+#define SH1_DIVISOR (32 * SH1_SCI_BAUD)
+#define SH1_BRR     (((SH1_CLOCK + (SH1_DIVISOR/2))/SH1_DIVISOR)-1)
+
+/**************************************************************************
+ * Private Types
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Function Prototypes
+ **************************************************************************/
+
+/**************************************************************************
+ * Global Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Name: up_txready
+ *
+ * Description:
+ *   Return TRUE of the Transmit Data Register is empty
+ *
+ **************************************************************************/
+
+#ifdef HAVE_CONSOLE
+static inline int up_txready(void)
+{
+  /* Check the TDRE bit in the SSR.  1=TDR is empty */
+
+  return ((getreg8(SH1_SCI_BASE + SH1_SCI_SSR_OFFSET) & SH1_SCISSR_TDRE) != 0);
+}
+#endif
+
+/**************************************************************************
+ * Public Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Name: up_lowputc
+ *
+ * Description:
+ *   Output one byte on the serial console
+ *
+ **************************************************************************/
+
+void up_lowputc(char ch)
+{
+#ifdef HAVE_CONSOLE
+  uint8_t ssr;
+
+  /* Wait until the TDR is avaible */
+
+  while (!up_txready());
+
+  /* Write the data to the TDR */
+
+  putreg8(ch, SH1_SCI_BASE + SH1_SCI_TDR_OFFSET);
+
+  /* Clear the TDRE bit in the SSR */
+
+  ssr  = getreg8(SH1_SCI_BASE + SH1_SCI_SSR_OFFSET);
+  ssr &= ~SH1_SCISSR_TDRE;
+  putreg8(ssr, SH1_SCI_BASE + SH1_SCI_SSR_OFFSET);
+#endif
+}
+
+/**************************************************************************
+ * Name: up_lowsetup
+ *
+ * Description:
+ *   This performs basic initialization of the UART used for the serial
+ *   console.  Its purpose is to get the console output availabe as soon
+ *   as possible.
+ *
+ **************************************************************************/
+
+void up_lowsetup(void)
+{
+#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_SCI_CONFIG)
+  uint8_t scr;
+
+  /* Disable the transmitter and receiver */
+
+  scr  = getreg8(SH1_SCI_BASE + SH1_SCI_SCR_OFFSET);
+  scr &= ~(SH1_SCISCR_TE | SH1_SCISCR_RE);
+  putreg8(scr, SH1_SCI_BASE + SH1_SCI_SCR_OFFSET);
+
+  /* Set communication to be asynchronous with the configured number of data
+   * bits, parity, and stop bits.  Use the internal clock (undivided)
+   */
+
+  putreg8(SH1_SMR_VALUE, SH1_SCI_BASE + SH1_SCI_SMR_OFFSET);
+
+  /* Set the baud based on the configured console baud and configured
+   * system clock.
+   */
+
+  putreg8(SH1_BRR, SH1_SCI_BASE + SH1_SCI_BRR_OFFSET);
+
+  /* Select the internal clock source as input */
+
+  scr &= ~SH1_SCISCR_CKEMASK;
+  putreg8(scr, SH1_SCI_BASE + SH1_SCI_SCR_OFFSET);
+
+  /* Wait a bit for the clocking to settle */
+
+  up_udelay(100);
+
+  /* Then enable the transmitter and reciever */
+
+  scr |= (SH1_SCISCR_TE | SH1_SCISCR_RE);
+  putreg8(scr, SH1_SCI_BASE + SH1_SCI_SCR_OFFSET);
+#endif
+}

nuttx/arch/sh/src/sh1/sh1_saveusercontext.S

@@ -0,0 +1,121 @@
+/**************************************************************************
+ * arch/sh/src/sh1/sh1_saveusercontext.S
+ *
+ *   Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ **************************************************************************/
+
+/**************************************************************************
+ * Included Files
+ **************************************************************************/
+
+#include <nuttx/irq.h>
+#include "up_internal.h"
+
+/**************************************************************************
+ * Private Definitions
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Types
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Function Prototypes
+ **************************************************************************/
+
+/**************************************************************************
+ * Global Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Public Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Name: up_saveusercontext
+ **************************************************************************/
+
+	.text
+	.globl	_up_saveusercontext
+	.type	_up_saveusercontext, function
+_up_saveusercontext:
+
+	/* On entry, R4 contains a reference to the register save structure
+	 * to populate.
+	 *
+	 * Re-position to the end of the structure (+4_ so that we can use
+	 * auto decrement 
+	 */
+
+	add	#(XCPTCONTEXT_SIZE), r4	/* R4: Address of last entry + 4 */
+
+	/* Save the necessary registers */
+
+	stc     sr, r0			/* Get and save the SR */
+	mov.l	r0, @-r4
+	sts.l	pr, @-r4		/* The return address is the restore PC */
+	add	#-(7*4), r4		/* Skip over r4, r7-r1.  R4 points at R1 storage */
+
+	/* Save a nonzero value for R0 in the register save area.  This will
+	 * will be the apparent return value when a context switch back to
+	 * this thread is performed.
+	 */
+
+	mov	#1, r0			/* Save R0=1 (return value) */
+	mov.l	r0, @-r4
+	add	#-(2*4), r4		/* Skip over mach and macl.  R4 points at R15 storage. */
+	mov.l	r15, @-r4		/* SP */
+	stc.l	gbr, @-r4		/* GBR & PR */
+	sts.l	pr, @-r4
+
+	mov.l	r14, @-r4		/* R14-R8 */
+	mov.l	r13, @-r4
+	mov.l	r12, @-r4
+	mov.l	r11, @-r4
+	mov.l	r10, @-r4
+	mov.l	r9, @-r4
+	mov.l	r8, @-r4
+
+	/* And return zero */
+
+	rts
+	mov	#0, r0
+	.size	up_saveusercontext, . - up_saveusercontext
+	.end

nuttx/arch/sh/src/sh1/sh1_schedulesigaction.c

@@ -0,0 +1,197 @@
+/****************************************************************************
+ * arch/sh/src/sh1/sh1_schedulesigaction.c
+ *
+ *   Copyright (C) 2008-2010 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <sched.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+
+#include "os_internal.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+#ifndef CONFIG_DISABLE_SIGNALS
+
+/****************************************************************************
+ * Private Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Funictions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_schedule_sigaction
+ *
+ * Description:
+ *   This function is called by the OS when one or more
+ *   signal handling actions have been queued for execution.
+ *   The architecture specific code must configure things so
+ *   that the 'igdeliver' callback is executed on the thread
+ *   specified by 'tcb' as soon as possible.
+ *
+ *   This function may be called from interrupt handling logic.
+ *
+ *   This operation should not cause the task to be unblocked
+ *   nor should it cause any immediate execution of sigdeliver.
+ *   Typically, a few cases need to be considered:
+ *
+ *   (1) This function may be called from an interrupt handler
+ *       During interrupt processing, all xcptcontext structures
+ *       should be valid for all tasks.  That structure should
+ *       be modified to invoke sigdeliver() either on return
+ *       from (this) interrupt or on some subsequent context
+ *       switch to the recipient task.
+ *   (2) If not in an interrupt handler and the tcb is NOT
+ *       the currently executing task, then again just modify
+ *       the saved xcptcontext structure for the recipient
+ *       task so it will invoke sigdeliver when that task is
+ *       later resumed.
+ *   (3) If not in an interrupt handler and the tcb IS the
+ *       currently executing task -- just call the signal
+ *       handler now.
+ *
+ ****************************************************************************/
+
+void up_schedule_sigaction(_TCB *tcb, sig_deliver_t sigdeliver)
+{
+  /* Refuse to handle nested signal actions */
+
+  sdbg("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
+
+  if (!tcb->xcp.sigdeliver)
+    {
+      irqstate_t flags;
+
+      /* Make sure that interrupts are disabled */
+
+      flags = irqsave();
+
+      /* First, handle some special cases when the signal is
+       * being delivered to the currently executing task.
+       */
+
+      sdbg("rtcb=0x%p current_regs=0x%p\n", g_readytorun.head, current_regs);
+
+      if (tcb == (_TCB*)g_readytorun.head)
+        {
+          /* CASE 1:  We are not in an interrupt handler and
+           * a task is signalling itself for some reason.
+           */
+
+          if (!current_regs)
+            {
+              /* In this case just deliver the signal now. */
+
+              sigdeliver(tcb);
+            }
+
+          /* CASE 2:  We are in an interrupt handler AND the
+           * interrupted task is the same as the one that
+           * must receive the signal, then we will have to modify
+           * the return state as well as the state in the TCB.
+           */
+
+          else
+            {
+              /* Save the return PC and SR and one scratch register
+               * These will be restored by the signal trampoline after
+               * the signals have been delivered.
+               */
+
+              tcb->xcp.sigdeliver   = sigdeliver;
+              tcb->xcp.saved_pc     = current_regs[REG_PC];
+              tcb->xcp.saved_sr     = current_regs[REG_SR];
+
+              /* Then set up to vector to the trampoline with interrupts
+               * disabled
+               */
+
+              current_regs[REG_PC]  = (uint32_t)up_sigdeliver;
+              current_regs[REG_SR] |= 0x000000f0;
+
+              /* And make sure that the saved context in the TCB
+               * is the same as the interrupt return context.
+               */
+
+              up_copystate(tcb->xcp.regs, current_regs);
+            }
+        }
+
+      /* Otherwise, we are (1) signaling a task is not running
+       * from an interrupt handler or (2) we are not in an
+       * interrupt handler and the running task is signalling
+       * some non-running task.
+       */
+
+      else
+        {
+          /* Save the return PC and SR and one scratch register
+           * These will be restored by the signal trampoline after
+           * the signals have been delivered.
+           */
+
+          tcb->xcp.sigdeliver    = sigdeliver;
+          tcb->xcp.saved_pc      = tcb->xcp.regs[REG_PC];
+          tcb->xcp.saved_sr      = tcb->xcp.regs[REG_SR];
+
+          /* Then set up to vector to the trampoline with interrupts
+           * disabled
+           */
+
+          tcb->xcp.regs[REG_PC]  = (uint32_t)up_sigdeliver;
+          tcb->xcp.regs[REG_SR] |= 0x000000f0 ;
+        }
+
+      irqrestore(flags);
+    }
+}
+
+#endif /* !CONFIG_DISABLE_SIGNALS */

nuttx/arch/sh/src/sh1/sh1_serial.c

@@ -0,0 +1,957 @@
+/****************************************************************************
+ * arch/sh/src/sh1/sh1_serial.c
+ *
+ *   Copyright (C) 2008-2009, 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <semaphore.h>
+#include <string.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/serial/serial.h>
+#include <arch/serial.h>
+
+#include "chip.h"
+#include "up_arch.h"
+#include "up_internal.h"
+#include "os_internal.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/* Some sanity checks *******************************************************/
+
+/* Are there any SCIs? */
+
+#if !defined(CONFIG_SH1_SCI0) && !defined(CONFIG_SH1_SCI1)
+#  ifdef USE_SERIALDRIVER
+#    error "Serial driver selected, but SCIs not enabled"
+#    undef USE_SERIALDRIVER
+#  endif
+#endif
+
+/* Is there a serial console? */
+
+#if defined(CONFIG_SCI0_SERIAL_CONSOLE) && defined(CONFIG_SH1_SCI0)
+#  define HAVE_CONSOLE 1
+#  undef CONFIG_SCI1_SERIAL_CONSOLE
+#elif defined(CONFIG_SCI1_SERIAL_CONSOLE) && defined(CONFIG_SH1_SCI1)
+#  define HAVE_CONSOLE 1
+#  undef CONFIG_SCI0_SERIAL_CONSOLE
+#else
+#  if defined(CONFIG_SCI0_SERIAL_CONSOLE) || defined(CONFIG_SCI1_SERIAL_CONSOLE)
+#    error "Serial console selected, but corresponding SCI not enabled"
+#  endif
+#  undef HAVE_CONSOLE
+#  undef CONFIG_SCI0_SERIAL_CONSOLE
+#  undef CONFIG_SCI1_SERIAL_CONSOLE
+#endif
+
+#ifdef USE_SERIALDRIVER
+
+/* Which SCI with be tty0/console and which tty1? */
+
+/* CONFIG_SCI0_SERIAL_CONSOLE (implies CONFIG_SH1_SCI0 also defined) */
+
+#if defined(CONFIG_SCI0_SERIAL_CONSOLE)
+#  define CONSOLE_DEV     g_sci0port     /* SCI0 is console */
+#  define TTYS0_DEV       g_sci0port     /* SCI0 is tty0 */
+#  ifdef CONFIG_SH1_SCI1
+#    define TTYS1_DEV     g_sci1port     /* SCI1 is tty1 */
+#  else
+#    undef TTYS1_DEV
+#  endif
+
+/* CONFIG_SCI1_SERIAL_CONSOLE (implies CONFIG_SH1_SCI1 also defined) */
+
+#elif defined(CONFIG_SCI1_SERIAL_CONSOLE)
+#  define CONSOLE_DEV     g_sci1port     /* SCI1 is console */
+#  define TTYS0_DEV       g_sci1port     /* SCI1 is tty0 */
+#  ifdef CONFIG_SH1_SCI0
+#    define TTYS1_DEV     g_sci0port     /* SCI0 is tty1 */
+#  else
+#    undef TTYS1_DEV                     /* No tty1 */
+#  endif
+
+/* No console, at least one of CONFIG_SH1_SCI0 and CONFIG_SH1_SCI1 defined */
+
+#elif defined(CONFIG_SH1_SCI0)
+#  undef  CONSOLE_DEV                    /* No console */
+#  define TTYS0_DEV       g_sci0port     /* SCI0 is tty0 */
+#  ifdef CONFIG_SH1_SCI1
+#    define TTYS1_DEV     g_sci1port     /* SCI1 is tty1 */
+#  else
+#    undef TTYS1_DEV                     /* No tty1 */
+#  endif
+
+/* Otherwise, there is no console and only CONFIG_SH1_SCI1 is defined */
+
+#else
+#  undef  CONSOLE_DEV                    /* No console */
+#  define TTYS0_DEV       g_sci1port     /* SCI1 is tty0 */
+#  undef TTYS1_DEV                       /* No tty1 */
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct up_dev_s
+{
+          uint32_t scibase;   /* Base address of SCI registers */
+          uint32_t baud;      /* Configured baud */
+ volatile  uint8_t scr;       /* Saved SCR value */
+ volatile  uint8_t ssr;       /* Saved SR value (only used during interrupt processing) */
+           uint8_t irq;       /* Base IRQ associated with this SCI */
+           uint8_t parity;    /* 0=none, 1=odd, 2=even */
+           uint8_t bits;      /* Number of bits (7 or 8) */
+              bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int  up_setup(struct uart_dev_s *dev);
+static void up_shutdown(struct uart_dev_s *dev);
+static int  up_attach(struct uart_dev_s *dev);
+static void up_detach(struct uart_dev_s *dev);
+static int  up_interrupt(int irq, void *context);
+static int  up_receive(struct uart_dev_s *dev, uint32_t *status);
+static void up_rxint(struct uart_dev_s *dev, bool enable);
+static bool up_rxavailable(struct uart_dev_s *dev);
+static void up_send(struct uart_dev_s *dev, int ch);
+static void up_txint(struct uart_dev_s *dev, bool enable);
+static bool up_txready(struct uart_dev_s *dev);
+
+/****************************************************************************
+ * Private Variables
+ ****************************************************************************/
+
+struct uart_ops_s g_sci_ops =
+{
+  .setup          = up_setup,
+  .shutdown       = up_shutdown,
+  .attach         = up_attach,
+  .detach         = up_detach,
+  .receive        = up_receive,
+  .rxint          = up_rxint,
+  .rxavailable    = up_rxavailable,
+  .send           = up_send,
+  .txint          = up_txint,
+  .txready        = up_txready,
+  .txempty        = up_txready,
+};
+
+/* I/O buffers */
+
+#ifdef CONFIG_SH1_SCI0
+static char g_sci0rxbuffer[CONFIG_SCI0_RXBUFSIZE];
+static char g_sci0txbuffer[CONFIG_SCI0_TXBUFSIZE];
+#endif
+#ifdef CONFIG_SH1_SCI1
+static char g_sci1rxbuffer[CONFIG_SCI1_RXBUFSIZE];
+static char g_sci1txbuffer[CONFIG_SCI1_TXBUFSIZE];
+#endif
+
+/* This describes the state of the SH1 SCI0 port. */
+
+#ifdef CONFIG_SH1_SCI0
+static struct up_dev_s g_sci0priv =
+{
+  .scibase        = SH1_SCI0_BASE,
+  .baud           = CONFIG_SCI0_BAUD,
+  .irq            = SH1_SCI0_IRQBASE,
+  .parity         = CONFIG_SCI0_PARITY,
+  .bits           = CONFIG_SCI0_BITS,
+  .stopbits2      = CONFIG_SCI0_2STOP,
+};
+
+static uart_dev_t g_sci0port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_SCI0_RXBUFSIZE,
+    .buffer = g_sci0rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_SCI0_TXBUFSIZE,
+    .buffer = g_sci0txbuffer,
+  },
+  .ops      = &g_sci_ops,
+  .priv     = &g_sci0priv,
+};
+#endif
+
+/* This describes the state of the SH1 SCI1 port. */
+
+#ifdef CONFIG_SH1_SCI1
+static struct up_dev_s g_sci1priv =
+{
+  .scibase        = SH1_SCI1_BASE,
+  .baud           = CONFIG_SCI1_BAUD,
+  .irq            = SH1_SCI1_IRQBASE,
+  .parity         = CONFIG_SCI1_PARITY,
+  .bits           = CONFIG_SCI1_BITS,
+  .stopbits2      = CONFIG_SCI1_2STOP,
+};
+
+static uart_dev_t g_sci1port =
+{
+  .recv     =
+  {
+    .size   = CONFIG_SCI1_RXBUFSIZE,
+    .buffer = g_sci1rxbuffer,
+  },
+  .xmit     =
+  {
+    .size   = CONFIG_SCI1_TXBUFSIZE,
+    .buffer = g_sci1txbuffer,
+   },
+  .ops      = &g_sci_ops,
+  .priv     = &g_sci1priv,
+};
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_serialin
+ ****************************************************************************/
+
+static inline uint8_t up_serialin(struct up_dev_s *priv, int offset)
+{
+  return getreg8(priv->scibase + offset);
+}
+
+/****************************************************************************
+ * Name: up_serialout
+ ****************************************************************************/
+
+static inline void up_serialout(struct up_dev_s *priv, int offset, uint8_t value)
+{
+  putreg8(value, priv->scibase + offset);
+}
+
+/****************************************************************************
+ * Name: up_disablesciint
+ ****************************************************************************/
+
+static inline void up_disablesciint(struct up_dev_s *priv, uint8_t *scr)
+{
+  /* Return a copy of the current scr settings */
+
+  if (scr)
+    {
+      *scr = priv->scr;
+    }
+
+  /* The disable all interrupts */
+
+  priv->scr &= ~SH1_SCISCR_ALLINTS;
+  up_serialout(priv, SH1_SCI_SCR_OFFSET, priv->scr);
+}
+
+/****************************************************************************
+ * Name: up_restoresciint
+ ****************************************************************************/
+
+static inline void up_restoresciint(struct up_dev_s *priv, uint8_t scr)
+{
+  /* Set the interrupt bits in the scr value */
+
+  priv->scr  &= ~SH1_SCISCR_ALLINTS;
+  priv->scr |= (scr & SH1_SCISCR_ALLINTS);
+  up_serialout(priv, SH1_SCI_SCR_OFFSET, priv->scr);
+}
+
+/****************************************************************************
+ * Name: up_waittxready
+ ****************************************************************************/
+
+#ifdef HAVE_CONSOLE
+static inline void up_waittxready(struct up_dev_s *priv)
+{
+  int tmp;
+
+  /* Limit how long we will wait for the TDR empty condition */
+
+  for (tmp = 1000 ; tmp > 0 ; tmp--)
+    {
+      /* Check if the TDR is empty.  The TDR becomes empty when:  (1) the
+       * the chip is reset or enters standby mode, (2) the TE bit in the SCR
+       * is cleared, or (3) the current TDR contents are loaded in the TSR so
+       * that new data can be written in the TDR.
+       */
+
+      if ((up_serialin(priv, SH1_SCI_SSR_OFFSET) & SH1_SCISSR_TDRE) != 0)
+        {
+          /* The TDR is empty... return */
+          break;
+        }
+    }
+}
+#endif
+
+/****************************************************************************
+ * Name: up_setbrr
+ *
+ * Description:
+ *   Calculate the correct value for the BRR given the configured frequency
+ *   and the desired BAUD settings.
+ *
+ ****************************************************************************/
+
+static inline void up_setbrr(struct up_dev_s *priv, unsigned int baud)
+{
+  /* The calculation of the BRR to achieve the desired BAUD is given by the
+   * following formula:
+   *
+   *   brr = (f/(64*2**(2n-1)*b))-1
+   *
+   * Where:
+   *
+   *   b = bit rate
+   *   f = frequency (Hz)
+   *   n = divider setting (0, 1, 2, 3)
+   *
+   * For n == 0 and with rounding this becomes:
+   *
+   *   brr = ((((f+16)/32) +(b/2)) / b) - 1
+   *
+   * For example, if the processor is clocked at 10 MHz and 9600 is the
+   * desired BAUD:
+   *
+   *   brr = ((10,000,016/32) + 4800) / 9600 -1
+   *       = 32
+   */
+
+  uint32_t brr = ((((SH1_CLOCK + 16) / 32) + (baud >> 1)) / baud) - 1;
+  up_serialout(priv, SH1_SCI_BRR_OFFSET, (uint16_t)brr);
+}
+
+/****************************************************************************
+ * Name: up_setup
+ *
+ * Description:
+ *   Configure the SCI baud, bits, parity, fifos, etc. This
+ *   method is called the first time that the serial port is
+ *   opened.
+ *
+ ****************************************************************************/
+
+static int up_setup(struct uart_dev_s *dev)
+{
+#ifndef CONFIG_SUPPRESS_SCI_CONFIG
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  uint8_t smr;
+
+  /* Disable the transmitter and receiver */
+
+  priv->scr  = up_serialin(priv, SH1_SCI_SCR_OFFSET);
+  priv->scr &= ~(SH1_SCISCR_TE | SH1_SCISCR_RE);
+  up_serialout(priv, SH1_SCI_SCR_OFFSET, priv->scr);
+
+  /* Set communication to be asynchronous with the configured number of data
+   * bits, parity, and stop bits.  Use the internal clock (undivided)
+   */
+
+  smr = 0;
+  if (priv->bits == 7)
+    {
+      smr |= SH1_SCISMR_CHR;
+    }
+
+  if (priv->parity == 1)
+    {
+      smr |= (SH1_SCISMR_PE|SH1_SCISMR_OE);
+    }
+  else if (priv->parity == 2)
+    {
+      smr |= SH1_SCISMR_PE;
+    }
+
+  if (priv->stopbits2)
+    {
+      smr |= SH1_SCISMR_STOP;
+    }
+
+  up_serialout(priv, SH1_SCI_SMR_OFFSET, smr);
+
+  /* Set the baud based on the configured console baud and configured
+   * system clock.
+   */
+
+  up_setbrr(priv, priv->baud);
+
+  /* Select the internal clock source as input */
+
+  priv->scr &= ~SH1_SCISCR_CKEMASK;
+  up_serialout(priv, SH1_SCI_SCR_OFFSET, priv->scr);
+
+  /* Wait a bit for the clocking to settle */
+
+  up_udelay(100);
+
+  /* Then enable the transmitter and reciever */
+
+  priv->scr |= (SH1_SCISCR_TE | SH1_SCISCR_RE);
+  up_serialout(priv, SH1_SCI_SCR_OFFSET, priv->scr);
+#endif
+  return OK;
+}
+
+/****************************************************************************
+ * Name: up_shutdown
+ *
+ * Description:
+ *   Disable the SCI.  This method is called when the serial port is closed
+ *
+ ****************************************************************************/
+
+static void up_shutdown(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  up_disablesciint(priv, NULL);
+}
+
+/****************************************************************************
+ * Name: up_attach
+ *
+ * Description:
+ *   Configure the SCI to operation in interrupt driven mode.  This method is
+ *   called when the serial port is opened.  Normally, this is just after the
+ *   the setup() method is called, however, the serial console may operate in
+ *   a non-interrupt driven mode during the boot phase.
+ *
+ *   RX and TX interrupts are not enabled when by the attach method (unless the
+ *   hardware supports multiple levels of interrupt enabling).  The RX and TX
+ *   interrupts are not enabled until the txint() and rxint() methods are called.
+ *
+ ****************************************************************************/
+
+static int up_attach(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  int ret;
+
+  /* Attach the RDR full IRQ (RXI) that is enabled by the RIE SCR bit */
+
+  ret = irq_attach(priv->irq + SH1_RXI_IRQ_OFFSET, up_interrupt);
+  if (ret == OK)
+    {
+      /* The RIE interrupt enable also enables the receive error interrupt (ERI) */
+
+      ret = irq_attach(priv->irq + SH1_ERI_IRQ_OFFSET, up_interrupt);
+      if (ret == OK)
+        {
+          /* Attach the TDR empty IRQ (TXI) enabled by the TIE SCR bit */
+
+          ret = irq_attach(priv->irq + SH1_TXI_IRQ_OFFSET, up_interrupt);
+          if (ret == OK)
+            {
+              /* All SCI0 interrupts share the same prioritization */
+
+              up_prioritize_irq(priv->irq, 7);  /* Set SCI priority midway */
+
+              /* Return OK on success */
+
+              return OK;
+            }
+
+          /* Detach the ERI interrupt on failure */
+
+          (void)irq_detach(priv->irq + SH1_ERI_IRQ_OFFSET);
+        }
+
+      /* Detach the RXI interrupt on failure */
+
+      (void)irq_detach(priv->irq + SH1_RXI_IRQ_OFFSET);
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: up_detach
+ *
+ * Description:
+ *   Detach SCI interrupts.  This method is called when the serial port is
+ *   closed normally just before the shutdown method is called.  The exception is
+ *   the serial console which is never shutdown.
+ *
+ ****************************************************************************/
+
+static void up_detach(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+
+  /* Disable all SCI interrupts */
+
+  up_disablesciint(priv, NULL);
+
+  /* Detach the SCI interrupts */
+
+  (void)irq_detach(priv->irq + SH1_RXI_IRQ_OFFSET);
+  (void)irq_detach(priv->irq + SH1_ERI_IRQ_OFFSET);
+  (void)irq_detach(priv->irq + SH1_RXI_IRQ_OFFSET);
+
+  /* Set the interrupt priority to zero (masking all SCI interrupts).  NOTE
+   * that all SCI0 interrupts share the same prioritization.
+   */
+
+  up_prioritize_irq(priv->irq, 0);
+}
+
+/****************************************************************************
+ * Name: up_interrupt
+ *
+ * Description:
+ *   This is the SCI interrupt handler.  It will be invoked
+ *   when an interrupt received on the 'irq'  It should call
+ *   uart_transmitchars or uart_receivechar to perform the
+ *   appropriate data transfers.  The interrupt handling logic\
+ *   must be able to map the 'irq' number into the approprite
+ *   up_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int up_interrupt(int irq, void *context)
+{
+  struct uart_dev_s *dev = NULL;
+  struct up_dev_s   *priv;
+
+#ifdef CONFIG_SH1_SCI0
+  if ((irq >= g_sci0priv.irq) && 
+      (irq <= g_sci0priv.irq +  SH1_SCI_NIRQS))
+    {
+      dev = &g_sci0port;
+    }
+  else
+#endif
+#ifdef CONFIG_SH1_SCI1
+  if ((irq >= g_sci1priv.irq) && 
+      (irq <= g_sci1priv.irq +  SH1_SCI_NIRQS))
+    {
+      dev = &g_sci1port;
+    }
+  else
+#endif
+    {
+      PANIC(OSERR_INTERNAL);
+    }
+  priv = (struct up_dev_s*)dev->priv;
+
+  /* Get the current SCI status  */
+
+  priv->ssr = up_serialin(priv, SH1_SCI_SSR_OFFSET);
+
+  /* Handle receive-related events with RIE is enabled.  RIE is enabled at
+   * times that driver is open EXCEPT when the driver is actively copying
+   * data from the circular buffer.  In that case, the read events must
+   * pend until RIE is set
+   */
+
+  if ((priv->scr & SH1_SCISCR_RIE) != 0)
+    {
+      /* Handle incoming, receive bytes (RDRF: Receive Data Register Full) */
+
+      if ((priv->ssr & SH1_SCISSR_RDRF) != 0)
+        {
+           /* Rx data register not empty ... process incoming bytes */
+
+           uart_recvchars(dev);
+        }
+
+      /* Clear all read related events (probably already done in up_receive)) */
+
+      priv->ssr &= ~(SH1_SCISSR_RDRF|SH1_SCISSR_ORER|SH1_SCISSR_FER|SH1_SCISSR_PER);
+    }
+
+  /* Handle outgoing, transmit bytes (TDRE: Transmit Data Register Empty)
+   * when TIE is enabled.  TIE is only enabled when the driver is waiting with
+   * buffered data.  Since TDRE is usually true, 
+   */
+
+  if ((priv->ssr & SH1_SCISSR_TDRE) != 0 && (priv->scr & SH1_SCISCR_TIE) != 0)
+    {
+       /* Tx data register empty ... process outgoing bytes */
+
+       uart_xmitchars(dev);
+
+       /* Clear the TDR empty flag (Possibly done in up_send, will have not
+        * effect if the TDR is still empty)
+        */
+
+      priv->ssr &= ~SH1_SCISSR_TDRE;
+    }
+
+  /* Clear all (clear-able) status flags.  Note that that SH-1 requires
+   * that you read the bit in the "1" then write "0" to the bit in order
+   * to clear it.  Any bits in the SSR that transitioned from 0->1 after
+   * we read the SR will not be effected by the following:
+   */
+
+  up_serialout(priv, SH1_SCI_SSR_OFFSET, priv->ssr);
+  return OK;
+}
+
+/****************************************************************************
+ * Name: up_receive
+ *
+ * Description:
+ *   Called (usually) from the interrupt level to receive one
+ *   character from the SCI.  Error bits associated with the
+ *   receipt are provided in the return 'status'.
+ *
+ ****************************************************************************/
+
+static int up_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  uint8_t rdr;
+  uint8_t ssr;
+
+  /* Read the character from the RDR port */
+
+  rdr  = up_serialin(priv, SH1_SCI_RDR_OFFSET);
+
+  /* Clear all read related status in  real ssr (so that when when rxavailable
+   * is called again, it will return false.
+   */
+
+  ssr = up_serialin(priv, SH1_SCI_SSR_OFFSET);
+  ssr &= ~(SH1_SCISSR_RDRF|SH1_SCISSR_ORER|SH1_SCISSR_FER|SH1_SCISSR_PER);
+  up_serialout(priv, SH1_SCI_SSR_OFFSET, ssr);
+
+  /* For status, return the SSR at the time that the interrupt was received */
+
+  *status = (uint32_t)priv->ssr << 8 | rdr;
+
+  /* Return the received character */
+
+  return (int)rdr;
+}
+
+/****************************************************************************
+ * Name: up_rxint
+ *
+ * Description:
+ *   Call to enable or disable RX interrupts
+ *
+ ****************************************************************************/
+
+static void up_rxint(struct uart_dev_s *dev, bool enable)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  irqstate_t flags;
+
+  /* Disable interrupts to prevent asynchronous accesses */
+
+  flags = irqsave();
+
+  /* Are we enabling or disabling? */
+
+  if (enable)
+    {
+      /* Enable the RDR full interrupt */
+
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+      priv->scr |= SH1_SCISCR_RIE;
+#endif
+    }
+  else
+    {
+      /* Disable the RDR full interrupt */
+
+      priv->scr &= ~SH1_SCISCR_RIE;
+    }
+
+  /* Write the modified SCR value to hardware */
+
+  up_serialout(priv, SH1_SCI_SCR_OFFSET, priv->scr);
+  irqrestore(flags);
+}
+
+/****************************************************************************
+ * Name: up_rxavailable
+ *
+ * Description:
+ *   Return true if the RDR is not empty
+ *
+ ****************************************************************************/
+
+static bool up_rxavailable(struct uart_dev_s *dev)
+{
+  /* Return true if the RDR full bit is set in the SSR */
+
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return ((up_serialin(priv, SH1_SCI_SSR_OFFSET) & SH1_SCISSR_RDRF) != 0);
+}
+
+/****************************************************************************
+ * Name: up_send
+ *
+ * Description:
+ *   This method will send one byte on the SCI
+ *
+ ****************************************************************************/
+
+static void up_send(struct uart_dev_s *dev, int ch)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  uint8_t ssr;
+
+  /* Write the data to the TDR */
+
+  up_serialout(priv, SH1_SCI_TDR_OFFSET, (uint8_t)ch);
+
+  /* Clear the TDRE bit in the SSR */
+
+  ssr  = up_serialin(priv, SH1_SCI_SSR_OFFSET);
+  ssr &= ~SH1_SCISSR_TDRE;
+  up_serialout(priv, SH1_SCI_SSR_OFFSET, ssr);
+}
+
+/****************************************************************************
+ * Name: up_txint
+ *
+ * Description:
+ *   Call to enable or disable TX interrupts
+ *
+ ****************************************************************************/
+
+static void up_txint(struct uart_dev_s *dev, bool enable)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  irqstate_t flags;
+
+  /* Disable interrupts to prevent asynchronous accesses */
+
+  flags = irqsave();
+
+  /* Are we enabling or disabling? */
+
+  if (enable)
+    {
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+      /* Enable the TDR empty interrupt */
+
+      priv->scr |= SH1_SCISCR_TIE;
+
+      /* If the TDR is already empty, then don't wait for the interrupt */
+
+#if 1
+      if (up_txready(dev))
+        {
+          /* Tx data register empty ... process outgoing bytes.  Note:
+           * this could call up_txint to be called recursively.  However,
+           * in this event, priv->scr should hold the correct value upon
+           * return from uuart_xmitchars().
+           */
+
+          uart_xmitchars(dev);
+        }
+#endif
+#endif
+    }
+  else
+    {
+      /* Disable the TDR empty interrupt */
+
+      priv->scr &= ~SH1_SCISCR_TIE;
+    }
+
+  /* Write the modified SCR value to hardware */
+
+  up_serialout(priv, SH1_SCI_SCR_OFFSET, priv->scr);
+  irqrestore(flags);
+}
+
+/****************************************************************************
+ * Name: up_txready
+ *
+ * Description:
+ *   Return true if the TDR is empty
+ *
+ ****************************************************************************/
+
+static bool up_txready(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+  return (up_serialin(priv, SH1_SCI_SSR_OFFSET) & SH1_SCISSR_TDRE) != 0;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_earlyconsoleinit
+ *
+ * Description:
+ *   Performs the low level SCI initialization early in 
+ *   debug so that the serial console will be available
+ *   during bootup.  This must be called before up_consoleinit.
+ *
+ ****************************************************************************/
+
+void up_earlyconsoleinit(void)
+{
+  /* NOTE:  All GPIO configuration for the SCIs was performed in
+   * up_lowsetup
+   */
+
+  /* Disable all SCIs */
+
+#ifdef TTYS0_DEV
+  up_disablesciint(TTYS0_DEV.priv, NULL);
+#ifdef TTYS1_DEV
+  up_disablesciint(TTYS1_DEV.priv, NULL);
+#endif
+#endif
+
+  /* Configuration whichever one is the console */
+
+#ifdef HAVE_CONSOLE
+  CONSOLE_DEV.isconsole = true;
+  up_setup(&CONSOLE_DEV);
+#endif
+}
+
+/****************************************************************************
+ * Name: up_consoleinit
+ *
+ * Description:
+ *   Register serial console and serial ports.  This assumes
+ *   that up_earlyconsoleinit was called previously.
+ *
+ ****************************************************************************/
+
+void up_consoleinit(void)
+{
+  /* Register the console */
+
+#ifdef HAVE_CONSOLE
+  (void)uart_register("/dev/console", &CONSOLE_DEV);
+#endif
+
+  /* Register all SCIs */
+
+#ifdef TTYS0_DEV
+  (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
+#ifdef TTYS1_DEV
+  (void)uart_register("/dev/ttyS1", &TTYS1_DEV);
+#endif
+#endif
+}
+
+/****************************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ *   Provide priority, low-level access to support OS debug  writes
+ *
+ ****************************************************************************/
+
+int up_putc(int ch)
+{
+#ifdef HAVE_CONSOLE
+  struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv;
+  uint8_t  scr;
+
+  up_disablesciint(priv, &scr);
+
+  /* Check for LF */
+
+  if (ch == '\n')
+    {
+      /* Add CR */
+
+      up_waittxready(priv);
+      up_serialout(priv, SH1_SCI_TDR_OFFSET, '\r');
+    }
+
+  up_waittxready(priv);
+  up_serialout(priv, SH1_SCI_TDR_OFFSET, (uint8_t)ch);
+
+  up_waittxready(priv);
+  up_restoresciint(priv, scr);
+#endif
+  return ch;
+}
+
+#else /* USE_SERIALDRIVER */
+
+/****************************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ *   Provide priority, low-level access to support OS debug writes
+ *
+ ****************************************************************************/
+
+int up_putc(int ch)
+{
+#ifdef HAVE_CONSOLE
+  /* Check for LF */
+
+  if (ch == '\n')
+    {
+      /* Add CR */
+
+      up_lowputc('\r');
+    }
+
+  up_lowputc(ch);
+#endif
+  return ch;
+}
+
+#endif /* USE_SERIALDRIVER */

nuttx/arch/sh/src/sh1/sh1_sigdeliver.c

@@ -0,0 +1,141 @@
+/****************************************************************************
+ * common/up_sigdeliver.c
+ *
+ *   Copyright (C) 2008-2010 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <sched.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+
+#include "os_internal.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+#ifndef CONFIG_DISABLE_SIGNALS
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_sigdeliver
+ *
+ * Description:
+ *   This is the a signal handling trampoline.  When a signal action was
+ *   posted.  The task context was mucked with and forced to branch to this
+ *   location with interrupts disabled.
+ *
+ ****************************************************************************/
+
+void up_sigdeliver(void)
+{
+#ifndef CONFIG_DISABLE_SIGNALS
+  _TCB  *rtcb = (_TCB*)g_readytorun.head;
+  uint32_t regs[XCPTCONTEXT_REGS];
+  sig_deliver_t sigdeliver;
+
+  /* Save the errno.  This must be preserved throughout the signal handling
+   * so that the user code final gets the correct errno value (probably
+   * EINTR).
+   */
+
+  int saved_errno = rtcb->pterrno;
+
+  up_ledon(LED_SIGNAL);
+
+  sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
+        rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
+  ASSERT(rtcb->xcp.sigdeliver != NULL);
+
+  /* Save the real return state on the stack. */
+
+  up_copystate(regs, rtcb->xcp.regs);
+  regs[REG_PC] = rtcb->xcp.saved_pc;
+  regs[REG_SR] = rtcb->xcp.saved_sr;
+
+  /* Get a local copy of the sigdeliver function pointer.  We do this so
+   * that we can nullify the sigdeliver function pointer in the TCB and
+   * accept more signal deliveries while processing the current pending
+   * signals.
+   */
+
+  sigdeliver           = rtcb->xcp.sigdeliver;
+  rtcb->xcp.sigdeliver = NULL;
+
+  /* Then restore the task interrupt state. */
+
+  irqrestore(regs[REG_SR] & 0x000000f0);
+
+  /* Deliver the signals */
+
+  sigdeliver(rtcb);
+
+  /* Output any debug messages BEFORE restoring errno (because they may
+   * alter errno), then disable interrupts again and restore the original
+   * errno that is needed by the user logic (it is probably EINTR).
+   */
+
+  sdbg("Resuming\n");
+  (void)irqsave();
+  rtcb->pterrno = saved_errno;
+
+  /* Then restore the correct state for this thread of execution. */
+
+  up_ledoff(LED_SIGNAL);
+  up_fullcontextrestore(regs);
+#endif
+}
+
+#endif /* !CONFIG_DISABLE_SIGNALS */
+

nuttx/arch/sh/src/sh1/sh1_timerisr.c

@@ -0,0 +1,205 @@
+/****************************************************************************
+ * arch/sh/src/sh1/sh1_timerisr.c
+ *
+ *   Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <time.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <arch/board/board.h>
+
+#include "clock_internal.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/* The desired timer interrupt frequency is provided by the definition
+ * CLK_TCK (see include/time.h).  CLK_TCK defines the desired number of
+ * system clock ticks per second.  That value is a user configurable setting
+ * that defaults to 100 (100 ticks per second = 10 MS interval).
+ *
+ * ITU1 operates in periodic timer mode.  TCNT counts up until it matches
+ * the value of GRA0, then an interrupt is generated.  Two values must be
+ * computed:
+ *
+ * (1) The divider that determines the rate at which TCNT increments, and
+ * (2) The value of GRA0 that cause the interrupt to occur.
+ *
+ * These must be selected so that the frequency of interrupt generation is
+ * CLK_TCK.  Ideally, we would like to use the full range of GRA0 for better
+ * timing acuracy:
+ */
+
+#define DESIRED_GRA0     65535
+
+/* The ideal divider would be one that generates exactly 65535 ticks in
+ * 1/CLK_TCK seconds.  For example, if SH1_CLOCK is 10MHz and CLK_TCK is
+ * 100, then the ideal divider must be less greater than or equal to:
+ *
+ *   (10,000,000 / CLK_TCK) / 65535 = 1.525
+ *
+ * The actual selected divider would then have to be 2, resulting in a
+ * counting rate of 5,000,0000 and a GRA0 setting of 50,000.
+ */
+
+#define SYSCLKS_PER_TICK ((SH1_CLOCK + (CLK_TCK-1))/ CLK_TCK)
+#define DESIRED_DIVIDER  ((SYSCLKS_PER_TICK + (DESIRED_GRA0-1))/ DESIRED_GRA0)
+
+#if (DESIRED_DIVIDER <= 1)
+#  define SYSCLK_DIVIDER 1
+#  define SH1_ITUTCR_DIV SH1_ITUTCR_DIV1
+#elif (DESIRED_DIVIDER <= 2)
+#  define SYSCLK_DIVIDER 2
+#  define SH1_ITUTCR_DIV SH1_ITUTCR_DIV2
+#elif (DESIRED_DIVIDER <= 4)
+#  define SYSCLK_DIVIDER 4
+#  define SH1_ITUTCR_DIV SH1_ITUTCR_DIV4
+#elif (DESIRED_DIVIDER <= 8)
+#  define SYSCLK_DIVIDER 8
+#  define SH1_ITUTCR_DIV SH1_ITUTCR_DIV8
+#else
+#  error "No divider is available for this system clock"
+#endif
+
+/* The TCNT will then increment at the following rate: */
+
+#define TCNT_CLOCK       ((SH1_CLOCK + (SYSCLK_DIVIDER/2))/ SYSCLK_DIVIDER)
+
+/* And the value of GRA0 that generates at CLK_TCK ticks per second is: */
+
+#define TCNT_PER_TICK    ((TCNT_CLOCK + (CLK_TCK-1))/ CLK_TCK)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Global Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function:  up_timerisr
+ *
+ * Description:
+ *   The timer ISR will perform a variety of services for various portions
+ *   of the systems.
+ *
+ ****************************************************************************/
+
+int up_timerisr(int irq, uint32_t *regs)
+{
+   uint8_t reg8;
+
+   /* Process timer interrupt */
+
+   sched_process_timer();
+
+   /* Clear ITU0 interrupt status flag */
+
+   reg8 = getreg8(SH1_ITU0_TSR);
+   reg8 &= ~SH1_ITUTSR_IMFA;
+   putreg8(reg8, SH1_ITU0_TSR);
+
+   return 0;
+}
+
+/****************************************************************************
+ * Function:  up_timerinit
+ *
+ * Description:
+ *   This function is called during start-up to initialize
+ *   the timer interrupt.
+ *
+ ****************************************************************************/
+
+void up_timerinit(void)
+{
+  uint8_t reg8;
+
+  /* Clear timer counter 0 */
+
+  putreg16(0, SH1_ITU0_TCNT);
+
+  /* Set the GRA0 match value.  The interrupt will be generated when TNCT
+   * increments to this value
+   */
+
+  putreg16(TCNT_PER_TICK, SH1_ITU0_GRA);
+
+  /* Set the timer control register.  TCNT cleared by FRA */
+
+  putreg8(SH1_ITUTCR_CGRA|SH1_ITUTCR_DIV, SH1_ITU0_TCR);
+
+  /* Set the timer I/O control register */
+
+  putreg8(0, SH1_ITU0_TIOR); /* GRA used but with no inputs/output pins */
+
+  /* Make sure that all status flags are clear */
+
+  putreg8(0, SH1_ITU0_TSR);
+
+  /* Attach the IMIA0 IRQ */
+
+  irq_attach(SH1_SYSTIMER_IRQ, (xcpt_t)up_timerisr);
+
+  /* Enable interrupts on GRA compare match */
+
+  putreg8(SH1_ITUTIER_IMIEA, SH1_ITU0_TIER);
+
+  /* Set the interrupt priority */
+
+  up_prioritize_irq(SH1_SYSTIMER_IRQ, 7);  /* Set ITU priority midway */
+
+  /* Start the timer */
+
+  reg8  = getreg8(SH1_ITU_TSTR);
+  reg8 |= SH1_ITUTSTR_STR0;     /* Enable TCNT0 */
+  putreg8(reg8, SH1_ITU_TSTR);  /* TCNT0 is counting */
+}

nuttx/arch/sh/src/sh1/sh1_vector.S

@@ -0,0 +1,525 @@
+/*****************************************************************************
+ * arch/sh/src/sh1/sh1_vector.S
+ *
+ *   Copyright (C) 2008 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/*****************************************************************************
+ * Included Files
+ *****************************************************************************/
+
+#include <nuttx/config.h>	/* NuttX configuration settings */
+#include <arch/board/board.h>	/* Board-specific settings */
+#include <arch/irq.h>		/* IRQ definitons */
+
+#include "chip.h"		/* Chip-specific settings */
+#include "up_internal.h"
+
+/*****************************************************************************
+ * Definitions
+ *****************************************************************************/
+
+/*****************************************************************************
+ * External references
+ *****************************************************************************/
+
+/* Called functions */
+
+	.globl	_up_doirq		/* C interrupt processing logic */
+
+/*****************************************************************************
+ * Macros
+ *****************************************************************************/
+
+/************************************************************************************
+ * Macro: trampoline
+ *
+ * Description:
+ *   Enter on exception with:
+ *
+ *   SP -> PC
+ *         SR
+ *
+ *   Branch to up_vector with:
+ *
+ *   R4  : IRQ vector number
+ *   SP -> Saved R4
+ *         PC
+ *         SR
+ *
+ ************************************************************************************/
+
+	.macro	trampoline, irq, label
+	mov.l	r4, @-r15		/* Save the value of R4 on the stack */
+	mov.w	.L\label, r4		/* R4=IRQ number */
+	bra	_up_vector		/* Jump to the common vector handling logic */
+	nop
+.L\label:
+	.word	\irq
+	.endm
+
+/*****************************************************************************
+ * Text
+ *****************************************************************************/
+
+	.section	.reset
+
+/*****************************************************************************
+ * Name: _up_*_handler
+ *
+ * Description:
+ *   Trampoline entry points for each, individual IRQ
+ *
+ *  R4 :  Points to a the register save structure
+ *
+ *****************************************************************************/
+
+	.globl	_up_invalid_handler
+_up_invalid_handler:
+	trampoline NR_IRQS, 1
+
+#ifdef CONFIG_SH1_DMAC0
+	.globl	_up_dmac0_handler
+_up_dmac0_handler:
+	trampoline SH1_DEI0_IRQ, 2 /* DEI0 */
+#endif
+
+#ifdef CONFIG_SH1_DMAC1
+	.globl	_up_dmac1_handler
+_up_dmac1_handler:
+	trampoline SH1_DEI1_IRQ, 3 /* DEI1 */
+#endif
+
+#ifdef CONFIG_SH1_DMAC2
+	.globl	_up_dmac2_handler
+_up_dmac2_handler:
+	trampoline SH1_DEI2_IRQ, 4 /* DEI2 */
+#endif
+
+#ifdef CONFIG_SH1_DMAC3
+	.globl	_up_dmac3_handler
+_up_dmac4_handler:
+	trampoline SH1_DEI3_IRQ, 5 /* DEI3 */
+#endif
+
+	.globl	_up_imia0_handler
+	.globl	_up_imib0_handler
+	.globl	_up_ovi0_handler
+_up_imia0_handler:
+	trampoline SH1_IMIA0_IRQ, 6 /* IMIA0 */
+_up_imib0_handler:
+	trampoline SH1_IMIB0_IRQ, 7 /* IMIB0 */
+_up_ovi0_handler:
+	trampoline SH1_OVI0_IRQ, 8  /* OVI0 */
+
+#ifdef CONFIG_SH1_ITU1
+	.globl	_up_imia1_handler
+	.globl	_up_imib1_handler
+	.globl	_up_ovi1_handler
+_up_imia1_handler:
+	trampoline SH1_IMIA1_IRQ, 9 /* IMIA1 */
+_up_imib1_handler:
+	trampoline SH1_IMIB1_IRQ, 10 /* IMIB1 */
+_up_ovi1_handler:
+	trampoline SH1_OVI1_IRQ, 11  /* OVI1 */
+#endif
+
+#ifdef CONFIG_SH1_ITU2
+	.globl	_up_imia2_handler
+	.globl	_up_imib2_handler
+	.globl	_up_ovi2_handler
+_up_imia2_handler:
+	trampoline SH1_IMIA2_IRQ, 12 /* IMIA2 */
+_up_imib2_handler:
+	trampoline SH1_IMIB2_IRQ, 13 /* IMIB2 */
+_up_ovi2_handler:
+	trampoline SH1_OVI2_IRQ, 14  /* OVI2 */
+#endif
+
+#ifdef CONFIG_SH1_ITU3
+	.globl	_up_imia3_handler
+	.globl	_up_imib3_handler
+	.globl	_up_ovi3_handler
+_up_imia3_handler:
+	trampoline SH1_IMIA3_IRQ, 15 /* IMIA3 */
+_up_imib3_handler:
+	trampoline SH1_IMIB3_IRQ, 16 /* IMIB3 */
+_up_ovi3_handler:
+	trampoline SH1_OVI3_IRQ, 17  /* OVI3 */
+#endif
+
+#ifdef CONFIG_SH1_ITU4
+	.globl	_up_imia4_handler
+	.globl	_up_imib4_handler
+	.globl	_up_ovi4_handler
+_up_imia4_handler:
+	trampoline SH1_IMIA4_IRQ, 18 /* IMIA4 */
+_up_imib4_handler:
+	trampoline SH1_IMIB4_IRQ, 19 /* IMIB4 */
+_up_ovi4_handler:
+	trampoline SH1_OVI4_IRQ, 20  /* OVI4 */
+#endif
+
+#ifdef CONFIG_SH1_SCI0
+	.globl	_up_eri0_handler
+	.globl	_up_rxi0_handler
+	.globl	_up_txi0_handler
+	.globl	_up_tei0_handler
+_up_eri0_handler:
+	trampoline SH1_ERI0_IRQ, 21 /*  ERI0 */
+_up_rxi0_handler:
+	trampoline SH1_RXI0_IRQ, 22 /*  RxI0 */
+_up_txi0_handler:
+	trampoline SH1_TXI0_IRQ, 23 /*  TxI0 */
+_up_tei0_handler:
+	trampoline SH1_TEI0_IRQ, 24 /*  TEI0 */
+#endif
+
+#ifdef CONFIG_SH1_SCI1
+	.globl	_up_eri1_handler
+	.globl	_up_rxi1_handler
+	.globl	_up_txi1_handler
+	.globl	_up_tei1_handler
+_up_eri1_handler:
+	trampoline SH1_ERI1_IRQ, 25 /*  ERI1 */
+_up_rxi1_handler:
+	trampoline SH1_RXI1_IRQ, 26 /*  RxI1 */
+_up_txi1_handler:
+	trampoline SH1_TXI1_IRQ, 27 /*  TxI1 */
+_up_tei1_handler:
+	trampoline SH1_TEI1_IRQ, 28 /*  TEI1 */
+#endif
+
+#ifdef CONFIG_SH1_PCU
+	.globl	_up_pei_handler
+_up_pei_handler:
+	trampoline SH1_PEI_IRQ, 29 /* Parity control unit PEI */
+#endif
+
+#ifdef CONFIG_SH1_AD
+	.globl	_up_aditi_handler
+_up_aditi_handler:
+	trampoline SH1_ADITI_IRQ, 30 /* A/D ITI */
+#endif
+
+#ifdef CONFIG_SH1_WDT
+	.globl	_up_wdt_handler
+_up_wdt_handler:
+	trampoline SH1_WDTITI_IRQ, 31 /* WDT ITI */
+#endif
+
+#ifdef CONFIG_SH1_CMI
+	.globl	_up_cmi_handler
+_up_cmi_handler:
+	trampoline SH1_CMI_IRQ,32 /* REF CMI */
+#endif
+
+/*****************************************************************************
+ * Name: _up_vector
+ *
+ * Description:
+ *   Execption entry point.  Upon entry:
+ *
+ *  R4 :  Holds IRQ number
+ *  SP -> Saved R4		(REG_R4=19)	See irq.h
+ *        PC			(REG_PC=20)
+ *        SR			(REG_SR=21)
+ *
+ *****************************************************************************/
+
+	.global _up_vector
+	.type	_up_vector, #function
+
+_up_vector:
+	/* Save r0-r3, r5-r7 on the stack so that we have a registers to work with.
+	 * After this, the stack will look like:
+	 *
+	 *  SP -> macl		(REG_MACL=10)	See irq.h
+	 *        mach		(REG_MACH=11)
+	 *        r0		(REG_R0=12)
+	 *        r1		(REG_R1=13)
+	 *        r2		(REG_R2=14)
+	 *        r3		(REG_R3=15)
+	 *        r5		(REG_R5=16)
+	 *        r6		(REG_R6=17)
+	 *        r7		(REG_R7=18)
+	 *        R4		(REG_R4=19)
+	 *        ...
+	 */
+
+	mov.l	r7, @-r15
+	mov.l	r6, @-r15
+
+	stc     sr, r6			/* Mask all interrupts */
+	mov.l	.Lintmask, r7
+	or	r7, r6
+	ldc     r6, sr
+
+	mov.l	r5, @-r15
+	mov.l	r3, @-r15
+	mov.l	r2, @-r15
+	mov.l	r1, @-r15
+	mov.l	r0, @-r15
+
+	sts.l	mach, @-r15
+	sts.l	macl, @-r15
+
+	/* Then save the value of the SP *before* the interrupt ocurred
+	 *
+	 * SP -> SP		(REG_SP=9) See irq.h
+	 *       macl		(REG_MACL=10)
+	 *       mach		(REG_MACH=11)
+	 *       ...
+	 */
+
+	mov	r15, r5		/* R5 = current SP */
+	add	#(12*4), r5	/* Account for sr, pc, r0-r7, mach, and macl */
+	mov.l	r5, @-r15	/* Save the SP before the interrupt */
+	
+	/* Save the remaining registers on the stack:
+	 *
+	 * SP -> r8		(REG_R8=0) See irq.h
+	 *       r9		(REG_R9=1)
+	 *       r10		(REG_R10=2)
+	 *       r11		(REG_R11=3)
+	 *       r12		(REG_R12=4)
+	 *       r13		(REG_R13=5)
+	 *       r14		(REG_R14=6)
+	 *       pr		(REG_PR=7)
+	 *       gbr		(REG_GBR=8)
+	 *       SP		(REG_SP=9)
+	 *       ...
+	 */
+
+	stc.l	gbr, @-r15
+	sts.l	pr, @-r15
+
+	mov.l	r14, @-r15
+	mov.l	r13, @-r15
+	mov.l	r12, @-r15
+	mov.l	r11, @-r15
+	mov.l	r10, @-r15
+	mov.l	r9, @-r15
+	mov.l	r8, @-r15
+
+	/* Setup parameters: R4=IRQ number, R5=base of saved state */
+
+	mov	r15, r5
+
+	/* Switch to the interrupt stack */
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+	mov.l	.Lintstack, r15		/* SP = interrupt stack base */
+	mov.l	r5, @r15		/* Save the user stack pointer (pre-decremented) */
+
+	/* Dispatch the interrupt */
+
+        mov.l   .Ldoirq, r0
+        jsr     @r0
+        nop
+
+	/* Recover the user stack point */
+
+	mov.l	@15, r15
+#else
+	/* Dispatch the interrupt */
+
+        mov.l   .Ldoirq, r0
+        jsr     @r0
+        nop
+#endif
+	/* On return, R0 holds the address of the base of the XCPTCONTEXT
+	 * structure to use for the return -- may not be the same as the
+	 * one that we passed in via r5.  If the value is different, then
+	 * we cannot assume that the values lie on the stack and we will
+	 * need to execute some more complete logic.
+	 */
+
+	cmp/eq	r0, r15
+	bf	.Lcontextswitch
+	mov	r0, r15
+
+	/* Restore registers from the stack. NOTE: We coudl improve interrupt
+         * performance by skipping the restore of r8-r14.  These will not
+         * be modified by the called C code
+         */
+
+#if 1
+	/* Skip over static registers -- these will not be modified by the
+	 * called C code (r8-r14)
+         */
+
+	add	#(7*4), r15	/* 0-6: Skip over r8-r14 */
+#else
+	mov.l	@r15+, r8	/* 0-6: r8-r14 */
+	mov.l	@r15+, r9
+	mov.l	@r15+, r10
+	mov.l	@r15+, r11
+	mov.l	@r15+, r12
+	mov.l	@r15+, r13
+	mov.l	@r15+, r14
+#endif
+
+	lds.l	@r15+, pr	/* 7-8: pr and gbr */
+	ldc.l	@r15+, gbr
+
+	add	#4, r15		/* 9: Skip SP restore */
+
+	lds.l	@r15+, macl	/* 10-11: mach and macl */
+	lds.l	@r15+, mach
+
+	mov.l	@r15+, r0	/* 12-18: r0-r3, r5-r7 */
+	mov.l	@r15+, r1
+	mov.l	@r15+, r2
+	mov.l	@r15+, r3
+	mov.l	@r15+, r5
+	mov.l	@r15+, r6
+	mov.l	@r15+, r7
+
+	mov.l	@r15+, r4	/* 19: r4 */
+	rte			/* 20-21: pc and sr */
+	nop
+	.align	2
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+.Lintstack:
+	.long	_up_stackbase
+#endif
+.Ldoirq:
+        .long   _up_doirq
+        .size   _up_vector, .-_up_vector
+
+/*****************************************************************************
+ * Name: _up_fullcontextrestore
+ *
+ * Description:
+ *   restore context from a set of save registers
+ *
+ *  R4 :  Points to a the register save structure
+ *
+ *****************************************************************************/
+
+	.global _up_fullcontextrestore
+	.type	_up_fullcontextrestore, #function
+
+_up_fullcontextrestore:
+	/* Mask all interrupts */
+
+	stc     sr, r8
+	mov.l	.Lintmask, r9
+	or	r9, r8
+	ldc     r8, sr
+
+	/* Replace stack pointer with the context save */
+
+	mov	r4, r15
+
+	/* Restore registers from a context structure */
+
+.Lcontextswitch:
+	mov.l	@r15+, r8	/* 0-8: r8-r14, pr, and gbr */
+	mov.l	@r15+, r9
+	mov.l	@r15+, r10
+	mov.l	@r15+, r11
+	mov.l	@r15+, r12
+	mov.l	@r15+, r13
+	mov.l	@r15+, r14
+
+	lds.l	@r15+, pr
+	ldc.l	@r15+, gbr
+
+	mov.l	@r15+, r4	/* r4: Saved SP */
+
+	lds.l	@r15+, macl	/* 10-11: mach and macl */
+	lds.l	@r15+, mach
+
+	mov.l	@r15+, r0	/* 12-17: r0-r3, r5-r6 */
+	mov.l	@r15+, r1
+	mov.l	@r15+, r2
+	mov.l	@r15+, r3
+	mov.l	@r15+, r5
+	mov.l	@r15+, r6
+
+	/* Copy the remainder of the stack context to the target stack.
+	 * At this point r15 points to offset REG_R6.
+	 */
+
+	add	#-16, r4	/* R4 points to offset REG_R7 in the new stack */
+	mov.l	@r15+, r7	/* R7=Saved R7 value */
+	mov.l	r7, @r4		/* Save at offset REG_R7 in the new stack */
+	mov.l	@r15+, r7	/* R7=Save R4 value */
+	mov.l	r7, @(4,r4)	/* Save at offset REG_R4 in the new stack */
+	mov.l	@r15+, r7	/* R7=Save PC value */
+	mov.l	r7, @(8,r4)	/* Save at offset REG_PC in the new stack */
+	mov.l	@r15+, r7	/* R7=Save SR value */
+	mov.l	r7, @(12,r4)	/* Save at offset REG_SR in the new stack */
+
+	/* Set the new stack pointer */
+
+	mov	r4, r15
+
+	/* Then recover the final register values from the new stack */
+
+	mov.l	@r15+, r7
+	mov.l	@r15+, r4
+
+	/* And return from interrupt */
+
+	rte
+	nop
+	.align	2
+.Lintmask:
+	.long	0x000000f0
+	.size	_up_fullcontextrestore, .-_up_fullcontextrestore
+
+/************************************************************************************
+ *  Name: up_interruptstack/g_userstack
+ *
+ * Description:
+ *   Shouldn't happen
+ *
+ ************************************************************************************/
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+	.bss
+	.align	2
+	.globl	_g_userstack
+	.type	_g_userstack, object
+_up_interruptstack:
+	.skip	((CONFIG_ARCH_INTERRUPTSTACK & ~3) - 4)
+_g_userstack:
+_up_stackbase:
+	.skip	2
+	.size	_g_userstack, 4
+	.size	_up_interruptstack, (CONFIG_ARCH_INTERRUPTSTACK & ~3)
+#endif
+	.end
+