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patacongo
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@@ -0,0 +1,396 @@
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/****************************************************************************
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* arch/mips/include/pic32mx/cp0.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
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||||
*
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||||
****************************************************************************/
|
||||
|
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#ifndef __ARCH_MIPS_INCLUDE_PIC32MX_CP0_H
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#define __ARCH_MIPS_INCLUDE_PIC32MX_CP0_H
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/****************************************************************************
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||||
* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/mips32/cp0.h>
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|
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/****************************************************************************
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* Pre-Processor Definitions
|
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****************************************************************************/
|
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/* CP0 Register Addresses ***************************************************/
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|
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#ifdef __ASSEMBLY__
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# define PIC32MX_CP0_HWRENA $7,0 /* Enables access via RDHWR hardware registers */
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# define PIC32MX_CP0_BADVADDR $8,0 /* Address of most recent exception */
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# define PIC32MX_CP0_COUNT $9,0 /* Processor cycle count */
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# define PIC32MX_CP0_COMPARE $11,0 /* Timer interrupt control */
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# define PIC32MX_CP0_STATUS $12,0 /* Processor status and control */
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# define PIC32MX_CP0_INTCTL $12,1 /* Interrupt system status and control */
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# define PIC32MX_CP0_SRSCTL $12,2 /* Shadow register set status and control */
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# define PIC32MX_CP0_SRSMAP $12,3 /* Maps from vectored interrupt to a shadow set */
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# define PIC32MX_CP0_CAUSE $13,0 /* Cause of last general exception */
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# define PIC32MX_CP0_EPC $14,0 /* Program counter at last exception */
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# define PIC32MX_CP0_PRID $15,0 /* Processor identification and revision */
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# define PIC32MX_CP0_EBASE $15,1 /* Exception vector base register */
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# define PIC32MX_CP0_CONFIG $16,0 /* Configuration register */
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# define PIC32MX_CP0_CONFIG1 $16,1 /* Configuration register 1 */
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# define PIC32MX_CP0_CONFIG2 $16,2 /* Configuration register 3 */
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# define PIC32MX_CP0_CONFIG3 $16,3 /* Configuration register 3 */
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# define PIC32MX_CP0_DEBUG $23,3 /* Debug control and exception status */
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# define PIC32MX_CP0_DEPC $24,3 /* Program counter at last debug exception */
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# define PIC32MX_CP0_ERREPC $30,3 /* Program counter at last error */
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# define PIC32MX_CP0_DESAVE $31,3 /* Debug handler scratchpad register */
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#endif
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/* CP0 Registers ************************************************************/
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/* Register Number: 0-6: Reserved
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* Compliance Level: Required for TLB-based MMU; Optional otherwise.
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*/
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/* Register Number: 7 Sel: 0 Name: HWREna
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* Function: Enables access via the RDHWR instruction to selected hardware
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* registers in non-privileged mode.
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* Compliance Level: (Reserved for future extensions)
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*/
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#define CP0_HWRENA_SHIFT (0) /* Bits 0-3: Enable access to a hardware resource */
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#define CP0_HWRENA_MASK (15 << CP0_HWRENA_SHIFT)
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# define CP0_HWRENA_BIT0 (1 << CP0_HWRENA_SHIFT)
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# define CP0_HWRENA_BIT1 (2 << CP0_HWRENA_SHIFT)
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# define CP0_HWRENA_BIT2 (4 << CP0_HWRENA_SHIFT)
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# define CP0_HWRENA_BIT3 (8 << CP0_HWRENA_SHIFT)
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/* Register Number: 8 Sel: 0 Name: BadVAddr
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* Function: Reports the address for the most recent address-related
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* exception
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* Compliance Level: Required.
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*
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* See arch/mips/include/mips32/cp0.h
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*
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* Register Number: 9 Sel: 0 Name: Count
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* Function: Processor cycle count
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* Compliance Level: Required.
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*
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* See arch/mips/include/mips32/cp0.h
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*
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* Register Number: 10 Reserved.
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* Compliance Level: Required for TLB-based MMU; Optional otherwise.
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*
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* Register Number: 11 Sel: 0 Name: Compare
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* Function: Timer interrupt control
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* Compliance Level: Required.
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*
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* See arch/mips/include/mips32/cp0.h
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*/
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/* Register Number: 12 Sel: 0 Name: Status
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* Function: Processor status and control
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* Compliance Level: Required.
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*
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* See arch/mips/include/mips32/cp0.h
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* NOTES:
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* 1. The following are reserved bits in the PIC32:
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* CP0_STATUS_UX Bit 5: Enables 64-bit user address space (Not MIPS32)
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* CP0_STATUS_SX Bit 6: Enables 64-bit supervisor address space (Not MIPS32)
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* CP0_STATUS_KX Bit 7: Enables 64-bit kernel address space (Not MIPS32)
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* CP0_STATUS_IMPL Bits 16-17: Implementation dependent
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* CP0_STATUS_TS Bit 21: TLB detected match on multiple entries
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* CP0_STATUS_PX Bit 23: Enables 64-bit operations (Not MIPS32)
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* CP0_STATUS_MX Bit 24: Enables MDMX™ (Not MIPS32)
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*/
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#undef CP0_STATUS_UX
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#undef CP0_STATUS_SX
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#undef CP0_STATUS_KX
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#undef CP0_STATUS_IMPL
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#undef CP0_STATUS_IMPL_SHIFT
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#undef CP0_STATUS_IMPL_MASK
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#undef CP0_STATUS_TS
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#undef CP0_STATUS_PX
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#undef CP0_STATUS_MX
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/* 2. The following field is of a different width. Apparently, it
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* excludes the software interrupt bits.
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*
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* CP0_STATUS_IM Bits 8-15: Interrupt Mask
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* Vs.
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* CP0_STATUS_IPL Bits 10-15: Interrupt priority level
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* Bitss 8-9 reserved
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*/
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#define CP0_STATUS_IPL_SHIFT (10) /* Bits 10-15: Interrupt priority level */
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#define CP0_STATUS_IPL_MASK (0x3f << CP0_STATUS_IPL_SHIFT)
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||||
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/* 3. Supervisor mode not supported
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* CP0_STATUS_KSU Bits 3-4: Operating mode (with supervisor mode)
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*/
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#undef CP0_STATUS_KSU_SHIFT
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#undef CP0_STATUS_KSU_MASK
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#undef CP0_STATUS_KSU_KERNEL
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#undef CP0_STATUS_KSU_SUPER
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#undef CP0_STATUS_KSU_USER
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/* Register Number: 12 Sel: 1 Name: IntCtl */
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#define CP0_INTCTL_VS_SHIFT (5) /* Bits 5-9: Vector spacing bits */
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#define CP0_INTCTL_VS_MASK (0x1f << CP0_INTCTL_VS_SHIFT)
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# define CP0_INTCTL_VS_0BYTES (0x00 << CP0_INTCTL_VS_SHIFT)
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# define CP0_INTCTL_VS_32BYTES (0x01 << CP0_INTCTL_VS_SHIFT)
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# define CP0_INTCTL_VS_64BYTES (0x02 << CP0_INTCTL_VS_SHIFT)
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# define CP0_INTCTL_VS_128BYTES (0x04 << CP0_INTCTL_VS_SHIFT)
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# define CP0_INTCTL_VS_256BYTES (0x08 << CP0_INTCTL_VS_SHIFT)
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# define CP0_INTCTL_VS_512BYTES (0x10 << CP0_INTCTL_VS_SHIFT)
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||||
|
||||
/* Register Number: 12 Sel: 2 Name: SRSCtl */
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||||
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||||
#define CP0_SRSCTL_CSS_SHIFT (0) /* Bits 0-3: Current shadow bit set */
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#define CP0_SRSCTL_CSS_MASK (15 << CP0_SRSCTL_CSS_SHIFT)
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#define CP0_SRSCTL_PSS_SHIFT (6) /* Bits 6-9: Previous shadow set */
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#define CP0_SRSCTL_PSS_MASK (15 << CP0_SRSCTL_PSS_SHIFT)
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#define CP0_SRSCTL_ESS_SHIFT (12) /* Bits 12-15: Exception shadow sets */
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#define CP0_SRSCTL_ESS_MASK (15 << CP0_SRSCTL_ESS_SHIFT)
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#define CP0_SRSCTL_EICSS_SHIFT (18) /* Bits 18-21: External interrupt controller shadow sets */
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#define CP0_SRSCTL_EICSS_MASK (15 << CP0_SRSCTL_EICSS_SHIFT)
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#define CP0_SRSCTL_HSS_SHIFT (26) /* Bits 26-29: High shadow sets */
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#define CP0_SRSCTL_HSS_MASK (15 << CP0_SRSCTL_HSS_SHIFT)
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# define CP0_SRSCTL_HSS_1SET (0 << CP0_SRSCTL_HSS_SHIFT) /* One shadow set (normal GPR set) */
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# define CP0_SRSCTL_HSS_2SETS (1 << CP0_SRSCTL_HSS_SHIFT) /* Two shadow sets */
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# define CP0_SRSCTL_HSS_4SETS (3 << CP0_SRSCTL_HSS_SHIFT) /* Four shadow sets */
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/* Register Number: 12 Sel: 3 Name: SRSMap */
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#define CP0_SRSMAP_SSV0_SHIFT (0) /* Bits 0-3: Shadow set vector 0 */
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#define CP0_SRSMAP_SSV0_MASK (15 << CP0_SRSMAP_SSV0_SHIFT)
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#define CP0_SRSMAP_SSV1_SHIFT (4) /* Bits 4-7: Shadow set vector 1 */
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#define CP0_SRSMAP_SSV1_MASK (15 << CP0_SRSMAP_SSV1_SHIFT)
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#define CP0_SRSMAP_SSV2_SHIFT (8) /* Bits 8-11: Shadow set vector 2 */
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#define CP0_SRSMAP_SSV2_MASK (15 << CP0_SRSMAP_SSV2_SHIFT)
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#define CP0_SRSMAP_SSV3_SHIFT (12) /* Bits 12-15: Shadow set vector 3 */
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#define CP0_SRSMAP_SSV3_MASK (15 << CP0_SRSMAP_SSV3_SHIFT)
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#define CP0_SRSMAP_SSV4_SHIFT (16) /* Bits 16-19: Shadow set vector 4 */
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#define CP0_SRSMAP_SSV4_MASK (15 << CP0_SRSMAP_SSV4_SHIFT)
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#define CP0_SRSMAP_SSV5_SHIFT (20) /* Bits 20-23: Shadow set vector 5 */
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#define CP0_SRSMAP_SSV5_MASK (15 << CP0_SRSMAP_SSV5_SHIFT)
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#define CP0_SRSMAP_SSV6_SHIFT (24) /* Bits 24-27: Shadow set vector 6 */
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#define CP0_SRSMAP_SSV6_MASK (15 << CP0_SRSMAP_SSV6_SHIFT)
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#define CP0_SRSMAP_SSV7_SHIFT (28) /* Bits 28-31: Shadow set vector 7 */
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#define CP0_SRSMAP_SSV7_MASK (15 << CP0_SRSMAP_SSV7_SHIFT)
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/* Register Number: 13 Sel: 0 Name: Cause
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* Function: Cause of last general exception
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* Compliance Level: Required.
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*
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* See arch/mips/include/mips32/cp0.h
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* NOTES: The following bits are added in the PIC32:
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*/
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#define CP0_CAUSE_R (1 << 26) /* Bit 26: R bit */
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#define CP0_CAUSE_DC (1 << 27) /* Bit 27: Disable count */
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#define CP0_CAUSE_TI (1 << 30) /* Bit 30: Timer interrupt bit *.
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/* Register Number: 14 Sel: 0 Name: EPC
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* Function: Program counter at last exception
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* Compliance Level: Required.
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*
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* See arch/mips/include/mips32/cp0.h
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*/
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/* Register Number: 15 Sel: 0 Name: PRId
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* Function: Processor identification and revision
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* Compliance Level: Required.
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*
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* See arch/mips/include/mips32/cp0.h
|
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* NOTE: Slightly different bit interpretations of some fields:
|
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*/
|
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|
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#define CP0_PRID_PATCH_SHIFT (5) /* Bits 0-1: Patch level */
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#define CP0_PRID_PATCH_MASK (3 << CP0_PRID_PATCH_SHIFT)
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#define CP0_PRID_MINOR_SHIFT (2) /* Bits 2-4: Minor revision number */
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#define CP0_PRID_MINOR_MASK (7 << CP0_PRID_MINOR_SHIFT)
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#define CP0_PRID_MAJOR_SHIFT (5) /* Bits 5-7: Major revision number */
|
||||
#define CP0_PRID_MAJOR_MASK (7 << CP0_PRID_MAJOR_SHIFT)
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||||
|
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#undef CP0_PRID_OPTIONS_SHIFT
|
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#undef CP0_PRID_OPTIONS_MASK
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|
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/* Register Number: 15 Sel: 1 Name: EBASE */
|
||||
|
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#define CP_EBASE_CPUNUM_SHIFT (0) /* Bits 0-9: CPU number */
|
||||
#define CP_EBASE_CPUNUM_MASK (0x3ff << CP_EBASE_CPUNUM_SHIFT)
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||||
#define CP_EBASE_SHIFT (12) /* Bits 30-31=10, Bits 12-29: Exception base */
|
||||
#define CP_EBASE_MASK (0x3ffff << CP_EBASE_SHIFT)
|
||||
|
||||
/* Register Number: 16 Sel: 0 Name: Config
|
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* Function: Configuration register
|
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* Compliance Level: Required.
|
||||
*
|
||||
* See arch/mips/include/mips32/cp0.h
|
||||
* 1. PIC32MX is always little-endian.
|
||||
* 2. Implementation specific bits defined.
|
||||
*/
|
||||
|
||||
#undef CP0_CONFIG_IMPL_SHIFT
|
||||
#undef CP0_CONFIG_IMPL_MASK
|
||||
|
||||
#define CP0_CONFIG_K23_SHIFT (0) /* Bits 28-30: KSEG2 and KSEG3 cacheability */
|
||||
#define CP0_CONFIG_K23_MASK (7 << CP0_CONFIG_K23_SHIFT)
|
||||
# define CP0_CONFIG_K23_UNCACHED (2 << CP0_CONFIG_K23_SHIFT)
|
||||
# define CP0_CONFIG_K23_CACHEABLE (3 << CP0_CONFIG_K23_SHIFT)
|
||||
#define CP0_CONFIG_KU_SHIFT (0) /* Bits 0-2: KUSEG and USEG cacheability */
|
||||
#define CP0_CONFIG_KU_MASK (7 << CP0_CONFIG_KU_SHIFT)
|
||||
# define CP0_CONFIG_KU_UNCACHED (2 << CP0_CONFIG_KU_SHIFT)
|
||||
# define CP0_CONFIG_KU_CACHEABLE (3 << CP0_CONFIG_KU_SHIFT)
|
||||
#define CP0_CONFIG_UDI (1 << 22) /* Bit 22: User defined bit */
|
||||
#define CP0_CONFIG_SB (1 << 21) /* Bit 32: Simple BE bus mode bit */
|
||||
#define CP0_CONFIG_MDU (1 << 20) /* Multipley/Divide unit bit */
|
||||
#define CP0_CONFIG_DS (1 << 16) /* Dual SRAM bit */
|
||||
|
||||
/* Register Number: 16 Sel: 1 Name: Config1
|
||||
* Function: Configuration register 1
|
||||
* Compliance Level: Required.
|
||||
*
|
||||
* See arch/mips/include/mips32/cp0.h
|
||||
*
|
||||
* Register Number: 16 Sel: 2 Name: Config2
|
||||
* Function: Configuration register 2
|
||||
* Compliance Level: Optional.
|
||||
*
|
||||
* See arch/mips/include/mips32/cp0.h
|
||||
*/
|
||||
|
||||
#undef CP0_CONFIG2_TBS_SHIFT
|
||||
#undef CP0_CONFIG2_TBS_MASK
|
||||
|
||||
/* Register Number: 16 Sel: 3 Name: Config3
|
||||
* Function: Configuration register 3
|
||||
* Compliance Level: Optional.
|
||||
*
|
||||
* See arch/mips/include/mips32/cp0.h
|
||||
*/
|
||||
|
||||
#define CP0_CONFIG3_SP (1 << 4) /* Bit 4: Support page bit */
|
||||
#define CP0_CONFIG3_VINT (1 << 5) /* Bit 5: Vector interrupt bit */
|
||||
#define CP0_CONFIG3_VEIC (1 << 6) /* Bit 6: External interrupt controller supported */
|
||||
|
||||
/* Register Number: 17-22 Reserved
|
||||
* Compliance Level: Optional.
|
||||
*/
|
||||
|
||||
/* Register Number: 23 Sel: 0 Name: Debug
|
||||
* Function: EJTAG Debug register
|
||||
* Compliance Level: Optional.
|
||||
*/
|
||||
|
||||
#define CP0_DEBUG_DSS (1 << 0) /* Bit 0: Debug single-step exception */
|
||||
#define CP0_DEBUG_DBP (1 << 1) /* Bit 1: Debug software breakpoint exception */
|
||||
#define CP0_DEBUG_DDBL (1 << 2) /* Bit 2: Debug data break exception on load */
|
||||
#define CP0_DEBUG_DDBS (1 << 3) /* Bit 3: Debug data break exception on store */
|
||||
#define CP0_DEBUG_DIB (1 << 4) /* Bit 4: Debug instruction break exception */
|
||||
#define CP0_DEBUG_DINT (1 << 5) /* Bit 5: Debug interrupt exception */
|
||||
#define CP0_DEBUG_SST (1 << 8) /* Bit 6: Enable debug single step exception */
|
||||
#define CP0_DEBUG_NOSST (1 << 9) /* Bit 7: No single step feature available */
|
||||
#define CP0_DEBUG_DEXCCODE_SHIFT (10) /* Bits 10-14: Cause of latest exception in DEBUG mode */
|
||||
#define CP0_DEBUG_DEXCCODE_MASK (31 << CP0_DEBUG_DEXCCODE_SHIFT)
|
||||
#define CP0_DEBUG_VER_SHIFT (15) /* Bits 15-17: EJTAG version */
|
||||
#define CP0_DEBUG_VER_MASK (7 << CP0_DEBUG_VER_SHIFT)
|
||||
#define CP0_DEBUG_DDBLIMPR (1 << 18) /* Bit 18: Imprecise debug data break load instruction */
|
||||
#define CP0_DEBUG_DDBSIMPR (1 << 19) /* Bit 19: Imprecise debug data break store instruction */
|
||||
#define CP0_DEBUG_IEXI (1 << 20) /* Bit 20: Imprecise error exception inhibit */
|
||||
#define CP0_DEBUG_DBUSEP (1 << 21) /* Bit 21: Data access bus error exception pending */
|
||||
#define CP0_DEBUG_CACHEEP (1 << 22) /* Bit 22: Imprecise cache error exception is pending */
|
||||
#define CP0_DEBUG_MCHECKP (1 << 23) /* Bit 23: Imprecise machine check exception is pending */
|
||||
#define CP0_DEBUG_IBUSEP (1 << 24) /* Bit 24: Bus error exception pending */
|
||||
#define CP0_DEBUG_COUNTDM (1 << 25) /* Bit 25: Count register behavior (1=running) */
|
||||
#define CP0_DEBUG_HALT (1 << 26) /* Bit 26: Internal system bus clock stopped */
|
||||
#define CP0_DEBUG_DOZE (1 << 27) /* Bit 27: Processor in low power mode */
|
||||
#define CP0_DEBUG_LSNM (1 << 28) /* Bit 28: Load/store in DSEG goes to main memory */
|
||||
#define CP0_DEBUG_NODCR (1 << 29) /* Bit 29: No DSEG preset */
|
||||
#define CP0_DEBUG_DM (1 << 30) /* Bit 30: Processor is operating in DEBUG mode */
|
||||
#define CP0_DEBUG_DBD (1 << 31) /* Bit 31: Last debug exception occurred in a dely slot */
|
||||
|
||||
/* Register Number: 23 Sel: ? Name: Debug2
|
||||
* Is this documented anywhere?
|
||||
*/
|
||||
|
||||
/* Register Number: 24 Sel: 0 Name: DEPC
|
||||
* Function: Program counter at last EJTAG debug exception
|
||||
* Compliance Level: Optional.
|
||||
*
|
||||
* See arch/mips/include/mips32/cp0.h
|
||||
*
|
||||
* Register Number: 25-29 Reserved
|
||||
* Compliance Level: Recommended/Optional.
|
||||
*
|
||||
* Register Number: 30 Sel: 0 Name: ErrorEPC
|
||||
* Function: Program counter at last error
|
||||
* Compliance Level: Required.
|
||||
*
|
||||
* See arch/mips/include/mips32/cp0.h
|
||||
*
|
||||
* Register Number: 31 Sel: 0 Name: DeSAVE
|
||||
* Function: EJTAG debug exception save register
|
||||
* Compliance Level: Optional.
|
||||
*
|
||||
* See arch/mips/include/mips32/cp0.h
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_MIPS_INCLUDE_PIC32MX_CP0_H */
|
||||
@@ -0,0 +1,214 @@
|
||||
/****************************************************************************
|
||||
* arch/mips/include/pic32mx/irq.h
|
||||
*
|
||||
* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* This file should never be included directed but, rather, only indirectly
|
||||
* through nuttx/irq.h
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_H
|
||||
#define __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <arch/pic32mx/chip.h>
|
||||
#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)
|
||||
# include <arch/pic32mx/irq_1xx2xx.h>
|
||||
#elif defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4)
|
||||
# include <arch/pic32mx/irq_3xx4xx.h>
|
||||
#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
|
||||
# include <arch/pic32mx/irq_5xx6xx7xx.h>
|
||||
#else
|
||||
# error "Unknown PIC32MX family
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Inline functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cp0_getintctl
|
||||
*
|
||||
* Description:
|
||||
* Get the CP0 IntCtl register
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline uint32_t cp0_getintctl(void)
|
||||
{
|
||||
register uint32_t intctl;
|
||||
__asm__ __volatile__
|
||||
(
|
||||
"\t.set push\n"
|
||||
"\t.set noat\n"
|
||||
"\t mfc0 %0, $12, 1\n" /* Get CP0 IntCtl register */
|
||||
"\t.set pop\n"
|
||||
: "=r" (intctl)
|
||||
:
|
||||
: "memory"
|
||||
);
|
||||
|
||||
return intctl;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cp0_putintctl
|
||||
*
|
||||
* Description:
|
||||
* Write the CP0 IntCtl register
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void cp0_putintctl(uint32_t intctl)
|
||||
{
|
||||
__asm__ __volatile__
|
||||
(
|
||||
"\t.set push\n"
|
||||
"\t.set noat\n"
|
||||
"\t.set noreorder\n"
|
||||
"\tmtc0 %0, $12, 1\n" /* Set the IntCtl to the provided value */
|
||||
"\t.set pop\n"
|
||||
:
|
||||
: "r" (intctl)
|
||||
: "memory"
|
||||
);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cp0_getebase
|
||||
*
|
||||
* Description:
|
||||
* Get the CP0 EBASE register
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline uint32_t cp0_getebase(void)
|
||||
{
|
||||
register uint32_t ebase;
|
||||
__asm__ __volatile__
|
||||
(
|
||||
"\t.set push\n"
|
||||
"\t.set noat\n"
|
||||
"\t mfc0 %0, $15, 1\n" /* Get CP0 EBASE register */
|
||||
"\t.set pop\n"
|
||||
: "=r" (ebase)
|
||||
:
|
||||
: "memory"
|
||||
);
|
||||
|
||||
return ebase;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cp0_putebase
|
||||
*
|
||||
* Description:
|
||||
* Write the CP0 EBASE register
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void cp0_putebase(uint32_t ebase)
|
||||
{
|
||||
__asm__ __volatile__
|
||||
(
|
||||
"\t.set push\n"
|
||||
"\t.set noat\n"
|
||||
"\t.set noreorder\n"
|
||||
"\tmtc0 %0, $15, 1\n" /* Set the EBASE to the provided value */
|
||||
"\t.set pop\n"
|
||||
:
|
||||
: "r" (ebase)
|
||||
: "memory"
|
||||
);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Variables
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_H */
|
||||
|
||||
@@ -0,0 +1,215 @@
|
||||
/****************************************************************************
|
||||
* arch/mips/include/pic32mx/irq_1xx2xx.h
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* This file should never be included directed but, rather, only indirectly
|
||||
* through nuttx/irq.h
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_1XX2XX_H
|
||||
#define __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_1XX2XX_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Interrupt vector numbers. These should be used to attach to interrupts
|
||||
* and to change interrupt priorities.
|
||||
*/
|
||||
|
||||
#define PIC32MX_IRQ_CT 0 /* Vector: 0, Core Timer Interrupt */
|
||||
#define PIC32MX_IRQ_CS0 1 /* Vector: 1, Core Software Interrupt 0 */
|
||||
#define PIC32MX_IRQ_CS1 2 /* Vector: 2, Core Software Interrupt 1 */
|
||||
#define PIC32MX_IRQ_INT0 3 /* Vector: 3, External Interrupt 0 */
|
||||
#define PIC32MX_IRQ_T1 4 /* Vector: 4, Timer 1 */
|
||||
#define PIC32MX_IRQ_IC1 5 /* Vector: 5, Input Capture 1 */
|
||||
#define PIC32MX_IRQ_OC1 6 /* Vector: 6, Output Compare 1 */
|
||||
#define PIC32MX_IRQ_INT1 7 /* Vector: 7, External Interrupt 1 */
|
||||
#define PIC32MX_IRQ_T2 8 /* Vector: 8, Timer 2 */
|
||||
#define PIC32MX_IRQ_IC2 9 /* Vector: 9, Input Capture 2 */
|
||||
#define PIC32MX_IRQ_OC2 10 /* Vector: 10, Output Compare 2 */
|
||||
#define PIC32MX_IRQ_INT2 11 /* Vector: 11, External Interrupt 2 */
|
||||
#define PIC32MX_IRQ_T3 12 /* Vector: 12, Timer 3 */
|
||||
#define PIC32MX_IRQ_IC3 13 /* Vector: 13, Input Capture 3 */
|
||||
#define PIC32MX_IRQ_OC3 14 /* Vector: 14, Output Compare 3 */
|
||||
#define PIC32MX_IRQ_INT3 15 /* Vector: 15, External Interrupt 3 */
|
||||
#define PIC32MX_IRQ_T4 16 /* Vector: 16, Timer 4 */
|
||||
#define PIC32MX_IRQ_IC4 17 /* Vector: 17, Input Capture 4 */
|
||||
#define PIC32MX_IRQ_OC4 18 /* Vector: 18, Output Compare 4 */
|
||||
#define PIC32MX_IRQ_INT4 19 /* Vector: 19, External Interrupt 4 */
|
||||
#define PIC32MX_IRQ_T5 20 /* Vector: 20, Timer 5 */
|
||||
#define PIC32MX_IRQ_IC5 21 /* Vector: 21, Input Capture 5 */
|
||||
#define PIC32MX_IRQ_OC5 22 /* Vector: 22, Output Compare 5 */
|
||||
#define PIC32MX_IRQ_AD1 23 /* Vector: 23, ADC1 Convert Done */
|
||||
#define PIC32MX_IRQ_FSCM 24 /* Vector: 24, Fail-Safe Clock Monitor */
|
||||
#define PIC32MX_IRQ_RTCC 25 /* Vector: 25, Real-Time Clock and Calendar */
|
||||
#define PIC32MX_IRQ_FCE 26 /* Vector: 26, Flash Control Event */
|
||||
#define PIC32MX_IRQ_CMP1 27 /* Vector: 27, Comparator 1 */
|
||||
#define PIC32MX_IRQ_CMP2 28 /* Vector: 28, Comparator 2 */
|
||||
#define PIC32MX_IRQ_CMP3 29 /* Vector: 29, Comparator 3 */
|
||||
#define PIC32MX_IRQ_USB 30 /* Vector: 30, USB */
|
||||
#define PIC32MX_IRQ_SPI1 31 /* Vector: 31, SPI1 */
|
||||
#define PIC32MX_IRQ_U1 32 /* Vector: 32, UART1 */
|
||||
#define PIC32MX_IRQ_I2C1 33 /* Vector: 33, I2C1 */
|
||||
#define PIC32MX_IRQ_CN 34 /* Vector: 34, Input Change */
|
||||
#define PIC32MX_IRQ_PMP 35 /* Vector: 35, Parallel Master Port */
|
||||
#define PIC32MX_IRQ_SPI2 36 /* Vector: 36, SPI2 */
|
||||
#define PIC32MX_IRQ_U2 37 /* Vector: 37, UART2 */
|
||||
#define PIC32MX_IRQ_I2C2 38 /* Vector: 38, I2C2 */
|
||||
#define PIC32MX_IRQ_CTMU 39 /* Vector: 39, CTMU */
|
||||
#define PIC32MX_IRQ_DMA0 40 /* Vector: 40, DMA Channel 0 */
|
||||
#define PIC32MX_IRQ_DMA1 41 /* Vector: 41, DMA Channel 1 */
|
||||
#define PIC32MX_IRQ_DMA2 42 /* Vector: 42, DMA Channel 2 */
|
||||
#define PIC32MX_IRQ_DMA3 43 /* Vector: 43, DMA Channel 3 */
|
||||
|
||||
#define PIC32MX_IRQ_BAD 44 /* Not a real IRQ number */
|
||||
#define NR_IRQS 44
|
||||
|
||||
/* Interrupt numbers. These should be used for enabling and disabling
|
||||
* interrupt sources. Note that there are more interrupt sources than
|
||||
* interrupt vectors and interrupt priorities. An offset of 128 is
|
||||
* used so that there is no overlap with the IRQ numbers and to avoid
|
||||
* errors due to misuse.
|
||||
*/
|
||||
|
||||
#define PIC32MX_IRQSRC0_FIRST (128+0)
|
||||
#define PIC32MX_IRQSRC_CT (128+0) /* Vector: 0, Core Timer Interrupt */
|
||||
#define PIC32MX_IRQSRC_CS0 (128+1) /* Vector: 1, Core Software Interrupt 0 */
|
||||
#define PIC32MX_IRQSRC_CS1 (128+2) /* Vector: 2, Core Software Interrupt 1 */
|
||||
#define PIC32MX_IRQSRC_INT0 (128+3) /* Vector: 3, External Interrupt 0 */
|
||||
#define PIC32MX_IRQSRC_T1 (128+4) /* Vector: 4, Timer 1 */
|
||||
#define PIC32MX_IRQSRC_IC1E (128+5) /* Vector: 5, Input Capture 1 Error */
|
||||
#define PIC32MX_IRQSRC_IC1 (128+6) /* Vector: 5, Input Capture 1 */
|
||||
#define PIC32MX_IRQSRC_OC1 (128+7) /* Vector: 6, Output Compare 1 */
|
||||
#define PIC32MX_IRQSRC_INT1 (128+8) /* Vector: 7, External Interrupt 1 */
|
||||
#define PIC32MX_IRQSRC_T2 (128+9) /* Vector: 8, Timer 2 */
|
||||
#define PIC32MX_IRQSRC_IC2E (128+10) /* Vector: 9, Input Capture 2 Error */
|
||||
#define PIC32MX_IRQSRC_IC2 (128+11) /* Vector: 9, Input Capture 2 */
|
||||
#define PIC32MX_IRQSRC_OC2 (128+12) /* Vector: 10, Output Compare 2 */
|
||||
#define PIC32MX_IRQSRC_INT2 (128+13) /* Vector: 11, External Interrupt 2 */
|
||||
#define PIC32MX_IRQSRC_T3 (128+14) /* Vector: 12, Timer 3 */
|
||||
#define PIC32MX_IRQSRC_IC3E (128+15) /* Vector: 13, Input Capture 3 Error */
|
||||
#define PIC32MX_IRQSRC_IC3 (128+16) /* Vector: 13, Input Capture 3 */
|
||||
#define PIC32MX_IRQSRC_OC3 (128+17) /* Vector: 14, Output Compare 3 */
|
||||
#define PIC32MX_IRQSRC_INT3 (128+18) /* Vector: 15, External Interrupt 3 */
|
||||
#define PIC32MX_IRQSRC_T4 (128+19) /* Vector: 16, Timer 4 */
|
||||
#define PIC32MX_IRQSRC_IC4E (128+20) /* Vector: 17, Input Capture 4 Error */
|
||||
#define PIC32MX_IRQSRC_IC4 (128+21) /* Vector: 17, Input Capture 4 */
|
||||
#define PIC32MX_IRQSRC_OC4 (128+22) /* Vector: 18, Output Compare 4 */
|
||||
#define PIC32MX_IRQSRC_INT4 (128+23) /* Vector: 19, External Interrupt 4 */
|
||||
#define PIC32MX_IRQSRC_T5 (128+24) /* Vector: 20, Timer 5 */
|
||||
#define PIC32MX_IRQSRC_IC5E (128+25) /* Vector: 21, Input Capture 5 Error */
|
||||
#define PIC32MX_IRQSRC_IC5 (128+26) /* Vector: 21, Input Capture 5 */
|
||||
#define PIC32MX_IRQSRC_OC5 (128+27) /* Vector: 22, Output Compare 5 */
|
||||
#define PIC32MX_IRQSRC_AD1 (128+28) /* Vector: 23, ADC1 Convert Done */
|
||||
#define PIC32MX_IRQSRC_FSCM (128+29) /* Vector: 24, Fail-Safe Clock Monitor */
|
||||
#define PIC32MX_IRQSRC_RTCC (128+30) /* Vector: 25, Real-Time Clock and Calendar */
|
||||
#define PIC32MX_IRQSRC_FCE (128+31) /* Vector: 26, Flash Control Event */
|
||||
#define PIC32MX_IRQSRC0_LAST (128+31)
|
||||
|
||||
#define PIC32MX_IRQSRC1_FIRST (128+32)
|
||||
#define PIC32MX_IRQSRC_CMP1 (128+32) /* Vector: 27, Comparator 1 Interrupt */
|
||||
#define PIC32MX_IRQSRC_CMP2 (128+33) /* Vector: 28, Comparator 2 Interrupt */
|
||||
#define PIC32MX_IRQSRC_CMP2 (128+34) /* Vector: 29, Comparator 3 Interrupt */
|
||||
#define PIC32MX_IRQSRC_USB (128+35) /* Vector: 30, USB */
|
||||
#define PIC32MX_IRQSRC_SPI1E (128+36) /* Vector: 31, SPI1 */
|
||||
#define PIC32MX_IRQSRC_SPI1TX (128+37) /* Vector: 31, " " */
|
||||
#define PIC32MX_IRQSRC_SPI1RX (128+38) /* Vector: 31, " " */
|
||||
#define PIC32MX_IRQSRC_U1E (128+39) /* Vector: 32, UART1 */
|
||||
#define PIC32MX_IRQSRC_U1RX (128+40) /* Vector: 32, " " */
|
||||
#define PIC32MX_IRQSRC_U1TX (128+41) /* Vector: 32, " " */
|
||||
#define PIC32MX_IRQSRC_I2C1B (128+42) /* Vector: 33, I2C1 */
|
||||
#define PIC32MX_IRQSRC_I2C1S (128+43) /* Vector: 33, " " */
|
||||
#define PIC32MX_IRQSRC_I2C1M (128+44) /* Vector: 33, " " */
|
||||
#define PIC32MX_IRQSRC_CNA (128+45) /* Vector: 34, Input Change Interrupt */
|
||||
#define PIC32MX_IRQSRC_CNB (128+46) /* Vector: 34, Input Change Interrupt */
|
||||
#define PIC32MX_IRQSRC_CNC (128+47) /* Vector: 34, Input Change Interrupt */
|
||||
#define PIC32MX_IRQSRC_PMP (128+48) /* Vector: 35, Parallel Master Port */
|
||||
#define PIC32MX_IRQSRC_PMPE (128+49) /* Vector: 35, Parallel Master Port */
|
||||
#define PIC32MX_IRQSRC_SPI2E (128+50) /* Vector: 36, SPI2 */
|
||||
#define PIC32MX_IRQSRC_SPI2TX (128+51) /* Vector: 36, " " */
|
||||
#define PIC32MX_IRQSRC_SPI2RX (128+52) /* Vector: 36, " " */
|
||||
#define PIC32MX_IRQSRC_U2E (128+53) /* Vector: 37, UART2 */
|
||||
#define PIC32MX_IRQSRC_U2RX (128+54) /* Vector: 37, " " */
|
||||
#define PIC32MX_IRQSRC_U2TX (128+55) /* Vector: 37, " " */
|
||||
#define PIC32MX_IRQSRC_I2C2B (128+56) /* Vector: 38, I2C2 */
|
||||
#define PIC32MX_IRQSRC_I2C2S (128+57) /* Vector: 38, " " */
|
||||
#define PIC32MX_IRQSRC_I2C2M (128+58) /* Vector: 38, " " */
|
||||
#define PIC32MX_IRQSRC_CTMU (128+59) /* Vector: 39, CTMU */
|
||||
#define PIC32MX_IRQSRC_DMA0 (128+60) /* Vector: 40, DMA Channel 0 */
|
||||
#define PIC32MX_IRQSRC_DMA1 (128+61) /* Vector: 41, DMA Channel 1 */
|
||||
#define PIC32MX_IRQSRC_DMA2 (128+62) /* Vector: 42, DMA Channel 2 */
|
||||
#define PIC32MX_IRQSRC_DMA3 (128+63) /* Vector: 43, DMA Channel 3 */
|
||||
#define PIC32MX_IRQSRC1_LAST (128+63)
|
||||
|
||||
#define PIC32MX_IRQSRC_FIRST PIC32MX_IRQSRC0_FIRST
|
||||
#define PIC32MX_IRQSRC_LAST PIC32MX_IRQSRC1_LAST
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Inline functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Variables
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_1XX2XX_H */
|
||||
|
||||
@@ -0,0 +1,204 @@
|
||||
/****************************************************************************
|
||||
* arch/mips/include/pic32mx/irq_3xx4xx.h
|
||||
*
|
||||
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* This file should never be included directed but, rather, only indirectly
|
||||
* through nuttx/irq.h
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_3XX4XX_H
|
||||
#define __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_3XX4XX_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Interrupt vector numbers. These should be used to attach to interrupts
|
||||
* and to change interrupt priorities.
|
||||
*/
|
||||
|
||||
#define PIC32MX_IRQ_CT 0 /* Vector: 0, Core Timer Interrupt */
|
||||
#define PIC32MX_IRQ_CS0 1 /* Vector: 1, Core Software Interrupt 0 */
|
||||
#define PIC32MX_IRQ_CS1 2 /* Vector: 2, Core Software Interrupt 1 */
|
||||
#define PIC32MX_IRQ_INT0 3 /* Vector: 3, External Interrupt 0 */
|
||||
#define PIC32MX_IRQ_T1 4 /* Vector: 4, Timer 1 */
|
||||
#define PIC32MX_IRQ_IC1 5 /* Vector: 5, Input Capture 1 */
|
||||
#define PIC32MX_IRQ_OC1 6 /* Vector: 6, Output Compare 1 */
|
||||
#define PIC32MX_IRQ_INT1 7 /* Vector: 7, External Interrupt 1 */
|
||||
#define PIC32MX_IRQ_T2 8 /* Vector: 8, Timer 2 */
|
||||
#define PIC32MX_IRQ_IC2 9 /* Vector: 9, Input Capture 2 */
|
||||
#define PIC32MX_IRQ_OC2 10 /* Vector: 10, Output Compare 2 */
|
||||
#define PIC32MX_IRQ_INT2 11 /* Vector: 11, External Interrupt 2 */
|
||||
#define PIC32MX_IRQ_T3 12 /* Vector: 12, Timer 3 */
|
||||
#define PIC32MX_IRQ_IC3 13 /* Vector: 13, Input Capture 3 */
|
||||
#define PIC32MX_IRQ_OC3 14 /* Vector: 14, Output Compare 3 */
|
||||
#define PIC32MX_IRQ_INT3 15 /* Vector: 15, External Interrupt 3 */
|
||||
#define PIC32MX_IRQ_T4 16 /* Vector: 16, Timer 4 */
|
||||
#define PIC32MX_IRQ_IC4 17 /* Vector: 17, Input Capture 4 */
|
||||
#define PIC32MX_IRQ_OC4 18 /* Vector: 18, Output Compare 4 */
|
||||
#define PIC32MX_IRQ_INT4 19 /* Vector: 19, External Interrupt 4 */
|
||||
#define PIC32MX_IRQ_T5 20 /* Vector: 20, Timer 5 */
|
||||
#define PIC32MX_IRQ_IC5 21 /* Vector: 21, Input Capture 5 */
|
||||
#define PIC32MX_IRQ_OC5 22 /* Vector: 22, Output Compare 5 */
|
||||
#define PIC32MX_IRQ_SPI1 23 /* Vector: 23, SPI1 */
|
||||
#define PIC32MX_IRQ_U1 24 /* Vector: 24, UART1 */
|
||||
#define PIC32MX_IRQ_I2C1 25 /* Vector: 25, I2C1 */
|
||||
#define PIC32MX_IRQ_CN 26 /* Vector: 26, Input Change Interrupt */
|
||||
#define PIC32MX_IRQ_AD1 27 /* Vector: 27, ADC1 Convert Done */
|
||||
#define PIC32MX_IRQ_PMP 28 /* Vector: 28, Parallel Master Port */
|
||||
#define PIC32MX_IRQ_CMP1 29 /* Vector: 29, Comparator Interrupt */
|
||||
#define PIC32MX_IRQ_CMP2 30 /* Vector: 30, Comparator Interrupt */
|
||||
#define PIC32MX_IRQ_SPI2 31 /* Vector: 31, SPI2 */
|
||||
#define PIC32MX_IRQ_U2 32 /* Vector: 32, UART2 */
|
||||
#define PIC32MX_IRQ_I2C2 33 /* Vector: 33, I2C2 */
|
||||
#define PIC32MX_IRQ_FSCM 34 /* Vector: 34, Fail-Safe Clock Monitor */
|
||||
#define PIC32MX_IRQ_RTCC 35 /* Vector: 35, Real-Time Clock and Calendar */
|
||||
#define PIC32MX_IRQ_DMA0 36 /* Vector: 36, DMA Channel 0 */
|
||||
#define PIC32MX_IRQ_DMA1 37 /* Vector: 37, DMA Channel 1 */
|
||||
#define PIC32MX_IRQ_DMA2 38 /* Vector: 38, DMA Channel 2 */
|
||||
#define PIC32MX_IRQ_DMA3 39 /* Vector: 39, DMA Channel 3 */
|
||||
/* Vectors 40-43: Not used */
|
||||
#define PIC32MX_IRQ_FCE 44 /* Vector: 44, Flash Control Event */
|
||||
#define PIC32MX_IRQ_USB 45 /* Vector: 45, USB */
|
||||
|
||||
#define PIC32MX_IRQ_BAD 46 /* Not a real IRQ number */
|
||||
#define NR_IRQS 46
|
||||
|
||||
/* Interrupt numbers. These should be used for enabling and disabling
|
||||
* interrupt sources. Note that there are more interrupt sources than
|
||||
* interrupt vectors and interrupt priorities. An offset of 128 is
|
||||
* used so that there is no overlap with the IRQ numbers and to avoid
|
||||
* errors due to misuse.
|
||||
*/
|
||||
|
||||
#define PIC32MX_IRQSRC0_FIRST (128+0)
|
||||
#define PIC32MX_IRQSRC_CT (128+0) /* Vector: 0, Core Timer Interrupt */
|
||||
#define PIC32MX_IRQSRC_CS0 (128+1) /* Vector: 1, Core Software Interrupt 0 */
|
||||
#define PIC32MX_IRQSRC_CS1 (128+2) /* Vector: 2, Core Software Interrupt 1 */
|
||||
#define PIC32MX_IRQSRC_INT0 (128+3) /* Vector: 3, External Interrupt 0 */
|
||||
#define PIC32MX_IRQSRC_T1 (128+4) /* Vector: 4, Timer 1 */
|
||||
#define PIC32MX_IRQSRC_IC1 (128+5) /* Vector: 5, Input Capture 1 */
|
||||
#define PIC32MX_IRQSRC_OC1 (128+6) /* Vector: 6, Output Compare 1 */
|
||||
#define PIC32MX_IRQSRC_INT1 (128+7) /* Vector: 7, External Interrupt 1 */
|
||||
#define PIC32MX_IRQSRC_T2 (128+8) /* Vector: 8, Timer 2 */
|
||||
#define PIC32MX_IRQSRC_IC2 (128+9) /* Vector: 9, Input Capture 2 */
|
||||
#define PIC32MX_IRQSRC_OC2 (128+10) /* Vector: 10, Output Compare 2 */
|
||||
#define PIC32MX_IRQSRC_INT2 (128+11) /* Vector: 11, External Interrupt 2 */
|
||||
#define PIC32MX_IRQSRC_T3 (128+12) /* Vector: 12, Timer 3 */
|
||||
#define PIC32MX_IRQSRC_IC3 (128+13) /* Vector: 13, Input Capture 3 */
|
||||
#define PIC32MX_IRQSRC_OC3 (128+14) /* Vector: 14, Output Compare 3 */
|
||||
#define PIC32MX_IRQSRC_INT3 (128+15) /* Vector: 15, External Interrupt 3 */
|
||||
#define PIC32MX_IRQSRC_T4 (128+16) /* Vector: 16, Timer 4 */
|
||||
#define PIC32MX_IRQSRC_IC4 (128+17) /* Vector: 17, Input Capture 4 */
|
||||
#define PIC32MX_IRQSRC_OC4 (128+18) /* Vector: 18, Output Compare 4 */
|
||||
#define PIC32MX_IRQSRC_INT4 (128+19) /* Vector: 19, External Interrupt 4 */
|
||||
#define PIC32MX_IRQSRC_T5 (128+20) /* Vector: 20, Timer 5 */
|
||||
#define PIC32MX_IRQSRC_IC5 (128+21) /* Vector: 21, Input Capture 5 */
|
||||
#define PIC32MX_IRQSRC_OC5 (128+22) /* Vector: 22, Output Compare 5 */
|
||||
#define PIC32MX_IRQSRC_SPI1E (128+23) /* Vector: 23, SPI1 */
|
||||
#define PIC32MX_IRQSRC_SPI1TX (128+24) /* Vector: 23, " " */
|
||||
#define PIC32MX_IRQSRC_SPI1RX (128+25) /* Vector: 23, " " */
|
||||
#define PIC32MX_IRQSRC_U1E (128+26) /* Vector: 24, UART1 */
|
||||
#define PIC32MX_IRQSRC_U1RX (128+27) /* Vector: 24, " " */
|
||||
#define PIC32MX_IRQSRC_U1TX (128+28) /* Vector: 24, " " */
|
||||
#define PIC32MX_IRQSRC_I2C1B (128+29) /* Vector: 25, I2C1 */
|
||||
#define PIC32MX_IRQSRC_I2C1S (128+30) /* Vector: 25, " " */
|
||||
#define PIC32MX_IRQSRC_I2C1M (128+31) /* Vector: 25, " " */
|
||||
#define PIC32MX_IRQSRC0_LAST (128+31)
|
||||
|
||||
#define PIC32MX_IRQSRC1_FIRST (128+32)
|
||||
#define PIC32MX_IRQSRC_CN (128+32) /* Vector: 26, Input Change Interrupt */
|
||||
#define PIC32MX_IRQSRC_AD1 (128+33) /* Vector: 27, ADC1 Convert Done */
|
||||
#define PIC32MX_IRQSRC_PMP (128+34) /* Vector: 28, Parallel Master Port */
|
||||
#define PIC32MX_IRQSRC_CMP1 (128+35) /* Vector: 29, Comparator Interrupt */
|
||||
#define PIC32MX_IRQSRC_CMP2 (128+36) /* Vector: 30, Comparator Interrupt */
|
||||
#define PIC32MX_IRQSRC_SPI2E (128+37) /* Vector: 31, SPI2 */
|
||||
#define PIC32MX_IRQSRC_SPI2TX (128+38) /* Vector: 31, " " */
|
||||
#define PIC32MX_IRQSRC_SPI2RX (128+39) /* Vector: 31, " " */
|
||||
#define PIC32MX_IRQSRC_U2E (128+40) /* Vector: 32, UART2 */
|
||||
#define PIC32MX_IRQSRC_U2RX (128+41) /* Vector: 32, " " */
|
||||
#define PIC32MX_IRQSRC_U2TX (128+42) /* Vector: 32, " " */
|
||||
#define PIC32MX_IRQSRC_I2C2B (128+43) /* Vector: 33, I2C2 */
|
||||
#define PIC32MX_IRQSRC_I2C2S (128+44) /* Vector: 33, " " */
|
||||
#define PIC32MX_IRQSRC_I2C2M (128+45) /* Vector: 33, " " */
|
||||
#define PIC32MX_IRQSRC_FSCM (128+46) /* Vector: 34, Fail-Safe Clock Monitor */
|
||||
#define PIC32MX_IRQSRC_RTCC (128+47) /* Vector: 35, Real-Time Clock and Calendar */
|
||||
#define PIC32MX_IRQSRC_DMA0 (128+48) /* Vector: 36, DMA Channel 0 */
|
||||
#define PIC32MX_IRQSRC_DMA1 (128+49) /* Vector: 37, DMA Channel 1 */
|
||||
#define PIC32MX_IRQSRC_DMA2 (128+50) /* Vector: 38, DMA Channel 2 */
|
||||
#define PIC32MX_IRQSRC_DMA3 (128+51) /* Vector: 39, DMA Channel 3 */
|
||||
#define PIC32MX_IRQSRC_FCE (128+56) /* Vector: 44, Flash Control Event */
|
||||
#define PIC32MX_IRQSRC_USB (128+57) /* Vector: 45, USB */
|
||||
#define PIC32MX_IRQSRC1_LAST (128+57)
|
||||
|
||||
#define PIC32MX_IRQSRC_FIRST PIC32MX_IRQSRC0_FIRST
|
||||
#define PIC32MX_IRQSRC_LAST PIC32MX_IRQSRC1_LAST
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Inline functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Variables
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_3XX4XX_H */
|
||||
|
||||
@@ -0,0 +1,273 @@
|
||||
/****************************************************************************
|
||||
* arch/mips/include/pic32mx/irq_5xx6xx7xx.h
|
||||
*
|
||||
* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* This file should never be included directed but, rather, only indirectly
|
||||
* through nuttx/irq.h
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_5XX6XX7XX_H
|
||||
#define __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_5XX6XX7XX_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Interrupt vector numbers. These should be used to attach to interrupts
|
||||
* and to change interrupt priorities.
|
||||
*/
|
||||
|
||||
#define PIC32MX_IRQ_CT 0 /* Vector: 0, Core Timer Interrupt */
|
||||
#define PIC32MX_IRQ_CS0 1 /* Vector: 1, Core Software Interrupt 0 */
|
||||
#define PIC32MX_IRQ_CS1 2 /* Vector: 2, Core Software Interrupt 1 */
|
||||
#define PIC32MX_IRQ_INT0 3 /* Vector: 3, External Interrupt 0 */
|
||||
#define PIC32MX_IRQ_T1 4 /* Vector: 4, Timer 1 */
|
||||
#define PIC32MX_IRQ_IC1 5 /* Vector: 5, Input Capture 1 */
|
||||
#define PIC32MX_IRQ_OC1 6 /* Vector: 6, Output Compare 1 */
|
||||
#define PIC32MX_IRQ_INT1 7 /* Vector: 7, External Interrupt 1 */
|
||||
#define PIC32MX_IRQ_T2 8 /* Vector: 8, Timer 2 */
|
||||
#define PIC32MX_IRQ_IC2 9 /* Vector: 9, Input Capture 2 */
|
||||
#define PIC32MX_IRQ_OC2 10 /* Vector: 10, Output Compare 2 */
|
||||
#define PIC32MX_IRQ_INT2 11 /* Vector: 11, External Interrupt 2 */
|
||||
#define PIC32MX_IRQ_T3 12 /* Vector: 12, Timer 3 */
|
||||
#define PIC32MX_IRQ_IC3 13 /* Vector: 13, Input Capture 3 */
|
||||
#define PIC32MX_IRQ_OC3 14 /* Vector: 14, Output Compare 3 */
|
||||
#define PIC32MX_IRQ_INT3 15 /* Vector: 15, External Interrupt 3 */
|
||||
#define PIC32MX_IRQ_T4 16 /* Vector: 16, Timer 4 */
|
||||
#define PIC32MX_IRQ_IC4 17 /* Vector: 17, Input Capture 4 */
|
||||
#define PIC32MX_IRQ_OC4 18 /* Vector: 18, Output Compare 4 */
|
||||
#define PIC32MX_IRQ_INT4 19 /* Vector: 19, External Interrupt 4 */
|
||||
#define PIC32MX_IRQ_T5 20 /* Vector: 20, Timer 5 */
|
||||
#define PIC32MX_IRQ_IC5 21 /* Vector: 21, Input Capture 5 */
|
||||
#define PIC32MX_IRQ_OC5 22 /* Vector: 22, Output Compare 5 */
|
||||
#define PIC32MX_IRQ_SPI1 23 /* Vector: 23, SPI1 */
|
||||
#define PIC32MX_IRQ_VEC24 24 /* Vector: 24, UART1, SPI3, I2C3 */
|
||||
# define PIC32MX_IRQ_U1 24 /* Vector: 24, UART1 */
|
||||
# define PIC32MX_IRQ_SPI3 24 /* Vector: 24, SPI3 */
|
||||
# define PIC32MX_IRQ_I2C3 24 /* Vector: 24, I2C3 */
|
||||
#define PIC32MX_IRQ_I2C1 25 /* Vector: 25, I2C1 */
|
||||
#define PIC32MX_IRQ_CN 26 /* Vector: 26, Input Change Interrupt */
|
||||
#define PIC32MX_IRQ_AD1 27 /* Vector: 27, ADC1 Convert Done */
|
||||
#define PIC32MX_IRQ_PMP 28 /* Vector: 28, Parallel Master Port */
|
||||
#define PIC32MX_IRQ_CMP1 29 /* Vector: 29, Comparator Interrupt */
|
||||
#define PIC32MX_IRQ_CMP2 30 /* Vector: 30, Comparator Interrupt */
|
||||
#define PIC32MX_IRQ_VEC31 31 /* Vector: 31, UART3, SPI2, I2C4 */
|
||||
# define PIC32MX_IRQ_U3 31 /* Vector: 31, UART3 */
|
||||
# define PIC32MX_IRQ_SPI2 31 /* Vector: 31, SPI2 */
|
||||
# define PIC32MX_IRQ_I2C4 31 /* Vector: 31, I2C4 */
|
||||
#define PIC32MX_IRQ_VEC31 32 /* Vector: 32, UART2, SPI4, I2C5 */
|
||||
# define PIC32MX_IRQ_U2 32 /* Vector: 32, UART2 */
|
||||
# define PIC32MX_IRQ_SPI4 32 /* Vector: 32, SPI4 */
|
||||
# define PIC32MX_IRQ_I2C5 32 /* Vector: 32, I2C5 */
|
||||
#define PIC32MX_IRQ_I2C2 33 /* Vector: 33, I2C2 */
|
||||
#define PIC32MX_IRQ_FSCM 34 /* Vector: 34, Fail-Safe Clock Monitor */
|
||||
#define PIC32MX_IRQ_RTCC 35 /* Vector: 35, Real-Time Clock and Calendar */
|
||||
#define PIC32MX_IRQ_DMA0 36 /* Vector: 36, DMA Channel 0 */
|
||||
#define PIC32MX_IRQ_DMA1 37 /* Vector: 37, DMA Channel 1 */
|
||||
#define PIC32MX_IRQ_DMA2 38 /* Vector: 38, DMA Channel 2 */
|
||||
#define PIC32MX_IRQ_DMA3 39 /* Vector: 39, DMA Channel 3 */
|
||||
#define PIC32MX_IRQ_DMA4 40 /* Vector: 40, DMA Channel 3 */
|
||||
#define PIC32MX_IRQ_DMA5 41 /* Vector: 41, DMA Channel 3 */
|
||||
#define PIC32MX_IRQ_DMA6 42 /* Vector: 42, DMA Channel 3 */
|
||||
#define PIC32MX_IRQ_DMA7 43 /* Vector: 43, DMA Channel 3 */
|
||||
#define PIC32MX_IRQ_FCE 44 /* Vector: 44, Flash Control Event */
|
||||
#define PIC32MX_IRQ_USB 45 /* Vector: 45, USB Interrupt */
|
||||
#define PIC32MX_IRQ_CAN1 46 /* Vector: 46, Control Area Network 1 */
|
||||
#define PIC32MX_IRQ_CAN2 47 /* Vector: 47, Control Area Network 2 */
|
||||
#define PIC32MX_IRQ_ETH 48 /* Vector: 48, Ethernet interrupt */
|
||||
#define PIC32MX_IRQ_U4 49 /* Vector: 49, UART4 */
|
||||
#define PIC32MX_IRQ_U6 50 /* Vector: 50, UART6 */
|
||||
#define PIC32MX_IRQ_U5 51 /* Vector: 51, UART5 */
|
||||
#define PIC32MX_IRQ_BAD 52 /* Not a real IRQ number */
|
||||
#define NR_IRQS 52
|
||||
|
||||
/* Interrupt numbers. These should be used for enabling and disabling
|
||||
* interrupt sources. Note that there are more interrupt sources than
|
||||
* interrupt vectors and interrupt priorities. An offset of 128 is
|
||||
* used so that there is no overlap with the IRQ numbers and to avoid
|
||||
* errors due to misuse.
|
||||
*/
|
||||
|
||||
#define PIC32MX_IRQSRC0_FIRST (128+0)
|
||||
#define PIC32MX_IRQSRC_CT (128+0) /* Vector: 0, Core Timer Interrupt */
|
||||
#define PIC32MX_IRQSRC_CS0 (128+1) /* Vector: 1, Core Software Interrupt 0 */
|
||||
#define PIC32MX_IRQSRC_CS1 (128+2) /* Vector: 2, Core Software Interrupt 1 */
|
||||
#define PIC32MX_IRQSRC_INT0 (128+3) /* Vector: 3, External Interrupt 0 */
|
||||
#define PIC32MX_IRQSRC_T1 (128+4) /* Vector: 4, Timer 1 */
|
||||
#define PIC32MX_IRQSRC_IC1 (128+5) /* Vector: 5, Input Capture 1 */
|
||||
#define PIC32MX_IRQSRC_OC1 (128+6) /* Vector: 6, Output Compare 1 */
|
||||
#define PIC32MX_IRQSRC_INT1 (128+7) /* Vector: 7, External Interrupt 1 */
|
||||
#define PIC32MX_IRQSRC_T2 (128+8) /* Vector: 8, Timer 2 */
|
||||
#define PIC32MX_IRQSRC_IC2 (128+9) /* Vector: 9, Input Capture 2 */
|
||||
#define PIC32MX_IRQSRC_OC2 (128+10) /* Vector: 10, Output Compare 2 */
|
||||
#define PIC32MX_IRQSRC_INT2 (128+11) /* Vector: 11, External Interrupt 2 */
|
||||
#define PIC32MX_IRQSRC_T3 (128+12) /* Vector: 12, Timer 3 */
|
||||
#define PIC32MX_IRQSRC_IC3 (128+13) /* Vector: 13, Input Capture 3 */
|
||||
#define PIC32MX_IRQSRC_OC3 (128+14) /* Vector: 14, Output Compare 3 */
|
||||
#define PIC32MX_IRQSRC_INT3 (128+15) /* Vector: 15, External Interrupt 3 */
|
||||
#define PIC32MX_IRQSRC_T4 (128+16) /* Vector: 16, Timer 4 */
|
||||
#define PIC32MX_IRQSRC_IC4 (128+17) /* Vector: 17, Input Capture 4 */
|
||||
#define PIC32MX_IRQSRC_OC4 (128+18) /* Vector: 18, Output Compare 4 */
|
||||
#define PIC32MX_IRQSRC_INT4 (128+19) /* Vector: 19, External Interrupt 4 */
|
||||
#define PIC32MX_IRQSRC_T5 (128+20) /* Vector: 20, Timer 5 */
|
||||
#define PIC32MX_IRQSRC_IC5 (128+21) /* Vector: 21, Input Capture 5 */
|
||||
#define PIC32MX_IRQSRC_OC5 (128+22) /* Vector: 22, Output Compare 5 */
|
||||
#define PIC32MX_IRQSRC_SPI1E (128+23) /* Vector: 23, SPI1 Fault */
|
||||
#define PIC32MX_IRQSRC_SPI1RX (128+24) /* Vector: 23, " " Receive done */
|
||||
#define PIC32MX_IRQSRC_SPI1TX (128+25) /* Vector: 23, " " Transfer done */
|
||||
#define PIC32MX_IRQSRC_26 (128+26) /* Vector: 24, UART1, SPI3, I2C3 */
|
||||
# define PIC32MX_IRQSRC_U1E (128+26) /* Vector: 24, UART1 Error */
|
||||
# define PIC32MX_IRQSRC_SPI3E (128+26) /* Vector: 24, SPI3 Fault */
|
||||
# define PIC32MX_IRQSRC_I2C3B (128+26) /* Vector: 24, I2C3 Bus collision event */
|
||||
#define PIC32MX_IRQSRC_27 (128+27) /* Vector: 24, UART1, SPI3, I2C3 */
|
||||
# define PIC32MX_IRQSRC_U1RX (128+27) /* Vector: 24, UART1 Receiver */
|
||||
# define PIC32MX_IRQSRC_SPI3RX (128+27) /* Vector: 24, SPI3 Receive done */
|
||||
# define PIC32MX_IRQSRC_I2C3S (128+27) /* Vector: 24, I2C3 Slave event */
|
||||
#define PIC32MX_IRQSRC_28 (128+27) /* Vector: 24, UART1, SPI3, I2C3 */
|
||||
# define PIC32MX_IRQSRC_U1TX (128+28) /* Vector: 24, UART1 Transmitter */
|
||||
# define PIC32MX_IRQSRC_SPI3TX (128+28) /* Vector: 24, SPI3 Transfer done */
|
||||
# define PIC32MX_IRQSRC_I2C3M (128+28) /* Vector: 24, I2C3 Master event */
|
||||
#define PIC32MX_IRQSRC_I2C1B (128+29) /* Vector: 25, I2C1 Bus collision event*/
|
||||
#define PIC32MX_IRQSRC_I2C1S (128+30) /* Vector: 25, " " Slave event */
|
||||
#define PIC32MX_IRQSRC_I2C1M (128+31) /* Vector: 25, " " Master event */
|
||||
#define PIC32MX_IRQSRC0_LAST (128+31)
|
||||
|
||||
#define PIC32MX_IRQSRC1_FIRST (128+32)
|
||||
#define PIC32MX_IRQSRC_CN (128+32) /* Vector: 26, Input Change Interrupt */
|
||||
#define PIC32MX_IRQSRC_AD1 (128+33) /* Vector: 27, ADC1 Convert Done */
|
||||
#define PIC32MX_IRQSRC_PMP (128+34) /* Vector: 28, Parallel Master Port */
|
||||
#define PIC32MX_IRQSRC_CMP1 (128+35) /* Vector: 29, Comparator Interrupt */
|
||||
#define PIC32MX_IRQSRC_CMP2 (128+36) /* Vector: 30, Comparator Interrupt */
|
||||
#define PIC32MX_IRQSRC_37 (128+37) /* Vector: 31, UART3, SPI2, I2C4 */
|
||||
# define PIC32MX_IRQSRC_U3E (128+37) /* Vector: 31, UART3 Error */
|
||||
# define PIC32MX_IRQSRC_SPI2E (128+37) /* Vector: 31, SPI2 Fault */
|
||||
# define PIC32MX_IRQSRC_I2C4B (128+37) /* Vector: 31, I2C4 Bus collision event */
|
||||
#define PIC32MX_IRQSRC_38 (128+38) /* Vector: 31, UART3, SPI2, I2C4 */
|
||||
# define PIC32MX_IRQSRC_U3RX (128+38) /* Vector: 31, UART3 Receiver */
|
||||
# define PIC32MX_IRQSRC_SPI2RX (128+38) /* Vector: 31, SPI2 Receive done */
|
||||
# define PIC32MX_IRQSRC_I2C4S (128+38) /* Vector: 31, I2C4 Slave event */
|
||||
#define PIC32MX_IRQSRC_39 (128+39) /* Vector: 31, UART3, SPI2, I2C4 */
|
||||
# define PIC32MX_IRQSRC_U3TX (128+39) /* Vector: 31, UART3 Transmitter */
|
||||
# define PIC32MX_IRQSRC_SPI2TX (128+39) /* Vector: 31, SPI2 Transfer done */
|
||||
# define PIC32MX_IRQSRC_I2C4M (128+39) /* Vector: 31, I2C4 Master event */
|
||||
#define PIC32MX_IRQSRC_40 (128+40) /* Vector: 32, UART2, SPI4, I2C5 */
|
||||
# define PIC32MX_IRQSRC_U2E (128+40) /* Vector: 32, UART2 Error */
|
||||
# define PIC32MX_IRQSRC_SPI4E (128+40) /* Vector: 32, SPI4 Fault */
|
||||
# define PIC32MX_IRQSRC_I2C5B (128+40) /* Vector: 32, I2C5 Bus collision event */
|
||||
#define PIC32MX_IRQSRC_41 (128+41) /* Vector: 32, UART2, SPI4, I2C5 */
|
||||
# define PIC32MX_IRQSRC_U2RX (128+41) /* Vector: 32, UART2 Receiver */
|
||||
# define PIC32MX_IRQSRC_SPI4RX (128+41) /* Vector: 32, SPI4 Receive done */
|
||||
# define PIC32MX_IRQSRC_I2C5S (128+41) /* Vector: 32, I2C5 Slave event */
|
||||
#define PIC32MX_IRQSRC_42 (128+42) /* Vector: 32, UART2, SPI4, I2C5 */
|
||||
# define PIC32MX_IRQSRC_U2TX (128+42) /* Vector: 32, UART2 Transmitter */
|
||||
# define PIC32MX_IRQSRC_SPI4TX (128+42) /* Vector: 32, SPI4 Transfer done */
|
||||
# define PIC32MX_IRQSRC_I2C5M (128+42) /* Vector: 32, I2C5 Master event */
|
||||
#define PIC32MX_IRQSRC_I2C2B (128+43) /* Vector: 33, I2C2 Bus collision event */
|
||||
#define PIC32MX_IRQSRC_I2C2S (128+44) /* Vector: 33, " " Slave event */
|
||||
#define PIC32MX_IRQSRC_I2C2M (128+45) /* Vector: 33, " " Master event */
|
||||
#define PIC32MX_IRQSRC_FSCM (128+46) /* Vector: 34, Fail-Safe Clock Monitor */
|
||||
#define PIC32MX_IRQSRC_RTCC (128+47) /* Vector: 35, Real-Time Clock and Calendar */
|
||||
#define PIC32MX_IRQSRC_DMA0 (128+48) /* Vector: 36, DMA Channel 0 */
|
||||
#define PIC32MX_IRQSRC_DMA1 (128+49) /* Vector: 37, DMA Channel 1 */
|
||||
#define PIC32MX_IRQSRC_DMA2 (128+50) /* Vector: 38, DMA Channel 2 */
|
||||
#define PIC32MX_IRQSRC_DMA3 (128+51) /* Vector: 39, DMA Channel 3 */
|
||||
#define PIC32MX_IRQSRC_DMA4 (128+52) /* Vector: 40, DMA Channel 3 */
|
||||
#define PIC32MX_IRQSRC_DMA5 (128+53) /* Vector: 41, DMA Channel 3 */
|
||||
#define PIC32MX_IRQSRC_DMA6 (128+54) /* Vector: 42, DMA Channel 3 */
|
||||
#define PIC32MX_IRQSRC_DMA7 (128+55) /* Vector: 43, DMA Channel 3 */
|
||||
#define PIC32MX_IRQSRC_FCE (128+56) /* Vector: 44, Flash Control Event */
|
||||
#define PIC32MX_IRQSRC_USB (128+57) /* Vector: 45, USB Interrupt */
|
||||
#define PIC32MX_IRQSRC_CAN1 (128+58) /* Vector: 46, Control Area Network 1 */
|
||||
#define PIC32MX_IRQSRC_CAN2 (128+59) /* Vector: 47, Control Area Network 2 */
|
||||
#define PIC32MX_IRQSRC_ETH (128+60) /* Vector: 48, Ethernet interrupt */
|
||||
#define PIC32MX_IRQSRC_IC1E (128+61) /* Vector: 5, Input capture 1 error */
|
||||
#define PIC32MX_IRQSRC_IC2E (128+62) /* Vector: 9, Input capture 1 error */
|
||||
#define PIC32MX_IRQSRC_IC3E (128+63) /* Vector: 13, Input capture 1 error */
|
||||
#define PIC32MX_IRQSRC1_LAST (128+63)
|
||||
|
||||
#define PIC32MX_IRQSRC2_FIRST (128+64)
|
||||
#define PIC32MX_IRQSRC_IC4E (128+64) /* Vector: 17, Input capture 1 error */
|
||||
#define PIC32MX_IRQSRC_IC5E (128+65) /* Vector: 21, Input capture 1 error */
|
||||
#define PIC32MX_IRQSRC_PMPE (128+66) /* Vector: 28, Parallel master port error */
|
||||
#define PIC32MX_IRQSRC_U4E (128+67) /* Vector: 49, UART4 Error */
|
||||
#define PIC32MX_IRQSRC_U4RX (128+68) /* Vector: 49, UART4 Receiver */
|
||||
#define PIC32MX_IRQSRC_U4TX (128+69) /* Vector: 49, UART4 Transmitter */
|
||||
#define PIC32MX_IRQSRC_U6E (128+70) /* Vector: 50, UART6 Error */
|
||||
#define PIC32MX_IRQSRC_U6RX (128+71) /* Vector: 50, UART6 Receiver */
|
||||
#define PIC32MX_IRQSRC_U6TX (128+72) /* Vector: 50, UART6 Transmitter */
|
||||
#define PIC32MX_IRQSRC_U5E (128+73) /* Vector: 51, UART5 Error */
|
||||
#define PIC32MX_IRQSRC_U5RX (128+74) /* Vector: 51, UART5 Receiver */
|
||||
#define PIC32MX_IRQSRC_U5TX (128+75) /* Vector: 51, UART5 Transmitter */
|
||||
#define PIC32MX_IRQSRC2_LAST (128+75)
|
||||
|
||||
#define PIC32MX_IRQSRC_FIRST PIC32MX_IRQSRC0_FIRST
|
||||
#define PIC32MX_IRQSRC_LAST PIC32MX_IRQSRC2_LAST
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Inline functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Variables
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_5XX6XX7XX_H */
|
||||
|
||||
Reference in New Issue
Block a user