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git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5153 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
2012-09-17 18:18:44 +00:00
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nuttx/arch/mips/include/arch.h
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/****************************************************************************
* arch/mips/include/arch.h
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather,
* only indirectly through nuttx/arch.h
*/
#ifndef __ARCH_MIPS_INCLUDE_ARCH_H
#define __ARCH_MIPS_INCLUDE_ARCH_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Definitions
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ARCH_MIPS_INCLUDE_ARCH_H */
nuttx/arch/mips/include/irq.h
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/****************************************************************************
* arch/mips/include/irq.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_MIPS_INCLUDE_IRQ_H
#define __ARCH_MIPS_INCLUDE_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
/* Include NuttX-specific IRQ definitions */
#include <nuttx/irq.h>
/* Include chip-specific IRQ definitions (including IRQ numbers) */
#include <arch/chip/irq.h>
/* Include AVR architecture-specific IRQ definitions (including register
* save structure and irqsave()/irqrestore() macros
*/
#ifdef CONFIG_ARCH_MIPS32
# include <arch/mips32/irq.h>
#endif
/****************************************************************************
* Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_MIPS_INCLUDE_IRQ_H */
nuttx/arch/mips/include/limits.h
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/****************************************************************************
* arch/mips/include/limits.h
*
* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_MIPS_INCLUDE_LIMITS_H
#define __ARCH_MIPS_INCLUDE_LIMITS_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Definitions
****************************************************************************/
#define CHAR_BIT 8
#define SCHAR_MIN (-128)
#define SCHAR_MAX 127
#define UCHAR_MAX 255
/* These could be different on machines where char is unsigned */
#ifdef __CHAR_UNSIGNED__
#define CHAR_MIN 0
#define CHAR_MAX UCHAR_MAX
#else
#define CHAR_MIN SCHAR_MIN
#define CHAR_MAX SCHAR_MAX
#endif
#define SHRT_MIN (-32768)
#define SHRT_MAX 32767
#define USHRT_MAX 65535
#define INT_MIN (-2147483648)
#define INT_MAX 2147483647
#define UINT_MAX 4294967295
/* These change on 32-bit and 64-bit platforms */
#define LONG_MIN (-2147483648L)
#define LONG_MAX 2147483647L
#define ULONG_MAX 4294967295UL
#define LLONG_MIN (-9223372036854775808LL)
#define LLONG_MAX 9223372036854775807LL
#define ULLONG_MAX 18446744073709551615ULL
/* A pointer is 4 bytes */
#define PTR_MIN (-2147483648)
#define PTR_MAX 2147483647
#define UPTR_MAX 4294967295
#endif /* __ARCH_MIPS_INCLUDE_LIMITS_H */
nuttx/arch/mips/include/mips32/cp0.h
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/********************************************************************************************
* arch/mips/include/mips32/cp0.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_MIPS_INCLUDE_MIPS32_CP0_H
#define __ARCH_MIPS_INCLUDE_MIPS32_CP0_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
/********************************************************************************************
* Pre-Processor Definitions
********************************************************************************************/
/* CP0 Register Addresses *******************************************************************/
#ifdef __ASSEMBLY__
# define MIPS32_CP0_INDEX1 $0,0 /* Index into the TLB array */
# define MIPS32_CP0_RANDOM1 $1,0 /* Randomly generated index into the TLB array */
# define MIPS32_CP0_ENTRYLO01 $2,0 /* LS TLB entry for even-numbered pages */
# define MIPS32_CP0_ENTRYLO11 $3,0 /* LS TLB entry for odd-numbered pages */
# define MIPS32_CP0_CONTEXT2 $4,0 /* Page table address */
# define MIPS32_CP0_PAGEMASK1 $5,0 /* Variable page sizes in TLB entries */
# define MIPS32_CP0_WIRED1 $6,0 /* umber of fixed (“wired”) TLB entries */
# define MIPS32_CP0_BADVADDR $8,0 /* Address of most recent exception */
# define MIPS32_CP0_COUNT $9,0 /* Processor cycle count */
# define MIPS32_CP0_ENTRYHI1 $10,0 /* High-order portion of the TLB entry */
# define MIPS32_CP0_COMPARE $11,0 /* Timer interrupt control */
# define MIPS32_CP0_STATUS $12,0 /* Processor status and control */
# define MIPS32_CP0_CAUSE $13,0 /* Cause of last general exception */
# define MIPS32_CP0_EPC $14,0 /* Program counter at last exception */
# define MIPS32_CP0_PRID $15,0 /* Processor identification and revision */
# define MIPS32_CP0_CONFIG $16,0 /* Configuration register */
# define MIPS32_CP0_CONFIG1 $16,1 /* Configuration register 1 */
# define MIPS32_CP0_CONFIG2 $16,2 /* Configuration register 3 */
# define MIPS32_CP0_CONFIG3 $16,2 /* Configuration register 3 */
# define MIPS32_CP0_LLADDR $17,0 /* Load linked address */
# define MIPS32_CP0_WATCHLO2 $18,0 /* LS Watchpoint address */
# define MIPS32_CP0_WATCHHI2 $19,0 /* MS Watchpoint address and mask */
# define MIPS32_CP0_DEBUG3 $23,0 /* Debug control and exception status */
# define MIPS32_CP0_DEPC3 $24,0 /* Program counter at last debug exception */
# define MIPS32_CP0_ERRCTL $26,0 /* Controls access data CACHE instruction */
# define MIPS32_CP0_TAGLO $28,0 /* LS portion of cache tag interface */
# define MIPS32_CP0_DATALO $28,1 /* LS portion of cache tag interface */
# define MIPS32_CP0_TAGHI $29,0 /* MS portion of cache tag interface */
# define MIPS32_CP0_DATAHI $29,1 /* MS portion of cache tag interface */
# define MIPS32_CP0_ERROREPC2 $30,0 /* Program counter at last error */
# define MIPS32_CP0_DESAVE3 $31,0 /* Debug handler scratchpad register */
#endif
/* CP0 Registers ****************************************************************************/
/* Register Number: 0 Sel: 0 Name: Index
* Function: Index into the TLB array
* Compliance Level: Required for TLB-based MMUs; Optional otherwise.
*/
#define CP0_INDEX_SHIFT (0) /* Bits 0-(n-1): TLB Index */
#define CP0_INDEX_MASK (0x7fffffff)
#define CP0_INDEX_P (1 << 31) /* Bit 31: Probe failure */
/* Register Number: 1 Sel: 0 Name: Random
* Function: Randomly generated index into the TLB array
* Compliance Level: Required for TLB-based MMUs; Optional otherwise.
*
* This is a 32-bit register containing a random TLB index. The valid width is some fixed
* number, 'n', but the upper bits are padded so that no fields need be defined for this
* register.
*/
/* Register Number: 2 Sel: 0 Name: EntryLo0
* Function: Low-order portion of the TLB entry for even-numbered virtual pages
* Compliance Level: EntryLo0 is Required for a TLB-based MMU; Optional
* otherwise.
*
* Register Number: 3 Sel: 0 Name: EntryLo1
* Function: Low-order portion of the TLB entry for odd-numbered virtual pages
* Compliance Level: EntryLo1 is Required for a TLB-based MMU; Optional otherwise.
*/
#define CP0_ENTRYLO_G (1 << 0) /* Bit 0: Global bit */
#define CP0_ENTRYLO_V (1 << 1) /* Bit 1: Valild bit */
#define CP0_ENTRYLO_D (1 << 2) /* Bit 2: Dirty bit */
#define CP0_ENTRYLO_C_SHIFT (3) /* Bits 3-5: Coherency attribute */
#define CP0_ENTRYLO_C_MASK (7 << CP0_ENTRYLO_CSHIFT)
# define CP0_ENTRYLO_UNCACHED (2 << CP0_ENTRYLO_CSHIFT)
# define CP0_ENTRYLO_CACHEABLE (3 << CP0_ENTRYLO_CSHIFT)
#define CP0_ENTRYLO_PFN_SHIFT (6) /* Bits 6-29: Page frame number */
#define CP0_ENTRYLO_PFN_MASK (0x00ffffff << CP0_ENTRYLO_CSHIFT)
/* Register Number: 4 Sel: 0 Name: Context
* Function: Pointer to page table entry in memory
* Compliance Level: Required for TLB-based MMUs; Optional otherwise.
*/
#define CP0_CONTEXT_BADVPN2_SHIFT (4) /* Bits 4-22: Virtual address that cause an excpetion */
#define CP0_CONTEXT_BADVPN2_MASK (0x0007ffff << CP0_CONTEXT_BADVPN2_SHIFT)
#define CP0_CONTEXT_PTEBASE_SHIFT (23) /* Bits 23-31: Page table base address */
#define CP0_CONTEXT_PTEBASE_MASK (0x000001ff << CP0_CONTEXT_PTEBASE_SHIFT)
/* Register Number: 5 Sel: 0 Name: PageMask
* Function: Control for variable page size in TLB entries.
* Compliance Level: Required for TLB-based MMUs; Optional otherwise.
*/
#define CP0_PAGEMASK_SHIFT (13) /* Bits 13-28: Page mask */
#define CP0_PAGEMASK_MASK (0xffff << CP0_PAGEMASK_SHIFT)
# define CP0_PAGEMASK_4KB (0x0000 << CP0_PAGEMASK_SHIFT)
# define CP0_PAGEMASK_16KB (0x0003 << CP0_PAGEMASK_SHIFT)
# define CP0_PAGEMASK_64KB (0x000f << CP0_PAGEMASK_SHIFT)
# define CP0_PAGEMASK_256KB (0x003f << CP0_PAGEMASK_SHIFT)
# define CP0_PAGEMASK_1MB (0x00ff << CP0_PAGEMASK_SHIFT)
# define CP0_PAGEMASK_4MB (0x03ff << CP0_PAGEMASK_SHIFT)
# define CP0_PAGEMASK_16MB (0x0fff << CP0_PAGEMASK_SHIFT)
# define CP0_PAGEMASK_64MB (0x3fff << CP0_PAGEMASK_SHIFT)
# define CP0_PAGEMASK_256MB (0xffff << CP0_PAGEMASK_SHIFT)
/* Register Number: 6 Sel: 0 Name: Wired
* Function: Controls the number of fixed (“wired”) TLB entries
* Compliance Level: Required for TLB-based MMUs; Optional otherwise.
*
* This is a 32-bit register containing the TLB wired boundary. The valid width is some
* fixed number, 'n', but the upper bits are padded so that no fields need be defined for
* this register.
*
* Register Number: 7 Sel: all (Reserved for future extensions)
*
* Register Number: 8 Sel: 0 Name: BadVAddr
* Function: Reports the address for the most recent address-related exception
* Compliance Level: Required.
*
* This register contains a 32-bit address value; No fields need be defined for this
* register.
*
* Register Number: 9 Sel: 0 Name: Count
* Function: Processor cycle count
* Compliance Level: Required.
*
* This register contains a 32-bit count value; No fields need be defined for this
* register.
*
* Register Number: 9 Sel: 6-7 (Available for implementation dependent user)
*/
/* Register Number: 10 Sel: 0 Name: EntryHi
* Function: High-order portion of the TLB entry
* Compliance Level: Required for TLB-based MMU; Optional otherwise.
*/
#define CP0_ENTRYHI_ASID_SHIFT (0) /* Bits 0-7: Address space identifier */
#define CP0_ENTRYHI_ASID_MASK (0xff << CP0_ENTRYHI_ASID_SHIFT)
#define CP0_ENTRYHI_VPN2_SHIFT (13) /* Bits 13-31: Virtual address */
#define CP0_ENTRYHI_VPN2_MASK (0x0007ffff << CP0_ENTRYHI_VPN2_SHIFT)
/* Register Number: 11 Sel: 0 Name: Compare
* Function: Timer interrupt control
* Compliance Level: Required.
*
* This register contains a 32-bit compare value; No fields need be defined for this
* register.
*
* Register Number: 11 Sel: 6-7 (Available for implementation dependent user)
*/
/* Register Number: 12 Sel: 0 Name: Status
* Function: Processor status and control
* Compliance Level: Required.
*/
#define CP0_STATUS_IE (1 << 0) /* Bit 0: Interrupt Enable */
#define CP0_STATUS_EXL (1 << 1) /* Bit 1: Exception Level */
#define CP0_STATUS_ERL (1 << 2) /* Bit 2: Error Level */
#define CP0_STATUS_KSU_SHIFT (3) /* Bits 3-4: Operating mode (with supervisor mode) */
#define CP0_STATUS_KSU_MASK (3 << CP0_STATUS_KSU_SHIFT)
# define CP0_STATUS_KSU_KERNEL (0 << CP0_STATUS_KSU_SHIFT)
# define CP0_STATUS_KSU_SUPER (1 << CP0_STATUS_KSU_SHIFT)
# define CP0_STATUS_KSU_USER (2 << CP0_STATUS_KSU_SHIFT)
#define CP0_STATUS_UM (1 << 4) /* Bit 4: Operating mode == USER (No supervisor mode) */
#define CP0_STATUS_UX (1 << 5) /* Bit 5: Enables 64-bit user address space (Not MIPS32) */
#define CP0_STATUS_SX (1 << 6) /* Bit 6: Enables 64-bit supervisor address space (Not MIPS32) */
#define CP0_STATUS_KX (1 << 7) /* Bit 7: Enables 64-bit kernel address space (Not MIPS32) */
#define CP0_STATUS_IM_SHIFT (8) /* Bits 8-15: Interrupt Mask */
#define CP0_STATUS_IM_MASK (0xff << CP0_STATUS_IM_SHIFT)
# define CP0_STATUS_IM_SWINTS (0x03 << CP0_STATUS_IM_SHIFT) /* IM0-1 = Software interrupts */
# define CP0_STATUS_IM0 (0x01 << CP0_STATUS_IM_SHIFT)
# define CP0_STATUS_IM1 (0x02 << CP0_STATUS_IM_SHIFT)
# define CP0_STATUS_IM_HWINTS (0x7c << CP0_STATUS_IM_SHIFT) /* IM2-6 = Hardware interrupts */
# define CP0_STATUS_IM2 (0x04 << CP0_STATUS_IM_SHIFT)
# define CP0_STATUS_IM3 (0x08 << CP0_STATUS_IM_SHIFT)
# define CP0_STATUS_IM4 (0x10 << CP0_STATUS_IM_SHIFT)
# define CP0_STATUS_IM5 (0x20 << CP0_STATUS_IM_SHIFT)
# define CP0_STATUS_IM6 (0x40 << CP0_STATUS_IM_SHIFT)
# define CP0_STATUS_IM_TIMER (0x80 << CP0_STATUS_IM_SHIFT) /* IM7 = Hardware/Timer/Perf interrupts */
# define CP0_STATUS_IM7 (0x80 << CP0_STATUS_IM_SHIFT)
# define CP0_STATUS_IM_ALL (0xff << CP0_STATUS_IM_SHIFT)
#define CP0_STATUS_IMPL_SHIFT (16) /* Bits 16-17: Implementation dependent */
#define CP0_STATUS_IMPL_MASK (3 << CP0_STATUS_IMPL_SHIFT)
#define CP0_STATUS_NMI (1 << 19) /* Bit 19: Reset exception due to an NMI */
#define CP0_STATUS_SR (1 << 20) /* Bit 20: Reset exception due to a Soft Reset */
#define CP0_STATUS_TS (1 << 21) /* Bit 21: TLB detected match on multiple entries */
#define CP0_STATUS_BEV (1 << 22) /* Bit 22: Location of exception vectors 1->Bootstrap */
#define CP0_STATUS_PX (1 << 23) /* Bit 23: Enables 64-bit operations (Not MIPS32) */
#define CP0_STATUS_MX (1 << 24) /* Bit 24: Enables MDMX™ (Not MIPS32) */
#define CP0_STATUS_RE (1 << 25) /* Bit 25: Enable reverse-endian memory in user mode */
#define CP0_STATUS_FR (1 << 26) /* Bit 26: Controls the floating point register mode (Not MIPS32) */
#define CP0_STATUS_RP (1 << 27) /* Bit 27: Enables reduced power mode */
#define CP0_STATUS_CU0 (1 << 28) /* Bit 28: Controls access to coprocessor 0 */
#define CP0_STATUS_CU1 (1 << 29) /* Bit 29: Controls access to coprocessor 1 */
#define CP0_STATUS_CU2 (1 << 30) /* Bit 30: Controls access to coprocessor 2 */
#define CP0_STATUS_CU3 (1 << 31) /* Bit 31: Controls access to coprocessor 3 */
/* Register Number: 13 Sel: 0 Name: Cause
* Function: Cause of last general exception
* Compliance Level: Required.
*/
#define CP0_CAUSE_EXCCODE_SHIFT (2) /* Bits 2-6: Exception code */
#define CP0_CAUSE_EXCCODE_MASK (31 << CP0_CAUSE_EXCCODE_SHIFT)
# define CP0_CAUSE_EXCCODE_INT (0 << CP0_CAUSE_EXCCODE_SHIFT) /* Interrupt */
# define CP0_CAUSE_EXCCODE_TLBL (2 << CP0_CAUSE_EXCCODE_SHIFT) /* TLB exception (load or instruction fetch) */
# define CP0_CAUSE_EXCCODE_TLBS (3 << CP0_CAUSE_EXCCODE_SHIFT) /* TLB exception (store) */
# define CP0_CAUSE_EXCCODE_ADEL (4 << CP0_CAUSE_EXCCODE_SHIFT) /* Address error exception (load or instruction fetch) */
# define CP0_CAUSE_EXCCODE_ADES (5 << CP0_CAUSE_EXCCODE_SHIFT) /* Address error exception (store) */
# define CP0_CAUSE_EXCCODE_IBE (6 << CP0_CAUSE_EXCCODE_SHIFT) /* Bus error exception (instruction fetch) */
# define CP0_CAUSE_EXCCODE_DBE (7 << CP0_CAUSE_EXCCODE_SHIFT) /* Bus error exception (data reference: load or store) */
# define CP0_CAUSE_EXCCODE_SYS (8 << CP0_CAUSE_EXCCODE_SHIFT) /* Syscall exception */
# define CP0_CAUSE_EXCCODE_BP (9 << CP0_CAUSE_EXCCODE_SHIFT) /* Breakpoint exception */
# define CP0_CAUSE_EXCCODE_RI (10 << CP0_CAUSE_EXCCODE_SHIFT) /* Reserved instruction exception */
# define CP0_CAUSE_EXCCODE_CPU (11 << CP0_CAUSE_EXCCODE_SHIFT) /* Coprocessor Unusable exception */
# define CP0_CAUSE_EXCCODE_OV (12 << CP0_CAUSE_EXCCODE_SHIFT) /* Arithmetic Overflow exception */
# define CP0_CAUSE_EXCCODE_TR (13 << CP0_CAUSE_EXCCODE_SHIFT) /* Trap exception */
# define CP0_CAUSE_EXCCODE_FPE (15 << CP0_CAUSE_EXCCODE_SHIFT) /* Floating point exception */
# define CP0_CAUSE_EXCCODE_C2E (18 << CP0_CAUSE_EXCCODE_SHIFT) /* Precise Coprocessor 2 exceptions */
# define CP0_CAUSE_EXCCODE_MDMX (22 << CP0_CAUSE_EXCCODE_SHIFT) /* MDMX Unusable (MIPS64) */
# define CP0_CAUSE_EXCCODE_WATCH (23 << CP0_CAUSE_EXCCODE_SHIFT) /* WatchHi/WatchLo address */
# define CP0_CAUSE_EXCCODE_MCHECK (24 << CP0_CAUSE_EXCCODE_SHIFT) /* Machine check */
# define CP0_CAUSE_EXCCODE_CACHEERR (30 << CP0_CAUSE_EXCCODE_SHIFT) /* Cache error */
#define CP0_CAUSE_IP0 (1 << 8) /* Bit 8: Controls request for software interrupt 0 */
#define CP0_CAUSE_IP1 (1 << 9) /* Bit 9: Controls request for software interrupt 1 */
#define CP0_CAUSE_IP_SHIFT (10) /* Bits 10-15: Pending external interrupts */
#define CP0_CAUSE_IP_MASK (0x3f << CP0_CAUSE_IP_SHIFT)
# define CP0_CAUSE_IP2 (0x10 << CP0_CAUSE_IP_SHIFT) /* Hardware interrupt 0 */
# define CP0_CAUSE_IP3 (0x11 << CP0_CAUSE_IP_SHIFT) /* Hardware interrupt 1 */
# define CP0_CAUSE_IP4 (0x12 << CP0_CAUSE_IP_SHIFT) /* Hardware interrupt 2 */
# define CP0_CAUSE_IP5 (0x13 << CP0_CAUSE_IP_SHIFT) /* Hardware interrupt 3 */
# define CP0_CAUSE_IP6 (0x14 << CP0_CAUSE_IP_SHIFT) /* Hardware interrupt 4 */
# define CP0_CAUSE_IP7 (0x15 << CP0_CAUSE_IP_SHIFT) /* Hardware interrupt 5, timer or performance counter interrupt */
#define CP0_CAUSE_WP (1 << 22) /* Watch exception was deferred */
#define CP0_CAUSE_IV (1 << 23) /* Bit 23: Interrupt exception uses special interrupt vector */
#define CP0_CAUSE_CE_SHIFT (28) /* Bits 28-29: Coprocessor unit number fo Coprocessor Unusable exception */
#define CP0_CAUSE_CE_MASK (3 << CP0_CAUSE_CE_SHIFT)
#define CP0_CAUSE_BD (1 << 31) /* Bit 31: Last exception occurred in a branch delay slot */
/* Register Number: 14 Sel: 0 Name: EPC
* Function: Program counter at last exception
* Compliance Level: Required.
*
* This register contains a 32-bit address value; No fields need be defined for this
* register.
*/
/* Register Number: 15 Sel: 0 Name: PRId
* Function: Processor identification and revision
* Compliance Level: Required.
*/
#define CP0_PRID_REV_SHIFT (0) /* Bits 0-7: Revision number of the processor */
#define CP0_PRID_REV_MASK (0xff << CP0_PRID_REV_SHIFT)
#define CP0_PRID_PROCID_SHIFT (8) /* Bits 8-15: Type of processor */
#define CP0_PRID_PROCID_MASK (0xff << CP0_PRID_PROCID_SHIFT)
#define CP0_PRID_COMPANY_SHIFT (16) /* Bits 16-23: Company ID */
#define CP0_PRID_COMPANY_MASK (0xff << CP0_PRID_COMPANY_SHIFT)
#define CP0_PRID_OPTIONS_SHIFT (24) /* Bits 24-31: Company-dependent options */
#define CP0_PRID_OPTIONS_MASK (0xff << CP0_PRID_OPTIONS_SHIFT)
/* Register Number: 16 Sel: 0 Name: Config
* Function: Configuration register
* Compliance Level: Required.
*/
#define CP0_CONFIG_K0_SHIFT (0) /* Bits 0-2: KSEG0 coherency algorithm */
#define CP0_CONFIG_K0_MASK (7 << CP0_CONFIG_K0_SHIFT)
# define CP0_CONFIG_K0_UNCACHED (2 << CP0_CONFIG_K0_SHIFT)
# define CP0_CONFIG_K0_CACHEABLE (3 << CP0_CONFIG_K0_SHIFT)
#define CP0_CONFIG_MT_SHIFT (7) /* Bits 7-9: MMU Type */
#define CP0_CONFIG_MT_MASK (7 << CP0_CONFIG_MT_SHIFT)
# define CP0_CONFIG_MT_NONE (0 << CP0_CONFIG_MT_SHIFT) /* None */
# define CP0_CONFIG_MT_TLB (1 << CP0_CONFIG_MT_SHIFT) /* Standard TLB */
# define CP0_CONFIG_MT_BAT (2 << CP0_CONFIG_MT_SHIFT) /* Standard BAT */
# define CP0_CONFIG_MT_FIXED (3 << CP0_CONFIG_MT_SHIFT) /* Standard fixed mapping */
#define CP0_CONFIG_AR_SHIFT (10) /* Bits 10-12: Architecture revision level */
#define CP0_CONFIG_AR_MASK (7 << CP0_CONFIG_AR_SHIFT)
# define CP0_CONFIG_AR_REV1 (0 << CP0_CONFIG_AR_SHIFT)
# define CP0_CONFIG_AR_REV2 (1 << CP0_CONFIG_AR_SHIFT)
#define CP0_CONFIG_AT_SHIFT (13) /* Bits 13-14: Architecture type implemented by the processor */
#define CP0_CONFIG_AT_MASK (3 << CP0_CONFIG_AT_SHIFT)
# define CP0_CONFIG_AT_MIPS32 (0 << CP0_CONFIG_AT_SHIFT) /* MIPS32 */
# define CP0_CONFIG_AT_MIPS64CMP (0 << CP0_CONFIG_AT_SHIFT) /* MIPS64 with 32-bit compatibility segments */
# define CP0_CONFIG_AT_MIPS64 (1 << CP0_CONFIG_AT_SHIFT) /* MIPS64 with access to all address segments */
#define CP0_CONFIG_BE (1 << 15) /* Bit 15: Processor is running in big-endian mode */
#define CP0_CONFIG_IMPL_SHIFT (16) /* Bits 16-30: Implementation dependent */
#define CP0_CONFIG_IMPL_MASK (0x7fff << CP0_CONFIG_IMPL_SHIFT)
#define CP0_CONFIG_M (1 << 31) /* Bit 31: Config1 register is implemented at select=1 */
/* Register Number: 16 Sel: 1 Name: Config1
* Function: Configuration register 1
* Compliance Level: Required.
*/
#define CP0_CONFIG1_FP (1 << 0 FPU implemented
#define CP0_CONFIG1_EP (1 << 1 EJTAG implemented
#define CP0_CONFIG1_CA (1 << 2 Code compression (MIPS16) implemented
#define CP0_CONFIG1_WR (1 << 3 Watch registers implemented
#define CP0_CONFIG1_PC (1 << 4 Performance Counter registers implemented
#define CP0_CONFIG1_MD (1 << 5 MDMX ASE implemented (MIPS64)
#define CP0_CONFIG1_C2 (1 << 6 Coprocessor 2 implemented
#define CP0_CONFIG1_DA_SHIFT (7) /* Bits 7-9: Dcache associativity */
#define CP0_CONFIG1_DA_MASK (7 << CP0_CONFIG1_DA_SHIFT)
# define CP0_CONFIG1_DA_DIRECT (0 << CP0_CONFIG1_DA_SHIFT) /* Direct mapped */
# define CP0_CONFIG1_DA_2WAY (1 << CP0_CONFIG1_DA_SHIFT) /* 2-way */
# define CP0_CONFIG1_DA_3WAY (2 << CP0_CONFIG1_DA_SHIFT) /* 3-way */
# define CP0_CONFIG1_DA_4WAY (3 << CP0_CONFIG1_DA_SHIFT) /* 4-way */
# define CP0_CONFIG1_DA_5WAY (4 << CP0_CONFIG1_DA_SHIFT) /* 5-way */
# define CP0_CONFIG1_DA_6WAY (5 << CP0_CONFIG1_DA_SHIFT) /* 6-way */
# define CP0_CONFIG1_DA_7WAY (6 << CP0_CONFIG1_DA_SHIFT) /* 7-way */
# define CP0_CONFIG1_DA_8WAY (7 << CP0_CONFIG1_DA_SHIFT) /* 8-way */
#define CP0_CONFIG1_DL_SHIFT (10) /* Bits 10-12: Dcache line size */
#define CP0_CONFIG1_DL_MASK (7 << CP0_CONFIG1_DL_SHIFT)
# define CP0_CONFIG1_DL_NONE (0 << CP0_CONFIG1_DL_SHIFT) /* No Dcache present */
# define CP0_CONFIG1_DL_4BYTES (1 << CP0_CONFIG1_DL_SHIFT) /* 4 bytes */
# define CP0_CONFIG1_DL_8BYTES (2 << CP0_CONFIG1_DL_SHIFT) /* 8 bytes */
# define CP0_CONFIG1_DL_16BYTES (3 << CP0_CONFIG1_DL_SHIFT) /* 16 bytes */
# define CP0_CONFIG1_DL_32BYTES (4 << CP0_CONFIG1_DL_SHIFT) /* 32 bytes */
# define CP0_CONFIG1_DL_64BYTES (5 << CP0_CONFIG1_DL_SHIFT) /* 64 bytes */
# define CP0_CONFIG1_DL_128BYTES (6 << CP0_CONFIG1_DL_SHIFT) /* 128 bytes */
#define CP0_CONFIG1_DS_SHIFT (13) /* Bits 13-15: Dcache sets per way */
#define CP0_CONFIG1_DS_MASK (7 << CP0_CONFIG1_DS_SHIFT)
# define CP0_CONFIG1_DS_64SETS (0 << CP0_CONFIG1_DS_SHIFT)
# define CP0_CONFIG1_DS_128SETS (1 << CP0_CONFIG1_DS_SHIFT)
# define CP0_CONFIG1_DS_256SETS (2 << CP0_CONFIG1_DS_SHIFT)
# define CP0_CONFIG1_DS_512SETS (3 << CP0_CONFIG1_DS_SHIFT)
# define CP0_CONFIG1_DS_1024SETS (4 << CP0_CONFIG1_DS_SHIFT)
# define CP0_CONFIG1_DS_2048SETS (5 << CP0_CONFIG1_DS_SHIFT)
# define CP0_CONFIG1_DS_4096SETS (6 << CP0_CONFIG1_DS_SHIFT)
#define CP0_CONFIG1_IA_SHIFT (16) /* Bits 16-18: Icache associativity */
#define CP0_CONFIG1_IA_MASK (7 << CP0_CONFIG1_IA_SHIFT)
# define CP0_CONFIG1_IA_DIRECT (0 << CP0_CONFIG1_IA_SHIFT) /* Direct mapped */
# define CP0_CONFIG1_IA_2WAY (1 << CP0_CONFIG1_IA_SHIFT) /* 2-way */
# define CP0_CONFIG1_IA_3WAY (2 << CP0_CONFIG1_IA_SHIFT) /* 3-way */
# define CP0_CONFIG1_IA_4WAY (3 << CP0_CONFIG1_IA_SHIFT) /* 4-way */
# define CP0_CONFIG1_IA_5WAY (4 << CP0_CONFIG1_IA_SHIFT) /* 5-way */
# define CP0_CONFIG1_IA_6WAY (5 << CP0_CONFIG1_IA_SHIFT) /* 6-way */
# define CP0_CONFIG1_IA_7WAY (6 << CP0_CONFIG1_IA_SHIFT) /* 7-way */
# define CP0_CONFIG1_IA_8WAY (7 << CP0_CONFIG1_IA_SHIFT) /* 8-way */
#define CP0_CONFIG1_IL_SHIFT (19) /* Bits 19-21: Icache line size */
#define CP0_CONFIG1_IL_MASK (7 << CP0_CONFIG1_IL_SHIFT)
# define CP0_CONFIG1_IL_NONE (0 << CP0_CONFIG1_IL_SHIFT) /* No Dcache present */
# define CP0_CONFIG1_IL_4BYTES (1 << CP0_CONFIG1_IL_SHIFT) /* 4 bytes */
# define CP0_CONFIG1_IL_8BYTES (2 << CP0_CONFIG1_IL_SHIFT) /* 8 bytes */
# define CP0_CONFIG1_IL_16BYTES (3 << CP0_CONFIG1_IL_SHIFT) /* 16 bytes */
# define CP0_CONFIG1_IL_32BYTES (4 << CP0_CONFIG1_IL_SHIFT) /* 32 bytes */
# define CP0_CONFIG1_IL_64BYTES (5 << CP0_CONFIG1_IL_SHIFT) /* 64 bytes */
# define CP0_CONFIG1_IL_128BYTES (6 << CP0_CONFIG1_IL_SHIFT) /* 128 bytes */
#define CP0_CONFIG1_IS_SHIFT (22) /* Bits 22-24: Icache sets per way */
#define CP0_CONFIG1_IS_MASK (7 << CP0_CONFIG1_IS_SHIFT)
# define CP0_CONFIG1_IS_64SETS (0 << CP0_CONFIG1_IS_SHIFT)
# define CP0_CONFIG1_IS_128SETS (1 << CP0_CONFIG1_IS_SHIFT)
# define CP0_CONFIG1_IS_256SETS (2 << CP0_CONFIG1_IS_SHIFT)
# define CP0_CONFIG1_IS_512SETS (3 << CP0_CONFIG1_IS_SHIFT)
# define CP0_CONFIG1_IS_1024SETS (4 << CP0_CONFIG1_IS_SHIFT)
# define CP0_CONFIG1_IS_2048SETS (5 << CP0_CONFIG1_IS_SHIFT)
# define CP0_CONFIG1_IS_4096SETS (6 << CP0_CONFIG1_IS_SHIFT)
#define CP0_CONFIG1_MMUSIZE_SHIFT (25) /* Bits 25-30: Number of entries in the TLB minus one */
#define CP0_CONFIG1_MMUSIZE_MASK (0x3f << CP0_CONFIG1_MMUSIZE_SHIFT)
#define CP0_CONFIG1_M (1 << 31) /* Bit 31: Config2 register is present */
/* Register Number: 16 Sel: 2 Name: Config2
* Function: Configuration register 2
* Compliance Level: Optional.
*/
#define CP0_CONFIG2_TBS_SHIFT (0) /* Bits 0-30: Configuration of the level 2 and level 3 caches */
#define CP0_CONFIG2_TBS_MASK (0x7fffffff << CP0_CONFIG2_TBS_SHIFT)
#define CP0_CONFIG2_M (1 << 31) /* Bit 31: Config3 register is present */
/* Register Number: 16 Sel: 3 Name: Config3
* Function: Configuration register 3
* Compliance Level: Optional.
*/
#define CP0_CONFIG3_TL (1 << 0) /* Bit 0: Trace Logic implemented */
#define CP0_CONFIG3_SM (1 << 1) /* Bit 1: SmartMIPS™ ASE implemented */
#define CP0_CONFIG3_M (1 << 31) /* Bit 31: Config4 register is present */
/* Register Number: 16 Sel: 6-7 (Available for implementation dependent use) */
/* Register Number: 17 Sel: 0 Name: LLAddr
* Function: Load linked address
* Compliance Level: Optional.
*
* This register contains a 32-bit address value; No fields need be defined for this
* register.
*/
/* Register Number: 18 Sel: 0-n Name: WatchLo
* Function: Watchpoint address
* Compliance Level: Optional.
*/
#define CP0_WATCHLO_W (1 << 0) /* Bit 0: Exceptions are enabled for stores */
#define CP0_WATCHLO_R (1 << 1) /* Bit 0: Exceptions are enabled for loads */
#define CP0_WATCHLO_I (1 << 2) /* Bit 0: Exceptions are enabled for instructions */
#define CP0_WATCHLO_VADDR_SHIFT (3) /* Bits 3-31: Virtual address to match */
#define CP0_WATCHLO_VADDR_MASK (0x1fffffff << CP0_WATCHLO_VADDR_SHIFT)
/* Register Number: 19 Sel: 0-n Name: WatchHi
* Function: Watchpoint control
* Compliance Level: Optional.
*/
#define CP0_WATCHHI_MASK_SHIFT (3) /* Bits 3-11: Mask that qualifies the WatchLo address */
#define CP0_WATCHHI_MASK_MASK (0x1ff << CP0_WATCHHI_MASK_SHIFT)
#define CP0_WATCHHI_ASID_SHIFT (16) /* Bits 16-23: ASID value which to match that in the EntryHi register */
#define CP0_WATCHHI_ASID_MASK (0xff << CP0_WATCHHI_ASID_SHIFT)
#define CP0_WATCHHI_G (1 << 30) /* Bit 30: Any address matcing the WatchLo addr will cause an exception */
#define CP0_WATCHHI_M (1 << 31) /* Bit 30: Another pair of WatchHi/WatchLo registers at select n+1 */
/* Register Number: 20 Sel: 0 Name: XContext
* Function: in 64-bit implementations
*
* Register Number: 21 Sel: all (Reserved for future extensions)
*
* Register Number: 22 Sel: all Available for implementation dependent use)
*
* Register Number: 23 Sel: 0 Name: Debug
* Function: EJTAG Debug register
* Compliance Level: Optional, part of the EJTAG specification.
*
* Register Number: 24 Sel: 0 Name: DEPC
* Function: Program counter at last EJTAG debug exception
* Compliance Level: Optional, part of the EJTAG specification.
*
* This register contains a 32-bit address value; No fields need be defined for this
* register.
*/
/* Register Number: 25 Sel: 0-n Name: PerfCnt
* Function: Performance counter interface
* Compliance Level: Recommended.
*/
#define CP0_PERFCNT_EXL (1 << 0) /* Bit 0: Enables event counting when STATUS EXL=1 ERL=0 */
#define CP0_PERFCNT_K (1 << 1) /* Bit 1: Enables event counting in Kernel Mode (EXL=0 ERL=0) */
#define CP0_PERFCNT_S (1 << 2) /* Bit 2: Enables event counting in Supervisor Mode */
#define CP0_PERFCNT_U (1 << 3) /* Bit 3: Enables event counting in User Mode */
#define CP0_PERFCNT_IE (1 << 4) /* Bit 4: Interrupt Enable */
#define CP0_PERFCNT_EVENT_SHIFT (5) /* Bits 5-10: Event to be counted */
#define CP0_PERFCNT_EVENT_MASK (0xffff << CP0_PERFCNT_EVENT_SHIFT)
#define CP0_PERFCNT_M (1 << 31) /* Bit 31: Another pair of performance registers at n+2 and n+3 */
/* Register Number: 26 Sel: 0 Name: ErrCtl
* Function: Parity/ECC error control and status
* Compliance Level: Optional.
*
* The bit definitions within the ErrCtl register are implementation dependent.
*
* Register Number: 27 Sel: 0-3 Name: CacheErr
* Function: Cache parity error control and status
* Compliance Level: Optional.
*
* The bit definitions within the CacheErr register are implementation dependent.
*
* Register Number: 28 Sel: 0 Name: TagLo
* Function: Low-order portion of cache tag interface
* Compliance Level: Required if a cache is implemented; Optional otherwise.
*
* The bit definitions within the TagLo register are implementation dependent.
*
* Register Number: 28 Sel: 1, 3 Name: DataLo
* Function: The DataLo and DataHi registers are read-only registers that
* act as the interface to the cache data array and are intended for
* diagnostic operation only.
* Compliance Level: Optional.
*
* The bit definitions within the DataLo register are implementation dependent.
*
* Register Number: 29 Sel: 0 Name: TagHi
* Function: High-order portion of cache tag interface
* Compliance Level: Required if a cache is implemented; Optional otherwise.
*
* The bit definitions within the TagHi register are implementation dependent.
*
* Register Number: 29 Sel: 1, 3 Name: DataHi
* Function: The DataLo and DataHi registers are read-only registers that
* act as the interface to the cache data array and are intended for
* diagnostic operation only.
* Compliance Level: Optional.
*
* The bit definitions within the DataHi register are implementation dependent.
*
* Register Number: 30 Sel: 0 Name: ErrorEPC
* Function: Program counter at last error
* Compliance Level: Required.
*
* This register contains a 32-bit address value; No fields need be defined for this
* register.
*
* Register Number: 31 Sel: 0 Name: DESAVE
* Function: EJTAG debug exception save register
* Compliance Level: Optional, part of the EJTAG specification.
*
* This register contains a 32-bit address value; No fields need be defined for this
* register.
*/
/********************************************************************************************
* Public Types
********************************************************************************************/
#ifndef __ASSEMBLY__
/********************************************************************************************
* Inline Functions
********************************************************************************************/
/********************************************************************************************
* Public Function Prototypes
********************************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_MIPS_INCLUDE_MIPS32_CP0_H */
nuttx/arch/mips/include/mips32/irq.h
+516
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@@ -0,0 +1,516 @@
/****************************************************************************
* arch/mips/include/mips32/irq.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_MIPS_INCLUDE_MIPS32_IRQ_H
#define __ARCH_MIPS_INCLUDE_MIPS32_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/types.h>
/****************************************************************************
* Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* The global pointer (GP) does not need to be saved in the "normal," flat
* NuttX build. However, it would be necessary to save the GP if this is
* a KERNEL build or if NXFLAT is supported.
*/
#undef MIPS32_SAVE_GP
#if defined(CONFIG_NUTTX_KERNEL) || defined(CONFIG_NXFLAT)
# define MIPS32_SAVE_GP 1
#endif
/* Register save state structure ********************************************/
/* Co processor registers */
#define REG_MFLO_NDX 0
#define REG_MFHI_NDX 1
#define REG_EPC_NDX 2
#define REG_STATUS_NDX 3
/* General pupose registers */
/* $0: Zero register does not need to be saved */
/* $1: at_reg, assembler temporary */
#define REG_R1_NDX 4
/* $2-$3 = v0-v1: Return value registers */
#define REG_R2_NDX 5
#define REG_R3_NDX 6
/* $4-$7 = a0-a3: Argument registers */
#define REG_R4_NDX 7
#define REG_R5_NDX 8
#define REG_R6_NDX 9
#define REG_R7_NDX 10
/* $8-$15 = t0-t7: Volatile registers */
#define REG_R8_NDX 11
#define REG_R9_NDX 12
#define REG_R10_NDX 13
#define REG_R11_NDX 14
#define REG_R12_NDX 15
#define REG_R13_NDX 16
#define REG_R14_NDX 17
#define REG_R15_NDX 18
/* $16-$23 = s0-s7: Static registers */
#define REG_R16_NDX 19
#define REG_R17_NDX 20
#define REG_R18_NDX 21
#define REG_R19_NDX 22
#define REG_R20_NDX 23
#define REG_R21_NDX 24
#define REG_R22_NDX 25
#define REG_R23_NDX 26
/* $24-25 = t8-t9: More Volatile registers */
#define REG_R24_NDX 27
#define REG_R25_NDX 28
/* $26-$27 = ko-k1: Reserved for use in exeption handers. These do not need
* to be saved.
*/
/* $28 = gp: Only needs to be saved under conditions where there are
* multiple, per-thread values for the GP.
*/
#ifdef MIPS32_SAVE_GP
# define REG_R28_NDX 29
/* $29 = sp: The value of the stack pointer on return from the exception */
# define REG_R29_NDX 30
/* $30 = either s8 or fp: Depends if a frame pointer is used or not */
# define REG_R30_NDX 31
/* $31 = ra: Return address */
# define REG_R31_NDX 32
# define XCPTCONTEXT_REGS 33
#else
/* $29 = sp: The value of the stack pointer on return from the exception */
# define REG_R29_NDX 29
/* $30 = either s8 or fp: Depends if a frame pointer is used or not */
# define REG_R30_NDX 30
/* $31 = ra: Return address */
# define REG_R31_NDX 31
# define XCPTCONTEXT_REGS 32
#endif
#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
/* In assembly language, values have to be referenced as byte address
* offsets. But in C, it is more convenient to reference registers as
* register save table offsets.
*/
#ifdef __ASSEMBLY__
# define REG_MFLO (4*REG_MFLO_NDX)
# define REG_MFHI (4*REG_MFHI_NDX)
# define REG_EPC (4*REG_EPC_NDX)
# define REG_STATUS (4*REG_STATUS_NDX)
# define REG_R1 (4*REG_R1_NDX)
# define REG_R2 (4*REG_R2_NDX)
# define REG_R3 (4*REG_R3_NDX)
# define REG_R4 (4*REG_R4_NDX)
# define REG_R5 (4*REG_R5_NDX)
# define REG_R6 (4*REG_R6_NDX)
# define REG_R7 (4*REG_R7_NDX)
# define REG_R8 (4*REG_R8_NDX)
# define REG_R9 (4*REG_R9_NDX)
# define REG_R10 (4*REG_R10_NDX)
# define REG_R11 (4*REG_R11_NDX)
# define REG_R12 (4*REG_R12_NDX)
# define REG_R13 (4*REG_R13_NDX)
# define REG_R14 (4*REG_R14_NDX)
# define REG_R15 (4*REG_R15_NDX)
# define REG_R16 (4*REG_R16_NDX)
# define REG_R17 (4*REG_R17_NDX)
# define REG_R18 (4*REG_R18_NDX)
# define REG_R19 (4*REG_R19_NDX)
# define REG_R20 (4*REG_R20_NDX)
# define REG_R21 (4*REG_R21_NDX)
# define REG_R22 (4*REG_R22_NDX)
# define REG_R23 (4*REG_R23_NDX)
# define REG_R24 (4*REG_R24_NDX)
# define REG_R25 (4*REG_R25_NDX)
# ifdef MIPS32_SAVE_GP
# define REG_R28 (4*REG_R28_NDX)
# endif
# define REG_R29 (4*REG_R29_NDX)
# define REG_R30 (4*REG_R30_NDX)
# define REG_R31 (4*REG_R31_NDX)
#else
# define REG_MFLO REG_MFLO_NDX
# define REG_MFHI REG_MFHI_NDX
# define REG_EPC REG_EPC_NDX
# define REG_STATUS REG_STATUS_NDX
# define REG_R1 REG_R1_NDX
# define REG_R2 REG_R2_NDX
# define REG_R3 REG_R3_NDX
# define REG_R4 REG_R4_NDX
# define REG_R5 REG_R5_NDX
# define REG_R6 REG_R6_NDX
# define REG_R7 REG_R7_NDX
# define REG_R8 REG_R8_NDX
# define REG_R9 REG_R9_NDX
# define REG_R10 REG_R10_NDX
# define REG_R11 REG_R11_NDX
# define REG_R12 REG_R12_NDX
# define REG_R13 REG_R13_NDX
# define REG_R14 REG_R14_NDX
# define REG_R15 REG_R15_NDX
# define REG_R16 REG_R16_NDX
# define REG_R17 REG_R17_NDX
# define REG_R18 REG_R18_NDX
# define REG_R19 REG_R19_NDX
# define REG_R20 REG_R20_NDX
# define REG_R21 REG_R21_NDX
# define REG_R22 REG_R22_NDX
# define REG_R23 REG_R23_NDX
# define REG_R24 REG_R24_NDX
# define REG_R25 REG_R25_NDX
# ifdef MIPS32_SAVE_GP
# define REG_R28 REG_R28_NDX
# endif
# define REG_R29 REG_R29_NDX
# define REG_R30 REG_R30_NDX
# define REG_R31 REG_R31_NDX
#endif
/* Now define more user friendly alternative name that can be used either
* in assembly or C contexts.
*/
/* $1: at_reg, assembler temporary */
#define REG_AT REG_R1
/* $2-$3 = v0-v1: Return value registers */
#define REG_V0 REG_R2
#define REG_V1 REG_R3
/* $4-$7 = a0-a3: Argument registers */
#define REG_A0 REG_R4
#define REG_A1 REG_R5
#define REG_A2 REG_R6
#define REG_A3 REG_R7
/* $8-$15 = t0-t7: Volatile registers */
#define REG_T0 REG_R8
#define REG_T1 REG_R9
#define REG_T2 REG_R10
#define REG_T3 REG_R11
#define REG_T4 REG_R12
#define REG_T5 REG_R13
#define REG_T6 REG_R14
#define REG_T7 REG_R15
/* $16-$23 = s0-s7: Static registers */
#define REG_S0 REG_R16
#define REG_S1 REG_R17
#define REG_S2 REG_R18
#define REG_S3 REG_R19
#define REG_S4 REG_R20
#define REG_S5 REG_R21
#define REG_S6 REG_R22
#define REG_S7 REG_R23
/* $24-25 = t8-t9: More Volatile registers */
#define REG_T8 REG_R24
#define REG_T9 REG_R25
/* $28 = gp: Only needs to be saved under conditions where there are
* multiple, per-thread values for the GP.
*/
#ifdef MIPS32_SAVE_GP
# define REG_GP REG_R28
#endif
/* $29 = sp: The value of the stack pointer on return from the exception */
#define REG_SP REG_R29
/* $30 = either s8 or fp: Depends if a frame pointer is used or not */
#define REG_S8 REG_R30
#define REG_FP REG_R30
/* $31 = ra: Return address */
#define REG_RA REG_R31
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
struct xcptcontext
{
/* The following function pointer is non-NULL if there are pending signals
* to be processed.
*/
#ifndef CONFIG_DISABLE_SIGNALS
void *sigdeliver; /* Actual type is sig_deliver_t */
/* These additional register save locations are used to implement the
* signal delivery trampoline.
*/
uint32_t saved_epc; /* Trampoline PC */
uint32_t saved_status; /* Status with interrupts disabled. */
#endif
/* Register save area */
uint32_t regs[XCPTCONTEXT_REGS];
};
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Name: cp0_getstatus
*
* Description:
* Read the CP0 STATUS register
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static inline irqstate_t cp0_getstatus(void)
{
register irqstate_t status;
__asm__ __volatile__
(
"\t.set push\n"
"\t.set noat\n"
"\t mfc0 %0, $12, 0\n" /* Get CP0 status register */
"\t.set pop\n"
: "=r" (status)
:
: "memory"
);
return status;
}
/****************************************************************************
* Name: cp0_putstatus
*
* Description:
* Write the CP0 STATUS register
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static inline void cp0_putstatus(irqstate_t status)
{
__asm__ __volatile__
(
"\t.set push\n"
"\t.set noat\n"
"\t.set noreorder\n"
"\tmtc0 %0, $12, 0\n" /* Set the status to the provided value */
"\tnop\n" /* MTC0 status hazard: */
"\tnop\n" /* Recommended spacing: 3 */
"\tnop\n"
"\tnop\n" /* Plus one for good measure */
"\t.set pop\n"
:
: "r" (status)
: "memory"
);
}
/****************************************************************************
* Name: cp0_getcause
*
* Description:
* Get the CP0 CAUSE register
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static inline uint32_t cp0_getcause(void)
{
register uint32_t cause;
__asm__ __volatile__
(
"\t.set push\n"
"\t.set noat\n"
"\t mfc0 %0, $13, 0\n" /* Get CP0 cause register */
"\t.set pop\n"
: "=r" (cause)
:
: "memory"
);
return cause;
}
/****************************************************************************
* Name: cp0_putcause
*
* Description:
* Write the CP0 CAUSE register
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static inline void cp0_putcause(uint32_t cause)
{
__asm__ __volatile__
(
"\t.set push\n"
"\t.set noat\n"
"\t.set noreorder\n"
"\tmtc0 %0, $13, 0\n" /* Set the cause to the provided value */
"\t.set pop\n"
:
: "r" (cause)
: "memory"
);
}
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: irqsave
*
* Description:
* Save the current interrupt state and disable interrupts.
*
* Input Parameters:
* None
*
* Returned Value:
* Interrupt state prior to disabling interrupts.
*
****************************************************************************/
EXTERN irqstate_t irqsave(void);
/****************************************************************************
* Name: irqrestore
*
* Description:
* Restore the previous interrupt state (i.e., the one previously returned
* by irqsave())
*
* Input Parameters:
* state - The interrupt state to be restored.
*
* Returned Value:
* None
*
****************************************************************************/
EXTERN void irqrestore(irqstate_t irqtate);
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY */
#endif /* __ARCH_MIPS_INCLUDE_MIPS32_IRQ_H */
nuttx/arch/mips/include/mips32/registers.h
+146
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/****************************************************************************
* arch/mips/include/mips32/registers.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_MIPS_INCLUDE_MIPS32_REGISTERS_H
#define __ARCH_MIPS_INCLUDE_MIPS32_REGISTERS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-Processor Definitions
****************************************************************************/
/* Standard synonmyms for MIPS registers */
#ifdef __ASSEMBLY__
/* Zero register: Always returns 0 */
#define zero $0
/* Assembler temporary register: Reserved for use by the assembler */
#define at_reg $1
/* Return value registers: Value returned by function */
#define v0 $2
#define v1 $3
/* Argument registers: First four parameters to a function */
#define a0 $4
#define a1 $5
#define a2 $6
#define a3 $7
/* Volatile registers: Registers that can be used without saving */
#define t0 $8
#define t1 $9
#define t2 $10
#define t3 $11
#define t4 $12
#define t5 $13
#define t6 $14
#define t7 $15
#define t8 $24
#define t9 $25
/* Static registers: Registers that must be saved and restored if used */
#define s0 $16
#define s1 $17
#define s2 $18
#define s3 $19
#define s4 $20
#define s5 $21
#define s6 $22
#define s7 $23
/* Reserved for use by interrupt/trap handling logic */
#define k0 $26
#define k1 $27
/* Global pointer register */
#define gp $28
/* Stack pointer register: Stack pointer */
#define sp $29
/* Register 30 may be either an additional static register or a frame pointer */
#define s8 $30
#define fp $30
/* Return address register: Contains the function return address */
#define ra $31
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_MIPS_INCLUDE_MIPS32_REGISTERS_H */
nuttx/arch/mips/include/mips32/syscall.h
+244
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/****************************************************************************
* arch/mips/include/mips32/syscall.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through include/syscall.h or include/sys/sycall.h
*/
#ifndef __ARCH_MIPS_INCLUDE_MIPS32_SYSCALL_H
#define __ARCH_MIPS_INCLUDE_MIPS32_SYSCALL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
/****************************************************************************
* Pro-processor Definitions
****************************************************************************/
#define SYS_syscall 0x00
/* Configuration ********************************************************************/
/* This logic uses three system calls {0,1,2} for context switching. The first three
* syscall values must be reserved.
*/
#ifdef CONFIG_NUTTX_KERNEL
# ifndef CONFIG_SYS_RESERVED
# error "CONFIG_SYS_RESERVED must be defined to the value 2"
# elif CONFIG_SYS_RESERVED != 2
# error "CONFIG_SYS_RESERVED must have the value 2"
# endif
#endif
/* sys_call macros ******************************************************************/
/* System calls with 3 parameters and fewer are handled by sys_call0 (sys_call1,
* sys_call2, and sys_call3 are aliases for sys_call0). This is because the
* parmeters are passed in a0-a3. a0 is reserved for the syscall number leaving
* up to thre additional parameters that can be passed in registers. The remainder
* would have to be pushed onto the stack.
*
* Instead, these macros are provided which handle parameters four, five and six in
* a non-standard way: The use s0 ($7), s1 ($8), and s2 ($9) to pass the additional
* parameters.
*/
#ifndef __ASSEMBLY__
/* System call SYS_ argument and four additional parameters. */
#define sys_call4(nbr,parm1,parm2,parm3,parm4) __extension__({ \
uintptr_t __result; \
__asm__ __volatile__ (\
"\tmove $4, %0\n" \
"\tmove $5, %1\n" \
"\tmove $6, %2\n" \
"\tmove $7, %3\n" \
"\tmove $8, %4\n" \
"\la $12, sys_call3\n" \
"\jalr $12, $31\n" \
"\tmove %5, $r2\n" \
: "=r" (nbr) "=r" (parm1) "=r" (parm2) "=r" (parm3) "=r" (parm4) \
: " "r"(__result)\
: "memory"\
); \
__result; \
})
/* System call SYS_ argument and five additional parameters. */
#define sys_call5(nbr,parm1,parm2,parm3,parm4,parm5) __extension__({ \
uintptr_t __result; \
__asm__ __volatile__ (\
"\tmove $4, %0\n" \
"\tmove $5, %1\n" \
"\tmove $6, %2\n" \
"\tmove $7, %3\n" \
"\tmove $8, %4\n" \
"\tmove $9, %5\n" \
"\la $12, sys_call3\n" \
"\jalr $12, $31\n" \
"\tmove %6, $r2\n" \
: "=r" (nbr) "=r" (parm1) "=r" (parm2) "=r" (parm3) "=r" (parm4) "=r" (parm5) \
: " "r"(__result)\
: "memory"\
); \
__result; \
})
/* System call SYS_ argument and six additional parameters. */
#define sys_call5(nbr,parm1,parm2,parm3,parm4,parm5,parm6) __extension__({ \
uintptr_t __result; \
__asm__ __volatile__ (\
"\tmove $4, %0\n" \
"\tmove $5, %1\n" \
"\tmove $6, %2\n" \
"\tmove $7, %3\n" \
"\tmove $8, %4\n" \
"\tmove $9, %5\n" \
"\tmove $10, %5\n" \
"\la $12, sys_call3\n" \
"\jalr $12, $31\n" \
"\tmove %6, $r2\n" \
: "=r" (nbr) "=r" (parm1) "=r" (parm2) "=r" (parm3) "=r" (parm4) "=r" (parm5) \
: " "r"(__result)\
: "memory"\
); \
__result; \
})
/* Context switching system calls ***************************************************/
/* SYS call 1:
*
* void up_fullcontextrestore(uint32_t *restoreregs) __attribute__ ((noreturn));
*/
#define SYS_restore_context (1)
#define up_fullcontextrestore(restoreregs) \
(void)sys_call1(SYS_restore_context, (uintptr_t)restoreregs)
/* SYS call 2:
*
* void up_switchcontext(uint32_t *saveregs, uint32_t *restoreregs);
*/
#define SYS_switch_context (2)
#define up_switchcontext(saveregs, restoreregs) \
(void)sys_call2(SYS_switch_context, (uintptr_t)saveregs, (uintptr_t)restoreregs)
#endif /* __ASSEMBLY__ */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: up_syscall0
*
* Description:
* System call SYS_ argument and no additional parameters.
*
****************************************************************************/
EXTERN uintptr_t sys_call0(unsigned int nbr);
/****************************************************************************
* Name: up_syscall1
*
* Description:
* System call SYS_ argument and one additional parameter.
*
****************************************************************************/
EXTERN uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1);
/****************************************************************************
* Name: up_syscall2
*
* Description:
* System call SYS_ argument and two additional parameters.
*
****************************************************************************/
EXTERN uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1, uintptr_t parm2);
/****************************************************************************
* Name: up_syscall3
*
* Description:
* System call SYS_ argument and three additional parameters.
*
****************************************************************************/
EXTERN uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1,
uintptr_t parm2, uintptr_t parm3);
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_MIPS_INCLUDE_MIPS32_SYSCALL_H */
nuttx/arch/mips/include/pic32mx/chip.h
+2430
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nuttx/arch/mips/include/pic32mx/cp0.h
+396
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/****************************************************************************
* arch/mips/include/pic32mx/cp0.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_MIPS_INCLUDE_PIC32MX_CP0_H
#define __ARCH_MIPS_INCLUDE_PIC32MX_CP0_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/mips32/cp0.h>
/****************************************************************************
* Pre-Processor Definitions
****************************************************************************/
/* CP0 Register Addresses ***************************************************/
#ifdef __ASSEMBLY__
# define PIC32MX_CP0_HWRENA $7,0 /* Enables access via RDHWR hardware registers */
# define PIC32MX_CP0_BADVADDR $8,0 /* Address of most recent exception */
# define PIC32MX_CP0_COUNT $9,0 /* Processor cycle count */
# define PIC32MX_CP0_COMPARE $11,0 /* Timer interrupt control */
# define PIC32MX_CP0_STATUS $12,0 /* Processor status and control */
# define PIC32MX_CP0_INTCTL $12,1 /* Interrupt system status and control */
# define PIC32MX_CP0_SRSCTL $12,2 /* Shadow register set status and control */
# define PIC32MX_CP0_SRSMAP $12,3 /* Maps from vectored interrupt to a shadow set */
# define PIC32MX_CP0_CAUSE $13,0 /* Cause of last general exception */
# define PIC32MX_CP0_EPC $14,0 /* Program counter at last exception */
# define PIC32MX_CP0_PRID $15,0 /* Processor identification and revision */
# define PIC32MX_CP0_EBASE $15,1 /* Exception vector base register */
# define PIC32MX_CP0_CONFIG $16,0 /* Configuration register */
# define PIC32MX_CP0_CONFIG1 $16,1 /* Configuration register 1 */
# define PIC32MX_CP0_CONFIG2 $16,2 /* Configuration register 3 */
# define PIC32MX_CP0_CONFIG3 $16,3 /* Configuration register 3 */
# define PIC32MX_CP0_DEBUG $23,3 /* Debug control and exception status */
# define PIC32MX_CP0_DEPC $24,3 /* Program counter at last debug exception */
# define PIC32MX_CP0_ERREPC $30,3 /* Program counter at last error */
# define PIC32MX_CP0_DESAVE $31,3 /* Debug handler scratchpad register */
#endif
/* CP0 Registers ************************************************************/
/* Register Number: 0-6: Reserved
* Compliance Level: Required for TLB-based MMU; Optional otherwise.
*/
/* Register Number: 7 Sel: 0 Name: HWREna
* Function: Enables access via the RDHWR instruction to selected hardware
* registers in non-privileged mode.
* Compliance Level: (Reserved for future extensions)
*/
#define CP0_HWRENA_SHIFT (0) /* Bits 0-3: Enable access to a hardware resource */
#define CP0_HWRENA_MASK (15 << CP0_HWRENA_SHIFT)
# define CP0_HWRENA_BIT0 (1 << CP0_HWRENA_SHIFT)
# define CP0_HWRENA_BIT1 (2 << CP0_HWRENA_SHIFT)
# define CP0_HWRENA_BIT2 (4 << CP0_HWRENA_SHIFT)
# define CP0_HWRENA_BIT3 (8 << CP0_HWRENA_SHIFT)
/* Register Number: 8 Sel: 0 Name: BadVAddr
* Function: Reports the address for the most recent address-related
* exception
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
*
* Register Number: 9 Sel: 0 Name: Count
* Function: Processor cycle count
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
*
* Register Number: 10 Reserved.
* Compliance Level: Required for TLB-based MMU; Optional otherwise.
*
* Register Number: 11 Sel: 0 Name: Compare
* Function: Timer interrupt control
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
*/
/* Register Number: 12 Sel: 0 Name: Status
* Function: Processor status and control
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
* NOTES:
* 1. The following are reserved bits in the PIC32:
* CP0_STATUS_UX Bit 5: Enables 64-bit user address space (Not MIPS32)
* CP0_STATUS_SX Bit 6: Enables 64-bit supervisor address space (Not MIPS32)
* CP0_STATUS_KX Bit 7: Enables 64-bit kernel address space (Not MIPS32)
* CP0_STATUS_IMPL Bits 16-17: Implementation dependent
* CP0_STATUS_TS Bit 21: TLB detected match on multiple entries
* CP0_STATUS_PX Bit 23: Enables 64-bit operations (Not MIPS32)
* CP0_STATUS_MX Bit 24: Enables MDMX™ (Not MIPS32)
*/
#undef CP0_STATUS_UX
#undef CP0_STATUS_SX
#undef CP0_STATUS_KX
#undef CP0_STATUS_IMPL
#undef CP0_STATUS_IMPL_SHIFT
#undef CP0_STATUS_IMPL_MASK
#undef CP0_STATUS_TS
#undef CP0_STATUS_PX
#undef CP0_STATUS_MX
/* 2. The following field is of a different width. Apparently, it
* excludes the software interrupt bits.
*
* CP0_STATUS_IM Bits 8-15: Interrupt Mask
* Vs.
* CP0_STATUS_IPL Bits 10-15: Interrupt priority level
* Bitss 8-9 reserved
*/
#define CP0_STATUS_IPL_SHIFT (10) /* Bits 10-15: Interrupt priority level */
#define CP0_STATUS_IPL_MASK (0x3f << CP0_STATUS_IPL_SHIFT)
/* 3. Supervisor mode not supported
* CP0_STATUS_KSU Bits 3-4: Operating mode (with supervisor mode)
*/
#undef CP0_STATUS_KSU_SHIFT
#undef CP0_STATUS_KSU_MASK
#undef CP0_STATUS_KSU_KERNEL
#undef CP0_STATUS_KSU_SUPER
#undef CP0_STATUS_KSU_USER
/* Register Number: 12 Sel: 1 Name: IntCtl */
#define CP0_INTCTL_VS_SHIFT (5) /* Bits 5-9: Vector spacing bits */
#define CP0_INTCTL_VS_MASK (0x1f << CP0_INTCTL_VS_SHIFT)
# define CP0_INTCTL_VS_0BYTES (0x00 << CP0_INTCTL_VS_SHIFT)
# define CP0_INTCTL_VS_32BYTES (0x01 << CP0_INTCTL_VS_SHIFT)
# define CP0_INTCTL_VS_64BYTES (0x02 << CP0_INTCTL_VS_SHIFT)
# define CP0_INTCTL_VS_128BYTES (0x04 << CP0_INTCTL_VS_SHIFT)
# define CP0_INTCTL_VS_256BYTES (0x08 << CP0_INTCTL_VS_SHIFT)
# define CP0_INTCTL_VS_512BYTES (0x10 << CP0_INTCTL_VS_SHIFT)
/* Register Number: 12 Sel: 2 Name: SRSCtl */
#define CP0_SRSCTL_CSS_SHIFT (0) /* Bits 0-3: Current shadow bit set */
#define CP0_SRSCTL_CSS_MASK (15 << CP0_SRSCTL_CSS_SHIFT)
#define CP0_SRSCTL_PSS_SHIFT (6) /* Bits 6-9: Previous shadow set */
#define CP0_SRSCTL_PSS_MASK (15 << CP0_SRSCTL_PSS_SHIFT)
#define CP0_SRSCTL_ESS_SHIFT (12) /* Bits 12-15: Exception shadow sets */
#define CP0_SRSCTL_ESS_MASK (15 << CP0_SRSCTL_ESS_SHIFT)
#define CP0_SRSCTL_EICSS_SHIFT (18) /* Bits 18-21: External interrupt controller shadow sets */
#define CP0_SRSCTL_EICSS_MASK (15 << CP0_SRSCTL_EICSS_SHIFT)
#define CP0_SRSCTL_HSS_SHIFT (26) /* Bits 26-29: High shadow sets */
#define CP0_SRSCTL_HSS_MASK (15 << CP0_SRSCTL_HSS_SHIFT)
# define CP0_SRSCTL_HSS_1SET (0 << CP0_SRSCTL_HSS_SHIFT) /* One shadow set (normal GPR set) */
# define CP0_SRSCTL_HSS_2SETS (1 << CP0_SRSCTL_HSS_SHIFT) /* Two shadow sets */
# define CP0_SRSCTL_HSS_4SETS (3 << CP0_SRSCTL_HSS_SHIFT) /* Four shadow sets */
/* Register Number: 12 Sel: 3 Name: SRSMap */
#define CP0_SRSMAP_SSV0_SHIFT (0) /* Bits 0-3: Shadow set vector 0 */
#define CP0_SRSMAP_SSV0_MASK (15 << CP0_SRSMAP_SSV0_SHIFT)
#define CP0_SRSMAP_SSV1_SHIFT (4) /* Bits 4-7: Shadow set vector 1 */
#define CP0_SRSMAP_SSV1_MASK (15 << CP0_SRSMAP_SSV1_SHIFT)
#define CP0_SRSMAP_SSV2_SHIFT (8) /* Bits 8-11: Shadow set vector 2 */
#define CP0_SRSMAP_SSV2_MASK (15 << CP0_SRSMAP_SSV2_SHIFT)
#define CP0_SRSMAP_SSV3_SHIFT (12) /* Bits 12-15: Shadow set vector 3 */
#define CP0_SRSMAP_SSV3_MASK (15 << CP0_SRSMAP_SSV3_SHIFT)
#define CP0_SRSMAP_SSV4_SHIFT (16) /* Bits 16-19: Shadow set vector 4 */
#define CP0_SRSMAP_SSV4_MASK (15 << CP0_SRSMAP_SSV4_SHIFT)
#define CP0_SRSMAP_SSV5_SHIFT (20) /* Bits 20-23: Shadow set vector 5 */
#define CP0_SRSMAP_SSV5_MASK (15 << CP0_SRSMAP_SSV5_SHIFT)
#define CP0_SRSMAP_SSV6_SHIFT (24) /* Bits 24-27: Shadow set vector 6 */
#define CP0_SRSMAP_SSV6_MASK (15 << CP0_SRSMAP_SSV6_SHIFT)
#define CP0_SRSMAP_SSV7_SHIFT (28) /* Bits 28-31: Shadow set vector 7 */
#define CP0_SRSMAP_SSV7_MASK (15 << CP0_SRSMAP_SSV7_SHIFT)
/* Register Number: 13 Sel: 0 Name: Cause
* Function: Cause of last general exception
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
* NOTES: The following bits are added in the PIC32:
*/
#define CP0_CAUSE_R (1 << 26) /* Bit 26: R bit */
#define CP0_CAUSE_DC (1 << 27) /* Bit 27: Disable count */
#define CP0_CAUSE_TI (1 << 30) /* Bit 30: Timer interrupt bit *.
/* Register Number: 14 Sel: 0 Name: EPC
* Function: Program counter at last exception
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
*/
/* Register Number: 15 Sel: 0 Name: PRId
* Function: Processor identification and revision
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
* NOTE: Slightly different bit interpretations of some fields:
*/
#define CP0_PRID_PATCH_SHIFT (5) /* Bits 0-1: Patch level */
#define CP0_PRID_PATCH_MASK (3 << CP0_PRID_PATCH_SHIFT)
#define CP0_PRID_MINOR_SHIFT (2) /* Bits 2-4: Minor revision number */
#define CP0_PRID_MINOR_MASK (7 << CP0_PRID_MINOR_SHIFT)
#define CP0_PRID_MAJOR_SHIFT (5) /* Bits 5-7: Major revision number */
#define CP0_PRID_MAJOR_MASK (7 << CP0_PRID_MAJOR_SHIFT)
#undef CP0_PRID_OPTIONS_SHIFT
#undef CP0_PRID_OPTIONS_MASK
/* Register Number: 15 Sel: 1 Name: EBASE */
#define CP_EBASE_CPUNUM_SHIFT (0) /* Bits 0-9: CPU number */
#define CP_EBASE_CPUNUM_MASK (0x3ff << CP_EBASE_CPUNUM_SHIFT)
#define CP_EBASE_SHIFT (12) /* Bits 30-31=10, Bits 12-29: Exception base */
#define CP_EBASE_MASK (0x3ffff << CP_EBASE_SHIFT)
/* Register Number: 16 Sel: 0 Name: Config
* Function: Configuration register
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
* 1. PIC32MX is always little-endian.
* 2. Implementation specific bits defined.
*/
#undef CP0_CONFIG_IMPL_SHIFT
#undef CP0_CONFIG_IMPL_MASK
#define CP0_CONFIG_K23_SHIFT (0) /* Bits 28-30: KSEG2 and KSEG3 cacheability */
#define CP0_CONFIG_K23_MASK (7 << CP0_CONFIG_K23_SHIFT)
# define CP0_CONFIG_K23_UNCACHED (2 << CP0_CONFIG_K23_SHIFT)
# define CP0_CONFIG_K23_CACHEABLE (3 << CP0_CONFIG_K23_SHIFT)
#define CP0_CONFIG_KU_SHIFT (0) /* Bits 0-2: KUSEG and USEG cacheability */
#define CP0_CONFIG_KU_MASK (7 << CP0_CONFIG_KU_SHIFT)
# define CP0_CONFIG_KU_UNCACHED (2 << CP0_CONFIG_KU_SHIFT)
# define CP0_CONFIG_KU_CACHEABLE (3 << CP0_CONFIG_KU_SHIFT)
#define CP0_CONFIG_UDI (1 << 22) /* Bit 22: User defined bit */
#define CP0_CONFIG_SB (1 << 21) /* Bit 32: Simple BE bus mode bit */
#define CP0_CONFIG_MDU (1 << 20) /* Multipley/Divide unit bit */
#define CP0_CONFIG_DS (1 << 16) /* Dual SRAM bit */
/* Register Number: 16 Sel: 1 Name: Config1
* Function: Configuration register 1
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
*
* Register Number: 16 Sel: 2 Name: Config2
* Function: Configuration register 2
* Compliance Level: Optional.
*
* See arch/mips/include/mips32/cp0.h
*/
#undef CP0_CONFIG2_TBS_SHIFT
#undef CP0_CONFIG2_TBS_MASK
/* Register Number: 16 Sel: 3 Name: Config3
* Function: Configuration register 3
* Compliance Level: Optional.
*
* See arch/mips/include/mips32/cp0.h
*/
#define CP0_CONFIG3_SP (1 << 4) /* Bit 4: Support page bit */
#define CP0_CONFIG3_VINT (1 << 5) /* Bit 5: Vector interrupt bit */
#define CP0_CONFIG3_VEIC (1 << 6) /* Bit 6: External interrupt controller supported */
/* Register Number: 17-22 Reserved
* Compliance Level: Optional.
*/
/* Register Number: 23 Sel: 0 Name: Debug
* Function: EJTAG Debug register
* Compliance Level: Optional.
*/
#define CP0_DEBUG_DSS (1 << 0) /* Bit 0: Debug single-step exception */
#define CP0_DEBUG_DBP (1 << 1) /* Bit 1: Debug software breakpoint exception */
#define CP0_DEBUG_DDBL (1 << 2) /* Bit 2: Debug data break exception on load */
#define CP0_DEBUG_DDBS (1 << 3) /* Bit 3: Debug data break exception on store */
#define CP0_DEBUG_DIB (1 << 4) /* Bit 4: Debug instruction break exception */
#define CP0_DEBUG_DINT (1 << 5) /* Bit 5: Debug interrupt exception */
#define CP0_DEBUG_SST (1 << 8) /* Bit 6: Enable debug single step exception */
#define CP0_DEBUG_NOSST (1 << 9) /* Bit 7: No single step feature available */
#define CP0_DEBUG_DEXCCODE_SHIFT (10) /* Bits 10-14: Cause of latest exception in DEBUG mode */
#define CP0_DEBUG_DEXCCODE_MASK (31 << CP0_DEBUG_DEXCCODE_SHIFT)
#define CP0_DEBUG_VER_SHIFT (15) /* Bits 15-17: EJTAG version */
#define CP0_DEBUG_VER_MASK (7 << CP0_DEBUG_VER_SHIFT)
#define CP0_DEBUG_DDBLIMPR (1 << 18) /* Bit 18: Imprecise debug data break load instruction */
#define CP0_DEBUG_DDBSIMPR (1 << 19) /* Bit 19: Imprecise debug data break store instruction */
#define CP0_DEBUG_IEXI (1 << 20) /* Bit 20: Imprecise error exception inhibit */
#define CP0_DEBUG_DBUSEP (1 << 21) /* Bit 21: Data access bus error exception pending */
#define CP0_DEBUG_CACHEEP (1 << 22) /* Bit 22: Imprecise cache error exception is pending */
#define CP0_DEBUG_MCHECKP (1 << 23) /* Bit 23: Imprecise machine check exception is pending */
#define CP0_DEBUG_IBUSEP (1 << 24) /* Bit 24: Bus error exception pending */
#define CP0_DEBUG_COUNTDM (1 << 25) /* Bit 25: Count register behavior (1=running) */
#define CP0_DEBUG_HALT (1 << 26) /* Bit 26: Internal system bus clock stopped */
#define CP0_DEBUG_DOZE (1 << 27) /* Bit 27: Processor in low power mode */
#define CP0_DEBUG_LSNM (1 << 28) /* Bit 28: Load/store in DSEG goes to main memory */
#define CP0_DEBUG_NODCR (1 << 29) /* Bit 29: No DSEG preset */
#define CP0_DEBUG_DM (1 << 30) /* Bit 30: Processor is operating in DEBUG mode */
#define CP0_DEBUG_DBD (1 << 31) /* Bit 31: Last debug exception occurred in a dely slot */
/* Register Number: 23 Sel: ? Name: Debug2
* Is this documented anywhere?
*/
/* Register Number: 24 Sel: 0 Name: DEPC
* Function: Program counter at last EJTAG debug exception
* Compliance Level: Optional.
*
* See arch/mips/include/mips32/cp0.h
*
* Register Number: 25-29 Reserved
* Compliance Level: Recommended/Optional.
*
* Register Number: 30 Sel: 0 Name: ErrorEPC
* Function: Program counter at last error
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
*
* Register Number: 31 Sel: 0 Name: DeSAVE
* Function: EJTAG debug exception save register
* Compliance Level: Optional.
*
* See arch/mips/include/mips32/cp0.h
*/
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_MIPS_INCLUDE_PIC32MX_CP0_H */
nuttx/arch/mips/include/pic32mx/irq.h
+214
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/****************************************************************************
* arch/mips/include/pic32mx/irq.h
*
* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_H
#define __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <arch/pic32mx/chip.h>
#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)
# include <arch/pic32mx/irq_1xx2xx.h>
#elif defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4)
# include <arch/pic32mx/irq_3xx4xx.h>
#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
# include <arch/pic32mx/irq_5xx6xx7xx.h>
#else
# error "Unknown PIC32MX family
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Name: cp0_getintctl
*
* Description:
* Get the CP0 IntCtl register
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static inline uint32_t cp0_getintctl(void)
{
register uint32_t intctl;
__asm__ __volatile__
(
"\t.set push\n"
"\t.set noat\n"
"\t mfc0 %0, $12, 1\n" /* Get CP0 IntCtl register */
"\t.set pop\n"
: "=r" (intctl)
:
: "memory"
);
return intctl;
}
/****************************************************************************
* Name: cp0_putintctl
*
* Description:
* Write the CP0 IntCtl register
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static inline void cp0_putintctl(uint32_t intctl)
{
__asm__ __volatile__
(
"\t.set push\n"
"\t.set noat\n"
"\t.set noreorder\n"
"\tmtc0 %0, $12, 1\n" /* Set the IntCtl to the provided value */
"\t.set pop\n"
:
: "r" (intctl)
: "memory"
);
}
/****************************************************************************
* Name: cp0_getebase
*
* Description:
* Get the CP0 EBASE register
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static inline uint32_t cp0_getebase(void)
{
register uint32_t ebase;
__asm__ __volatile__
(
"\t.set push\n"
"\t.set noat\n"
"\t mfc0 %0, $15, 1\n" /* Get CP0 EBASE register */
"\t.set pop\n"
: "=r" (ebase)
:
: "memory"
);
return ebase;
}
/****************************************************************************
* Name: cp0_putebase
*
* Description:
* Write the CP0 EBASE register
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static inline void cp0_putebase(uint32_t ebase)
{
__asm__ __volatile__
(
"\t.set push\n"
"\t.set noat\n"
"\t.set noreorder\n"
"\tmtc0 %0, $15, 1\n" /* Set the EBASE to the provided value */
"\t.set pop\n"
:
: "r" (ebase)
: "memory"
);
}
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_H */
nuttx/arch/mips/include/pic32mx/irq_1xx2xx.h
+215
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/****************************************************************************
* arch/mips/include/pic32mx/irq_1xx2xx.h
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_1XX2XX_H
#define __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_1XX2XX_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Interrupt vector numbers. These should be used to attach to interrupts
* and to change interrupt priorities.
*/
#define PIC32MX_IRQ_CT 0 /* Vector: 0, Core Timer Interrupt */
#define PIC32MX_IRQ_CS0 1 /* Vector: 1, Core Software Interrupt 0 */
#define PIC32MX_IRQ_CS1 2 /* Vector: 2, Core Software Interrupt 1 */
#define PIC32MX_IRQ_INT0 3 /* Vector: 3, External Interrupt 0 */
#define PIC32MX_IRQ_T1 4 /* Vector: 4, Timer 1 */
#define PIC32MX_IRQ_IC1 5 /* Vector: 5, Input Capture 1 */
#define PIC32MX_IRQ_OC1 6 /* Vector: 6, Output Compare 1 */
#define PIC32MX_IRQ_INT1 7 /* Vector: 7, External Interrupt 1 */
#define PIC32MX_IRQ_T2 8 /* Vector: 8, Timer 2 */
#define PIC32MX_IRQ_IC2 9 /* Vector: 9, Input Capture 2 */
#define PIC32MX_IRQ_OC2 10 /* Vector: 10, Output Compare 2 */
#define PIC32MX_IRQ_INT2 11 /* Vector: 11, External Interrupt 2 */
#define PIC32MX_IRQ_T3 12 /* Vector: 12, Timer 3 */
#define PIC32MX_IRQ_IC3 13 /* Vector: 13, Input Capture 3 */
#define PIC32MX_IRQ_OC3 14 /* Vector: 14, Output Compare 3 */
#define PIC32MX_IRQ_INT3 15 /* Vector: 15, External Interrupt 3 */
#define PIC32MX_IRQ_T4 16 /* Vector: 16, Timer 4 */
#define PIC32MX_IRQ_IC4 17 /* Vector: 17, Input Capture 4 */
#define PIC32MX_IRQ_OC4 18 /* Vector: 18, Output Compare 4 */
#define PIC32MX_IRQ_INT4 19 /* Vector: 19, External Interrupt 4 */
#define PIC32MX_IRQ_T5 20 /* Vector: 20, Timer 5 */
#define PIC32MX_IRQ_IC5 21 /* Vector: 21, Input Capture 5 */
#define PIC32MX_IRQ_OC5 22 /* Vector: 22, Output Compare 5 */
#define PIC32MX_IRQ_AD1 23 /* Vector: 23, ADC1 Convert Done */
#define PIC32MX_IRQ_FSCM 24 /* Vector: 24, Fail-Safe Clock Monitor */
#define PIC32MX_IRQ_RTCC 25 /* Vector: 25, Real-Time Clock and Calendar */
#define PIC32MX_IRQ_FCE 26 /* Vector: 26, Flash Control Event */
#define PIC32MX_IRQ_CMP1 27 /* Vector: 27, Comparator 1 */
#define PIC32MX_IRQ_CMP2 28 /* Vector: 28, Comparator 2 */
#define PIC32MX_IRQ_CMP3 29 /* Vector: 29, Comparator 3 */
#define PIC32MX_IRQ_USB 30 /* Vector: 30, USB */
#define PIC32MX_IRQ_SPI1 31 /* Vector: 31, SPI1 */
#define PIC32MX_IRQ_U1 32 /* Vector: 32, UART1 */
#define PIC32MX_IRQ_I2C1 33 /* Vector: 33, I2C1 */
#define PIC32MX_IRQ_CN 34 /* Vector: 34, Input Change */
#define PIC32MX_IRQ_PMP 35 /* Vector: 35, Parallel Master Port */
#define PIC32MX_IRQ_SPI2 36 /* Vector: 36, SPI2 */
#define PIC32MX_IRQ_U2 37 /* Vector: 37, UART2 */
#define PIC32MX_IRQ_I2C2 38 /* Vector: 38, I2C2 */
#define PIC32MX_IRQ_CTMU 39 /* Vector: 39, CTMU */
#define PIC32MX_IRQ_DMA0 40 /* Vector: 40, DMA Channel 0 */
#define PIC32MX_IRQ_DMA1 41 /* Vector: 41, DMA Channel 1 */
#define PIC32MX_IRQ_DMA2 42 /* Vector: 42, DMA Channel 2 */
#define PIC32MX_IRQ_DMA3 43 /* Vector: 43, DMA Channel 3 */
#define PIC32MX_IRQ_BAD 44 /* Not a real IRQ number */
#define NR_IRQS 44
/* Interrupt numbers. These should be used for enabling and disabling
* interrupt sources. Note that there are more interrupt sources than
* interrupt vectors and interrupt priorities. An offset of 128 is
* used so that there is no overlap with the IRQ numbers and to avoid
* errors due to misuse.
*/
#define PIC32MX_IRQSRC0_FIRST (128+0)
#define PIC32MX_IRQSRC_CT (128+0) /* Vector: 0, Core Timer Interrupt */
#define PIC32MX_IRQSRC_CS0 (128+1) /* Vector: 1, Core Software Interrupt 0 */
#define PIC32MX_IRQSRC_CS1 (128+2) /* Vector: 2, Core Software Interrupt 1 */
#define PIC32MX_IRQSRC_INT0 (128+3) /* Vector: 3, External Interrupt 0 */
#define PIC32MX_IRQSRC_T1 (128+4) /* Vector: 4, Timer 1 */
#define PIC32MX_IRQSRC_IC1E (128+5) /* Vector: 5, Input Capture 1 Error */
#define PIC32MX_IRQSRC_IC1 (128+6) /* Vector: 5, Input Capture 1 */
#define PIC32MX_IRQSRC_OC1 (128+7) /* Vector: 6, Output Compare 1 */
#define PIC32MX_IRQSRC_INT1 (128+8) /* Vector: 7, External Interrupt 1 */
#define PIC32MX_IRQSRC_T2 (128+9) /* Vector: 8, Timer 2 */
#define PIC32MX_IRQSRC_IC2E (128+10) /* Vector: 9, Input Capture 2 Error */
#define PIC32MX_IRQSRC_IC2 (128+11) /* Vector: 9, Input Capture 2 */
#define PIC32MX_IRQSRC_OC2 (128+12) /* Vector: 10, Output Compare 2 */
#define PIC32MX_IRQSRC_INT2 (128+13) /* Vector: 11, External Interrupt 2 */
#define PIC32MX_IRQSRC_T3 (128+14) /* Vector: 12, Timer 3 */
#define PIC32MX_IRQSRC_IC3E (128+15) /* Vector: 13, Input Capture 3 Error */
#define PIC32MX_IRQSRC_IC3 (128+16) /* Vector: 13, Input Capture 3 */
#define PIC32MX_IRQSRC_OC3 (128+17) /* Vector: 14, Output Compare 3 */
#define PIC32MX_IRQSRC_INT3 (128+18) /* Vector: 15, External Interrupt 3 */
#define PIC32MX_IRQSRC_T4 (128+19) /* Vector: 16, Timer 4 */
#define PIC32MX_IRQSRC_IC4E (128+20) /* Vector: 17, Input Capture 4 Error */
#define PIC32MX_IRQSRC_IC4 (128+21) /* Vector: 17, Input Capture 4 */
#define PIC32MX_IRQSRC_OC4 (128+22) /* Vector: 18, Output Compare 4 */
#define PIC32MX_IRQSRC_INT4 (128+23) /* Vector: 19, External Interrupt 4 */
#define PIC32MX_IRQSRC_T5 (128+24) /* Vector: 20, Timer 5 */
#define PIC32MX_IRQSRC_IC5E (128+25) /* Vector: 21, Input Capture 5 Error */
#define PIC32MX_IRQSRC_IC5 (128+26) /* Vector: 21, Input Capture 5 */
#define PIC32MX_IRQSRC_OC5 (128+27) /* Vector: 22, Output Compare 5 */
#define PIC32MX_IRQSRC_AD1 (128+28) /* Vector: 23, ADC1 Convert Done */
#define PIC32MX_IRQSRC_FSCM (128+29) /* Vector: 24, Fail-Safe Clock Monitor */
#define PIC32MX_IRQSRC_RTCC (128+30) /* Vector: 25, Real-Time Clock and Calendar */
#define PIC32MX_IRQSRC_FCE (128+31) /* Vector: 26, Flash Control Event */
#define PIC32MX_IRQSRC0_LAST (128+31)
#define PIC32MX_IRQSRC1_FIRST (128+32)
#define PIC32MX_IRQSRC_CMP1 (128+32) /* Vector: 27, Comparator 1 Interrupt */
#define PIC32MX_IRQSRC_CMP2 (128+33) /* Vector: 28, Comparator 2 Interrupt */
#define PIC32MX_IRQSRC_CMP2 (128+34) /* Vector: 29, Comparator 3 Interrupt */
#define PIC32MX_IRQSRC_USB (128+35) /* Vector: 30, USB */
#define PIC32MX_IRQSRC_SPI1E (128+36) /* Vector: 31, SPI1 */
#define PIC32MX_IRQSRC_SPI1TX (128+37) /* Vector: 31, " " */
#define PIC32MX_IRQSRC_SPI1RX (128+38) /* Vector: 31, " " */
#define PIC32MX_IRQSRC_U1E (128+39) /* Vector: 32, UART1 */
#define PIC32MX_IRQSRC_U1RX (128+40) /* Vector: 32, " " */
#define PIC32MX_IRQSRC_U1TX (128+41) /* Vector: 32, " " */
#define PIC32MX_IRQSRC_I2C1B (128+42) /* Vector: 33, I2C1 */
#define PIC32MX_IRQSRC_I2C1S (128+43) /* Vector: 33, " " */
#define PIC32MX_IRQSRC_I2C1M (128+44) /* Vector: 33, " " */
#define PIC32MX_IRQSRC_CNA (128+45) /* Vector: 34, Input Change Interrupt */
#define PIC32MX_IRQSRC_CNB (128+46) /* Vector: 34, Input Change Interrupt */
#define PIC32MX_IRQSRC_CNC (128+47) /* Vector: 34, Input Change Interrupt */
#define PIC32MX_IRQSRC_PMP (128+48) /* Vector: 35, Parallel Master Port */
#define PIC32MX_IRQSRC_PMPE (128+49) /* Vector: 35, Parallel Master Port */
#define PIC32MX_IRQSRC_SPI2E (128+50) /* Vector: 36, SPI2 */
#define PIC32MX_IRQSRC_SPI2TX (128+51) /* Vector: 36, " " */
#define PIC32MX_IRQSRC_SPI2RX (128+52) /* Vector: 36, " " */
#define PIC32MX_IRQSRC_U2E (128+53) /* Vector: 37, UART2 */
#define PIC32MX_IRQSRC_U2RX (128+54) /* Vector: 37, " " */
#define PIC32MX_IRQSRC_U2TX (128+55) /* Vector: 37, " " */
#define PIC32MX_IRQSRC_I2C2B (128+56) /* Vector: 38, I2C2 */
#define PIC32MX_IRQSRC_I2C2S (128+57) /* Vector: 38, " " */
#define PIC32MX_IRQSRC_I2C2M (128+58) /* Vector: 38, " " */
#define PIC32MX_IRQSRC_CTMU (128+59) /* Vector: 39, CTMU */
#define PIC32MX_IRQSRC_DMA0 (128+60) /* Vector: 40, DMA Channel 0 */
#define PIC32MX_IRQSRC_DMA1 (128+61) /* Vector: 41, DMA Channel 1 */
#define PIC32MX_IRQSRC_DMA2 (128+62) /* Vector: 42, DMA Channel 2 */
#define PIC32MX_IRQSRC_DMA3 (128+63) /* Vector: 43, DMA Channel 3 */
#define PIC32MX_IRQSRC1_LAST (128+63)
#define PIC32MX_IRQSRC_FIRST PIC32MX_IRQSRC0_FIRST
#define PIC32MX_IRQSRC_LAST PIC32MX_IRQSRC1_LAST
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_1XX2XX_H */
nuttx/arch/mips/include/pic32mx/irq_3xx4xx.h
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@@ -0,0 +1,204 @@
/****************************************************************************
* arch/mips/include/pic32mx/irq_3xx4xx.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_3XX4XX_H
#define __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_3XX4XX_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Interrupt vector numbers. These should be used to attach to interrupts
* and to change interrupt priorities.
*/
#define PIC32MX_IRQ_CT 0 /* Vector: 0, Core Timer Interrupt */
#define PIC32MX_IRQ_CS0 1 /* Vector: 1, Core Software Interrupt 0 */
#define PIC32MX_IRQ_CS1 2 /* Vector: 2, Core Software Interrupt 1 */
#define PIC32MX_IRQ_INT0 3 /* Vector: 3, External Interrupt 0 */
#define PIC32MX_IRQ_T1 4 /* Vector: 4, Timer 1 */
#define PIC32MX_IRQ_IC1 5 /* Vector: 5, Input Capture 1 */
#define PIC32MX_IRQ_OC1 6 /* Vector: 6, Output Compare 1 */
#define PIC32MX_IRQ_INT1 7 /* Vector: 7, External Interrupt 1 */
#define PIC32MX_IRQ_T2 8 /* Vector: 8, Timer 2 */
#define PIC32MX_IRQ_IC2 9 /* Vector: 9, Input Capture 2 */
#define PIC32MX_IRQ_OC2 10 /* Vector: 10, Output Compare 2 */
#define PIC32MX_IRQ_INT2 11 /* Vector: 11, External Interrupt 2 */
#define PIC32MX_IRQ_T3 12 /* Vector: 12, Timer 3 */
#define PIC32MX_IRQ_IC3 13 /* Vector: 13, Input Capture 3 */
#define PIC32MX_IRQ_OC3 14 /* Vector: 14, Output Compare 3 */
#define PIC32MX_IRQ_INT3 15 /* Vector: 15, External Interrupt 3 */
#define PIC32MX_IRQ_T4 16 /* Vector: 16, Timer 4 */
#define PIC32MX_IRQ_IC4 17 /* Vector: 17, Input Capture 4 */
#define PIC32MX_IRQ_OC4 18 /* Vector: 18, Output Compare 4 */
#define PIC32MX_IRQ_INT4 19 /* Vector: 19, External Interrupt 4 */
#define PIC32MX_IRQ_T5 20 /* Vector: 20, Timer 5 */
#define PIC32MX_IRQ_IC5 21 /* Vector: 21, Input Capture 5 */
#define PIC32MX_IRQ_OC5 22 /* Vector: 22, Output Compare 5 */
#define PIC32MX_IRQ_SPI1 23 /* Vector: 23, SPI1 */
#define PIC32MX_IRQ_U1 24 /* Vector: 24, UART1 */
#define PIC32MX_IRQ_I2C1 25 /* Vector: 25, I2C1 */
#define PIC32MX_IRQ_CN 26 /* Vector: 26, Input Change Interrupt */
#define PIC32MX_IRQ_AD1 27 /* Vector: 27, ADC1 Convert Done */
#define PIC32MX_IRQ_PMP 28 /* Vector: 28, Parallel Master Port */
#define PIC32MX_IRQ_CMP1 29 /* Vector: 29, Comparator Interrupt */
#define PIC32MX_IRQ_CMP2 30 /* Vector: 30, Comparator Interrupt */
#define PIC32MX_IRQ_SPI2 31 /* Vector: 31, SPI2 */
#define PIC32MX_IRQ_U2 32 /* Vector: 32, UART2 */
#define PIC32MX_IRQ_I2C2 33 /* Vector: 33, I2C2 */
#define PIC32MX_IRQ_FSCM 34 /* Vector: 34, Fail-Safe Clock Monitor */
#define PIC32MX_IRQ_RTCC 35 /* Vector: 35, Real-Time Clock and Calendar */
#define PIC32MX_IRQ_DMA0 36 /* Vector: 36, DMA Channel 0 */
#define PIC32MX_IRQ_DMA1 37 /* Vector: 37, DMA Channel 1 */
#define PIC32MX_IRQ_DMA2 38 /* Vector: 38, DMA Channel 2 */
#define PIC32MX_IRQ_DMA3 39 /* Vector: 39, DMA Channel 3 */
/* Vectors 40-43: Not used */
#define PIC32MX_IRQ_FCE 44 /* Vector: 44, Flash Control Event */
#define PIC32MX_IRQ_USB 45 /* Vector: 45, USB */
#define PIC32MX_IRQ_BAD 46 /* Not a real IRQ number */
#define NR_IRQS 46
/* Interrupt numbers. These should be used for enabling and disabling
* interrupt sources. Note that there are more interrupt sources than
* interrupt vectors and interrupt priorities. An offset of 128 is
* used so that there is no overlap with the IRQ numbers and to avoid
* errors due to misuse.
*/
#define PIC32MX_IRQSRC0_FIRST (128+0)
#define PIC32MX_IRQSRC_CT (128+0) /* Vector: 0, Core Timer Interrupt */
#define PIC32MX_IRQSRC_CS0 (128+1) /* Vector: 1, Core Software Interrupt 0 */
#define PIC32MX_IRQSRC_CS1 (128+2) /* Vector: 2, Core Software Interrupt 1 */
#define PIC32MX_IRQSRC_INT0 (128+3) /* Vector: 3, External Interrupt 0 */
#define PIC32MX_IRQSRC_T1 (128+4) /* Vector: 4, Timer 1 */
#define PIC32MX_IRQSRC_IC1 (128+5) /* Vector: 5, Input Capture 1 */
#define PIC32MX_IRQSRC_OC1 (128+6) /* Vector: 6, Output Compare 1 */
#define PIC32MX_IRQSRC_INT1 (128+7) /* Vector: 7, External Interrupt 1 */
#define PIC32MX_IRQSRC_T2 (128+8) /* Vector: 8, Timer 2 */
#define PIC32MX_IRQSRC_IC2 (128+9) /* Vector: 9, Input Capture 2 */
#define PIC32MX_IRQSRC_OC2 (128+10) /* Vector: 10, Output Compare 2 */
#define PIC32MX_IRQSRC_INT2 (128+11) /* Vector: 11, External Interrupt 2 */
#define PIC32MX_IRQSRC_T3 (128+12) /* Vector: 12, Timer 3 */
#define PIC32MX_IRQSRC_IC3 (128+13) /* Vector: 13, Input Capture 3 */
#define PIC32MX_IRQSRC_OC3 (128+14) /* Vector: 14, Output Compare 3 */
#define PIC32MX_IRQSRC_INT3 (128+15) /* Vector: 15, External Interrupt 3 */
#define PIC32MX_IRQSRC_T4 (128+16) /* Vector: 16, Timer 4 */
#define PIC32MX_IRQSRC_IC4 (128+17) /* Vector: 17, Input Capture 4 */
#define PIC32MX_IRQSRC_OC4 (128+18) /* Vector: 18, Output Compare 4 */
#define PIC32MX_IRQSRC_INT4 (128+19) /* Vector: 19, External Interrupt 4 */
#define PIC32MX_IRQSRC_T5 (128+20) /* Vector: 20, Timer 5 */
#define PIC32MX_IRQSRC_IC5 (128+21) /* Vector: 21, Input Capture 5 */
#define PIC32MX_IRQSRC_OC5 (128+22) /* Vector: 22, Output Compare 5 */
#define PIC32MX_IRQSRC_SPI1E (128+23) /* Vector: 23, SPI1 */
#define PIC32MX_IRQSRC_SPI1TX (128+24) /* Vector: 23, " " */
#define PIC32MX_IRQSRC_SPI1RX (128+25) /* Vector: 23, " " */
#define PIC32MX_IRQSRC_U1E (128+26) /* Vector: 24, UART1 */
#define PIC32MX_IRQSRC_U1RX (128+27) /* Vector: 24, " " */
#define PIC32MX_IRQSRC_U1TX (128+28) /* Vector: 24, " " */
#define PIC32MX_IRQSRC_I2C1B (128+29) /* Vector: 25, I2C1 */
#define PIC32MX_IRQSRC_I2C1S (128+30) /* Vector: 25, " " */
#define PIC32MX_IRQSRC_I2C1M (128+31) /* Vector: 25, " " */
#define PIC32MX_IRQSRC0_LAST (128+31)
#define PIC32MX_IRQSRC1_FIRST (128+32)
#define PIC32MX_IRQSRC_CN (128+32) /* Vector: 26, Input Change Interrupt */
#define PIC32MX_IRQSRC_AD1 (128+33) /* Vector: 27, ADC1 Convert Done */
#define PIC32MX_IRQSRC_PMP (128+34) /* Vector: 28, Parallel Master Port */
#define PIC32MX_IRQSRC_CMP1 (128+35) /* Vector: 29, Comparator Interrupt */
#define PIC32MX_IRQSRC_CMP2 (128+36) /* Vector: 30, Comparator Interrupt */
#define PIC32MX_IRQSRC_SPI2E (128+37) /* Vector: 31, SPI2 */
#define PIC32MX_IRQSRC_SPI2TX (128+38) /* Vector: 31, " " */
#define PIC32MX_IRQSRC_SPI2RX (128+39) /* Vector: 31, " " */
#define PIC32MX_IRQSRC_U2E (128+40) /* Vector: 32, UART2 */
#define PIC32MX_IRQSRC_U2RX (128+41) /* Vector: 32, " " */
#define PIC32MX_IRQSRC_U2TX (128+42) /* Vector: 32, " " */
#define PIC32MX_IRQSRC_I2C2B (128+43) /* Vector: 33, I2C2 */
#define PIC32MX_IRQSRC_I2C2S (128+44) /* Vector: 33, " " */
#define PIC32MX_IRQSRC_I2C2M (128+45) /* Vector: 33, " " */
#define PIC32MX_IRQSRC_FSCM (128+46) /* Vector: 34, Fail-Safe Clock Monitor */
#define PIC32MX_IRQSRC_RTCC (128+47) /* Vector: 35, Real-Time Clock and Calendar */
#define PIC32MX_IRQSRC_DMA0 (128+48) /* Vector: 36, DMA Channel 0 */
#define PIC32MX_IRQSRC_DMA1 (128+49) /* Vector: 37, DMA Channel 1 */
#define PIC32MX_IRQSRC_DMA2 (128+50) /* Vector: 38, DMA Channel 2 */
#define PIC32MX_IRQSRC_DMA3 (128+51) /* Vector: 39, DMA Channel 3 */
#define PIC32MX_IRQSRC_FCE (128+56) /* Vector: 44, Flash Control Event */
#define PIC32MX_IRQSRC_USB (128+57) /* Vector: 45, USB */
#define PIC32MX_IRQSRC1_LAST (128+57)
#define PIC32MX_IRQSRC_FIRST PIC32MX_IRQSRC0_FIRST
#define PIC32MX_IRQSRC_LAST PIC32MX_IRQSRC1_LAST
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_3XX4XX_H */
nuttx/arch/mips/include/pic32mx/irq_5xx6xx7xx.h
+273
View File
@@ -0,0 +1,273 @@
/****************************************************************************
* arch/mips/include/pic32mx/irq_5xx6xx7xx.h
*
* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_5XX6XX7XX_H
#define __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_5XX6XX7XX_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Interrupt vector numbers. These should be used to attach to interrupts
* and to change interrupt priorities.
*/
#define PIC32MX_IRQ_CT 0 /* Vector: 0, Core Timer Interrupt */
#define PIC32MX_IRQ_CS0 1 /* Vector: 1, Core Software Interrupt 0 */
#define PIC32MX_IRQ_CS1 2 /* Vector: 2, Core Software Interrupt 1 */
#define PIC32MX_IRQ_INT0 3 /* Vector: 3, External Interrupt 0 */
#define PIC32MX_IRQ_T1 4 /* Vector: 4, Timer 1 */
#define PIC32MX_IRQ_IC1 5 /* Vector: 5, Input Capture 1 */
#define PIC32MX_IRQ_OC1 6 /* Vector: 6, Output Compare 1 */
#define PIC32MX_IRQ_INT1 7 /* Vector: 7, External Interrupt 1 */
#define PIC32MX_IRQ_T2 8 /* Vector: 8, Timer 2 */
#define PIC32MX_IRQ_IC2 9 /* Vector: 9, Input Capture 2 */
#define PIC32MX_IRQ_OC2 10 /* Vector: 10, Output Compare 2 */
#define PIC32MX_IRQ_INT2 11 /* Vector: 11, External Interrupt 2 */
#define PIC32MX_IRQ_T3 12 /* Vector: 12, Timer 3 */
#define PIC32MX_IRQ_IC3 13 /* Vector: 13, Input Capture 3 */
#define PIC32MX_IRQ_OC3 14 /* Vector: 14, Output Compare 3 */
#define PIC32MX_IRQ_INT3 15 /* Vector: 15, External Interrupt 3 */
#define PIC32MX_IRQ_T4 16 /* Vector: 16, Timer 4 */
#define PIC32MX_IRQ_IC4 17 /* Vector: 17, Input Capture 4 */
#define PIC32MX_IRQ_OC4 18 /* Vector: 18, Output Compare 4 */
#define PIC32MX_IRQ_INT4 19 /* Vector: 19, External Interrupt 4 */
#define PIC32MX_IRQ_T5 20 /* Vector: 20, Timer 5 */
#define PIC32MX_IRQ_IC5 21 /* Vector: 21, Input Capture 5 */
#define PIC32MX_IRQ_OC5 22 /* Vector: 22, Output Compare 5 */
#define PIC32MX_IRQ_SPI1 23 /* Vector: 23, SPI1 */
#define PIC32MX_IRQ_VEC24 24 /* Vector: 24, UART1, SPI3, I2C3 */
# define PIC32MX_IRQ_U1 24 /* Vector: 24, UART1 */
# define PIC32MX_IRQ_SPI3 24 /* Vector: 24, SPI3 */
# define PIC32MX_IRQ_I2C3 24 /* Vector: 24, I2C3 */
#define PIC32MX_IRQ_I2C1 25 /* Vector: 25, I2C1 */
#define PIC32MX_IRQ_CN 26 /* Vector: 26, Input Change Interrupt */
#define PIC32MX_IRQ_AD1 27 /* Vector: 27, ADC1 Convert Done */
#define PIC32MX_IRQ_PMP 28 /* Vector: 28, Parallel Master Port */
#define PIC32MX_IRQ_CMP1 29 /* Vector: 29, Comparator Interrupt */
#define PIC32MX_IRQ_CMP2 30 /* Vector: 30, Comparator Interrupt */
#define PIC32MX_IRQ_VEC31 31 /* Vector: 31, UART3, SPI2, I2C4 */
# define PIC32MX_IRQ_U3 31 /* Vector: 31, UART3 */
# define PIC32MX_IRQ_SPI2 31 /* Vector: 31, SPI2 */
# define PIC32MX_IRQ_I2C4 31 /* Vector: 31, I2C4 */
#define PIC32MX_IRQ_VEC31 32 /* Vector: 32, UART2, SPI4, I2C5 */
# define PIC32MX_IRQ_U2 32 /* Vector: 32, UART2 */
# define PIC32MX_IRQ_SPI4 32 /* Vector: 32, SPI4 */
# define PIC32MX_IRQ_I2C5 32 /* Vector: 32, I2C5 */
#define PIC32MX_IRQ_I2C2 33 /* Vector: 33, I2C2 */
#define PIC32MX_IRQ_FSCM 34 /* Vector: 34, Fail-Safe Clock Monitor */
#define PIC32MX_IRQ_RTCC 35 /* Vector: 35, Real-Time Clock and Calendar */
#define PIC32MX_IRQ_DMA0 36 /* Vector: 36, DMA Channel 0 */
#define PIC32MX_IRQ_DMA1 37 /* Vector: 37, DMA Channel 1 */
#define PIC32MX_IRQ_DMA2 38 /* Vector: 38, DMA Channel 2 */
#define PIC32MX_IRQ_DMA3 39 /* Vector: 39, DMA Channel 3 */
#define PIC32MX_IRQ_DMA4 40 /* Vector: 40, DMA Channel 3 */
#define PIC32MX_IRQ_DMA5 41 /* Vector: 41, DMA Channel 3 */
#define PIC32MX_IRQ_DMA6 42 /* Vector: 42, DMA Channel 3 */
#define PIC32MX_IRQ_DMA7 43 /* Vector: 43, DMA Channel 3 */
#define PIC32MX_IRQ_FCE 44 /* Vector: 44, Flash Control Event */
#define PIC32MX_IRQ_USB 45 /* Vector: 45, USB Interrupt */
#define PIC32MX_IRQ_CAN1 46 /* Vector: 46, Control Area Network 1 */
#define PIC32MX_IRQ_CAN2 47 /* Vector: 47, Control Area Network 2 */
#define PIC32MX_IRQ_ETH 48 /* Vector: 48, Ethernet interrupt */
#define PIC32MX_IRQ_U4 49 /* Vector: 49, UART4 */
#define PIC32MX_IRQ_U6 50 /* Vector: 50, UART6 */
#define PIC32MX_IRQ_U5 51 /* Vector: 51, UART5 */
#define PIC32MX_IRQ_BAD 52 /* Not a real IRQ number */
#define NR_IRQS 52
/* Interrupt numbers. These should be used for enabling and disabling
* interrupt sources. Note that there are more interrupt sources than
* interrupt vectors and interrupt priorities. An offset of 128 is
* used so that there is no overlap with the IRQ numbers and to avoid
* errors due to misuse.
*/
#define PIC32MX_IRQSRC0_FIRST (128+0)
#define PIC32MX_IRQSRC_CT (128+0) /* Vector: 0, Core Timer Interrupt */
#define PIC32MX_IRQSRC_CS0 (128+1) /* Vector: 1, Core Software Interrupt 0 */
#define PIC32MX_IRQSRC_CS1 (128+2) /* Vector: 2, Core Software Interrupt 1 */
#define PIC32MX_IRQSRC_INT0 (128+3) /* Vector: 3, External Interrupt 0 */
#define PIC32MX_IRQSRC_T1 (128+4) /* Vector: 4, Timer 1 */
#define PIC32MX_IRQSRC_IC1 (128+5) /* Vector: 5, Input Capture 1 */
#define PIC32MX_IRQSRC_OC1 (128+6) /* Vector: 6, Output Compare 1 */
#define PIC32MX_IRQSRC_INT1 (128+7) /* Vector: 7, External Interrupt 1 */
#define PIC32MX_IRQSRC_T2 (128+8) /* Vector: 8, Timer 2 */
#define PIC32MX_IRQSRC_IC2 (128+9) /* Vector: 9, Input Capture 2 */
#define PIC32MX_IRQSRC_OC2 (128+10) /* Vector: 10, Output Compare 2 */
#define PIC32MX_IRQSRC_INT2 (128+11) /* Vector: 11, External Interrupt 2 */
#define PIC32MX_IRQSRC_T3 (128+12) /* Vector: 12, Timer 3 */
#define PIC32MX_IRQSRC_IC3 (128+13) /* Vector: 13, Input Capture 3 */
#define PIC32MX_IRQSRC_OC3 (128+14) /* Vector: 14, Output Compare 3 */
#define PIC32MX_IRQSRC_INT3 (128+15) /* Vector: 15, External Interrupt 3 */
#define PIC32MX_IRQSRC_T4 (128+16) /* Vector: 16, Timer 4 */
#define PIC32MX_IRQSRC_IC4 (128+17) /* Vector: 17, Input Capture 4 */
#define PIC32MX_IRQSRC_OC4 (128+18) /* Vector: 18, Output Compare 4 */
#define PIC32MX_IRQSRC_INT4 (128+19) /* Vector: 19, External Interrupt 4 */
#define PIC32MX_IRQSRC_T5 (128+20) /* Vector: 20, Timer 5 */
#define PIC32MX_IRQSRC_IC5 (128+21) /* Vector: 21, Input Capture 5 */
#define PIC32MX_IRQSRC_OC5 (128+22) /* Vector: 22, Output Compare 5 */
#define PIC32MX_IRQSRC_SPI1E (128+23) /* Vector: 23, SPI1 Fault */
#define PIC32MX_IRQSRC_SPI1RX (128+24) /* Vector: 23, " " Receive done */
#define PIC32MX_IRQSRC_SPI1TX (128+25) /* Vector: 23, " " Transfer done */
#define PIC32MX_IRQSRC_26 (128+26) /* Vector: 24, UART1, SPI3, I2C3 */
# define PIC32MX_IRQSRC_U1E (128+26) /* Vector: 24, UART1 Error */
# define PIC32MX_IRQSRC_SPI3E (128+26) /* Vector: 24, SPI3 Fault */
# define PIC32MX_IRQSRC_I2C3B (128+26) /* Vector: 24, I2C3 Bus collision event */
#define PIC32MX_IRQSRC_27 (128+27) /* Vector: 24, UART1, SPI3, I2C3 */
# define PIC32MX_IRQSRC_U1RX (128+27) /* Vector: 24, UART1 Receiver */
# define PIC32MX_IRQSRC_SPI3RX (128+27) /* Vector: 24, SPI3 Receive done */
# define PIC32MX_IRQSRC_I2C3S (128+27) /* Vector: 24, I2C3 Slave event */
#define PIC32MX_IRQSRC_28 (128+27) /* Vector: 24, UART1, SPI3, I2C3 */
# define PIC32MX_IRQSRC_U1TX (128+28) /* Vector: 24, UART1 Transmitter */
# define PIC32MX_IRQSRC_SPI3TX (128+28) /* Vector: 24, SPI3 Transfer done */
# define PIC32MX_IRQSRC_I2C3M (128+28) /* Vector: 24, I2C3 Master event */
#define PIC32MX_IRQSRC_I2C1B (128+29) /* Vector: 25, I2C1 Bus collision event*/
#define PIC32MX_IRQSRC_I2C1S (128+30) /* Vector: 25, " " Slave event */
#define PIC32MX_IRQSRC_I2C1M (128+31) /* Vector: 25, " " Master event */
#define PIC32MX_IRQSRC0_LAST (128+31)
#define PIC32MX_IRQSRC1_FIRST (128+32)
#define PIC32MX_IRQSRC_CN (128+32) /* Vector: 26, Input Change Interrupt */
#define PIC32MX_IRQSRC_AD1 (128+33) /* Vector: 27, ADC1 Convert Done */
#define PIC32MX_IRQSRC_PMP (128+34) /* Vector: 28, Parallel Master Port */
#define PIC32MX_IRQSRC_CMP1 (128+35) /* Vector: 29, Comparator Interrupt */
#define PIC32MX_IRQSRC_CMP2 (128+36) /* Vector: 30, Comparator Interrupt */
#define PIC32MX_IRQSRC_37 (128+37) /* Vector: 31, UART3, SPI2, I2C4 */
# define PIC32MX_IRQSRC_U3E (128+37) /* Vector: 31, UART3 Error */
# define PIC32MX_IRQSRC_SPI2E (128+37) /* Vector: 31, SPI2 Fault */
# define PIC32MX_IRQSRC_I2C4B (128+37) /* Vector: 31, I2C4 Bus collision event */
#define PIC32MX_IRQSRC_38 (128+38) /* Vector: 31, UART3, SPI2, I2C4 */
# define PIC32MX_IRQSRC_U3RX (128+38) /* Vector: 31, UART3 Receiver */
# define PIC32MX_IRQSRC_SPI2RX (128+38) /* Vector: 31, SPI2 Receive done */
# define PIC32MX_IRQSRC_I2C4S (128+38) /* Vector: 31, I2C4 Slave event */
#define PIC32MX_IRQSRC_39 (128+39) /* Vector: 31, UART3, SPI2, I2C4 */
# define PIC32MX_IRQSRC_U3TX (128+39) /* Vector: 31, UART3 Transmitter */
# define PIC32MX_IRQSRC_SPI2TX (128+39) /* Vector: 31, SPI2 Transfer done */
# define PIC32MX_IRQSRC_I2C4M (128+39) /* Vector: 31, I2C4 Master event */
#define PIC32MX_IRQSRC_40 (128+40) /* Vector: 32, UART2, SPI4, I2C5 */
# define PIC32MX_IRQSRC_U2E (128+40) /* Vector: 32, UART2 Error */
# define PIC32MX_IRQSRC_SPI4E (128+40) /* Vector: 32, SPI4 Fault */
# define PIC32MX_IRQSRC_I2C5B (128+40) /* Vector: 32, I2C5 Bus collision event */
#define PIC32MX_IRQSRC_41 (128+41) /* Vector: 32, UART2, SPI4, I2C5 */
# define PIC32MX_IRQSRC_U2RX (128+41) /* Vector: 32, UART2 Receiver */
# define PIC32MX_IRQSRC_SPI4RX (128+41) /* Vector: 32, SPI4 Receive done */
# define PIC32MX_IRQSRC_I2C5S (128+41) /* Vector: 32, I2C5 Slave event */
#define PIC32MX_IRQSRC_42 (128+42) /* Vector: 32, UART2, SPI4, I2C5 */
# define PIC32MX_IRQSRC_U2TX (128+42) /* Vector: 32, UART2 Transmitter */
# define PIC32MX_IRQSRC_SPI4TX (128+42) /* Vector: 32, SPI4 Transfer done */
# define PIC32MX_IRQSRC_I2C5M (128+42) /* Vector: 32, I2C5 Master event */
#define PIC32MX_IRQSRC_I2C2B (128+43) /* Vector: 33, I2C2 Bus collision event */
#define PIC32MX_IRQSRC_I2C2S (128+44) /* Vector: 33, " " Slave event */
#define PIC32MX_IRQSRC_I2C2M (128+45) /* Vector: 33, " " Master event */
#define PIC32MX_IRQSRC_FSCM (128+46) /* Vector: 34, Fail-Safe Clock Monitor */
#define PIC32MX_IRQSRC_RTCC (128+47) /* Vector: 35, Real-Time Clock and Calendar */
#define PIC32MX_IRQSRC_DMA0 (128+48) /* Vector: 36, DMA Channel 0 */
#define PIC32MX_IRQSRC_DMA1 (128+49) /* Vector: 37, DMA Channel 1 */
#define PIC32MX_IRQSRC_DMA2 (128+50) /* Vector: 38, DMA Channel 2 */
#define PIC32MX_IRQSRC_DMA3 (128+51) /* Vector: 39, DMA Channel 3 */
#define PIC32MX_IRQSRC_DMA4 (128+52) /* Vector: 40, DMA Channel 3 */
#define PIC32MX_IRQSRC_DMA5 (128+53) /* Vector: 41, DMA Channel 3 */
#define PIC32MX_IRQSRC_DMA6 (128+54) /* Vector: 42, DMA Channel 3 */
#define PIC32MX_IRQSRC_DMA7 (128+55) /* Vector: 43, DMA Channel 3 */
#define PIC32MX_IRQSRC_FCE (128+56) /* Vector: 44, Flash Control Event */
#define PIC32MX_IRQSRC_USB (128+57) /* Vector: 45, USB Interrupt */
#define PIC32MX_IRQSRC_CAN1 (128+58) /* Vector: 46, Control Area Network 1 */
#define PIC32MX_IRQSRC_CAN2 (128+59) /* Vector: 47, Control Area Network 2 */
#define PIC32MX_IRQSRC_ETH (128+60) /* Vector: 48, Ethernet interrupt */
#define PIC32MX_IRQSRC_IC1E (128+61) /* Vector: 5, Input capture 1 error */
#define PIC32MX_IRQSRC_IC2E (128+62) /* Vector: 9, Input capture 1 error */
#define PIC32MX_IRQSRC_IC3E (128+63) /* Vector: 13, Input capture 1 error */
#define PIC32MX_IRQSRC1_LAST (128+63)
#define PIC32MX_IRQSRC2_FIRST (128+64)
#define PIC32MX_IRQSRC_IC4E (128+64) /* Vector: 17, Input capture 1 error */
#define PIC32MX_IRQSRC_IC5E (128+65) /* Vector: 21, Input capture 1 error */
#define PIC32MX_IRQSRC_PMPE (128+66) /* Vector: 28, Parallel master port error */
#define PIC32MX_IRQSRC_U4E (128+67) /* Vector: 49, UART4 Error */
#define PIC32MX_IRQSRC_U4RX (128+68) /* Vector: 49, UART4 Receiver */
#define PIC32MX_IRQSRC_U4TX (128+69) /* Vector: 49, UART4 Transmitter */
#define PIC32MX_IRQSRC_U6E (128+70) /* Vector: 50, UART6 Error */
#define PIC32MX_IRQSRC_U6RX (128+71) /* Vector: 50, UART6 Receiver */
#define PIC32MX_IRQSRC_U6TX (128+72) /* Vector: 50, UART6 Transmitter */
#define PIC32MX_IRQSRC_U5E (128+73) /* Vector: 51, UART5 Error */
#define PIC32MX_IRQSRC_U5RX (128+74) /* Vector: 51, UART5 Receiver */
#define PIC32MX_IRQSRC_U5TX (128+75) /* Vector: 51, UART5 Transmitter */
#define PIC32MX_IRQSRC2_LAST (128+75)
#define PIC32MX_IRQSRC_FIRST PIC32MX_IRQSRC0_FIRST
#define PIC32MX_IRQSRC_LAST PIC32MX_IRQSRC2_LAST
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_5XX6XX7XX_H */
nuttx/arch/mips/include/syscall.h
+88
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@@ -0,0 +1,88 @@
/****************************************************************************
* arch/mips/include/syscall.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through include/syscall.h or include/sys/sycall.h
*/
#ifndef __ARCH_MIPS_INCLUDE_SYSCALL_H
#define __ARCH_MIPS_INCLUDE_SYSCALL_H
/****************************************************************************
* Included Files
****************************************************************************/
/* Include ARM architecture-specific syscall macros */
#ifdef CONFIG_ARCH_MIPS32
# include <arch/mips32/syscall.h>
#endif
/****************************************************************************
* Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_MIPS_INCLUDE_SYSCALL_H */
nuttx/arch/mips/include/types.h
+95
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@@ -0,0 +1,95 @@
/****************************************************************************
* arch/mips/include/types.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through stdint.h
*/
#ifndef __ARCH_MIPS_INCLUDE_TYPES_H
#define __ARCH_MIPS_INCLUDE_TYPES_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Type Declarations
****************************************************************************/
#ifndef __ASSEMBLY__
/* These are the sizes of the standard integer types. NOTE that these type
* names have a leading underscore character. This file will be included
* (indirectly) by include/stdint.h and typedef'ed to the final name without
* the underscore character. This roundabout way of doings things allows
* the stdint.h to be removed from the include/ directory in the event that
* the user prefers to use the definitions provided by their toolchain header
* files
*/
typedef signed char _int8_t;
typedef unsigned char _uint8_t;
typedef signed short _int16_t;
typedef unsigned short _uint16_t;
typedef signed int _int32_t;
typedef unsigned int _uint32_t;
typedef signed long long _int64_t;
typedef unsigned long long _uint64_t;
#define __INT64_DEFINED
/* A pointer is 4 bytes */
typedef signed int _intptr_t;
typedef unsigned int _uintptr_t;
/* This is the size of the interrupt state save returned by irqsave(). */
typedef unsigned int irqstate_t;
#endif /* __ASSEMBLY__ */
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_MIPS_INCLUDE_TYPES_H */