From 5660ea0fd255a5a2ae292115a38738b6654dc258 Mon Sep 17 00:00:00 2001 From: Daniel Agar Date: Sat, 22 Feb 2020 01:12:38 -0500 Subject: [PATCH] av_x-v1: add board_dma_map.h and enable SPI1/SPI2 DMA --- boards/av/x-v1/nuttx-config/include/board.h | 20 +------ .../x-v1/nuttx-config/include/board_dma_map.h | 55 +++++++++++++++++++ boards/av/x-v1/nuttx-config/nsh/defconfig | 4 +- boards/av/x-v1/src/board_config.h | 2 +- 4 files changed, 60 insertions(+), 21 deletions(-) create mode 100644 boards/av/x-v1/nuttx-config/include/board_dma_map.h diff --git a/boards/av/x-v1/nuttx-config/include/board.h b/boards/av/x-v1/nuttx-config/include/board.h index 4dd5ba546c..f3a7045d0a 100644 --- a/boards/av/x-v1/nuttx-config/include/board.h +++ b/boards/av/x-v1/nuttx-config/include/board.h @@ -37,6 +37,7 @@ /************************************************************************************ * Included Files ************************************************************************************/ +#include "board_dma_map.h" #include @@ -242,20 +243,6 @@ # define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) #endif -/* DMA Channl/Stream Selections *****************************************************/ -/* Stream selections are arbitrary for now but might become important in the future - * if we set aside more DMA channels/streams. - * - * SDMMC DMA is on DMA2 - * - * SDMMC1 DMA - * DMAMAP_SDMMC1_1 = Channel 4, Stream 3 <- may later be used by SPI DMA - * DMAMAP_SDMMC1_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDMMC1 DMAMAP_SDMMC1_1 - - /* FLASH wait states * * --------- ---------- ----------- @@ -300,11 +287,6 @@ * GPIO_UART8_TX PE1 */ -/* UART RX DMA configurations */ - -#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 -#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 - /* CAN * * CAN1 is routed to transceiver. diff --git a/boards/av/x-v1/nuttx-config/include/board_dma_map.h b/boards/av/x-v1/nuttx-config/include/board_dma_map.h new file mode 100644 index 0000000000..6b6c8dff01 --- /dev/null +++ b/boards/av/x-v1/nuttx-config/include/board_dma_map.h @@ -0,0 +1,55 @@ +/**************************************************************************** + * + * Copyright (c) 2020 PX4 Development Team. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name PX4 nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#pragma once + + +// DMA1 Channel/Stream Selections +//--------------------------------------------//---------------------------//---------------- +// DMAMAP_UART5_RX // DMA1, Stream 0, Channel 4 +// DMAMAP_USART3_RX // DMA1, Stream 1, Channel 4 +// AVAILABLE // DMA1, Stream 2, Channel 4 +#define DMAMAP_SPI2_RX DMAMAP_SPI2_RX_2 // DMA1, Stream 3, Channel 0 (SPI2 RX) +#define DMAMAP_SPI2_TX DMAMAP_SPI2_TX_2 // DMA1, Stream 4, Channel 0 (SPI2 TX) +// DMAMAP_USART2_RX // DMA1, Stream 5, Channel 4 +// DMAMAP_UART8_RX // DMA1, Stream 6, Channel 5 (CONSOLE) + +// DMA2 Channel/Stream Selections +//--------------------------------------------//---------------------------//---------------- +#define DMAMAP_SPI1_RX DMAMAP_SPI1_RX_1 // DMA2, Stream 0, Channel 3 (SPI1 RX) +// AVAILABLE // DMA2, Stream 1 +#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 // DMA2, Stream 2, Channel 5 +#define DMAMAP_SPI1_TX DMAMAP_SPI1_TX_1 // DMA2, Stream 3, Channel 3 (SPI1 TX) +// AVAILABLE // DMA2, Stream 4 +#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 // DMA2, Stream 5, Channel 4 +#define DMAMAP_SDMMC1 DMAMAP_SDMMC1_2 // DMA2, Stream 6, Channel 4 diff --git a/boards/av/x-v1/nuttx-config/nsh/defconfig b/boards/av/x-v1/nuttx-config/nsh/defconfig index a55147624d..bd25b60c24 100644 --- a/boards/av/x-v1/nuttx-config/nsh/defconfig +++ b/boards/av/x-v1/nuttx-config/nsh/defconfig @@ -210,9 +210,12 @@ CONFIG_STM32F7_SDMMC_DMA=y CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y CONFIG_STM32F7_SPI1=y +CONFIG_STM32F7_SPI1_DMA=y CONFIG_STM32F7_SPI2=y +CONFIG_STM32F7_SPI2_DMA=y CONFIG_STM32F7_SPI4=y CONFIG_STM32F7_SPI5=y +CONFIG_STM32F7_SPI_DMA=y CONFIG_STM32F7_TIM14=y CONFIG_STM32F7_TIM3=y CONFIG_STM32F7_UART4=y @@ -242,7 +245,6 @@ CONFIG_UART5_RXDMA=y CONFIG_UART5_TXBUFSIZE=1500 CONFIG_UART7_BAUD=57600 CONFIG_UART7_RXBUFSIZE=600 -CONFIG_UART7_RXDMA=y CONFIG_UART7_TXBUFSIZE=1500 CONFIG_UART8_BAUD=57600 CONFIG_UART8_RXBUFSIZE=600 diff --git a/boards/av/x-v1/src/board_config.h b/boards/av/x-v1/src/board_config.h index c21013d726..385930c2a0 100644 --- a/boards/av/x-v1/src/board_config.h +++ b/boards/av/x-v1/src/board_config.h @@ -236,7 +236,7 @@ /* This board provides a DMA pool and APIs */ -#define BOARD_DMA_ALLOC_POOL_SIZE 5120 +#define BOARD_DMA_ALLOC_POOL_SIZE (5120 + 512 + 512) // 5120 fat + 512 + 512 spi /* This board provides the board_on_reset interface */