mirror of
https://gitee.com/mirrors_PX4/PX4-Autopilot.git
synced 2026-11-06 05:21:36 +08:00
Add option to use BASEPRI instead of PRIMASK to disable interrupts in all ARMv7-M architectures
git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5546 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
@@ -93,17 +93,16 @@
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int up_hardfault(int irq, FAR void *context)
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{
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uint32_t *regs = (uint32_t*)context;
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uint16_t *pc;
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uint16_t insn;
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/* Get the value of the program counter where the fault occurred */
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pc = (uint16_t*)regs[REG_PC] - 1;
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#ifndef CONFIG_ARMV7M_USEBASEPRI
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uint16_t *pc = (uint16_t*)regs[REG_PC] - 1;
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if ((void*)pc >= (void*)&_stext && (void*)pc < (void*)&_etext)
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{
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/* Fetch the instruction that caused the Hard fault */
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insn = *pc;
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uint16_t insn = *pc;
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hfdbg(" PC: %p INSN: %04x\n", pc, insn);
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/* If this was the instruction 'svc 0', then forward processing
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@@ -116,6 +115,7 @@ int up_hardfault(int irq, FAR void *context)
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return up_svcall(irq, context);
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}
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}
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#endif
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/* Dump some hard fault info */
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@@ -42,802 +42,17 @@
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#include <nuttx/config.h>
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/* Include the memory map and the chip definitions file. Other chip hardware files
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* should then include this file for the proper setup.
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*/
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#include <arch/kinetis/chip.h>
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#include "kinetis_memorymap.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Get customizations for each supported chip */
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#if defined(CONFIG_ARCH_CHIP_MK40X64VFX50) || defined(CONFIG_ARCH_CHIP_MK40X64VLH50) || \
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defined(CONFIG_ARCH_CHIP_MK40X64VLK50) || defined(CONFIG_ARCH_CHIP_MK40X64VMB50)
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# define KINETIS_K40 1 /* Kinetics K40 family */
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# undef KINETIS_K60 /* Not Kinetis K60 family */
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# define KINETIS_FLASH_SIZE (64*1024) /* 64Kb */
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# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */
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# define KINETIS_SRAM_SIZE (16*1024) /* 16Kb */
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# undef KINETIS_MPU /* No memory protection unit */
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# undef KINETIS_EXTBUS /* No external bus interface */
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# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
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# undef KINETIS_NENET /* No Ethernet controller */
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# define KINETIS_NUSBHOST 1 /* One USB host controller */
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# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
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# define KINETIS_NUSBDEV 1 /* One USB device controller */
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# undef KINETIS_NSDHC /* No SD host controller */
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# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */
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# define KINETIS_NI2C 2 /* Two I2C modules */
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# undef KINETIS_NISO7816 /* No UART with ISO-786 */
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# define KINETIS_NUART 6 /* Six UARTs */
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# define KINETIS_NSPI 3 /* Three SPI modules */
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# if defined(CONFIG_ARCH_CHIP_MK40X64VLK50) || defined(CONFIG_ARCH_CHIP_MK40X64VMB50)
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# define KINETIS_NCAN 2 /* Two CAN controllers */
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# else
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# undef KINETIS_NCAN /* No CAN in 64-pin chips */
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# endif
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# define KINETIS_NI2S 1 /* One I2S module */
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# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 25x8/29x4) */
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# define KINETIS_NADC16 4 /* Four 16-bit ADC */
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# undef KINETIS_NADC12 /* No 12-channel ADC */
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# undef KINETIS_NADC13 /* No 13-channel ADC */
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# undef KINETIS_NADC15 /* No 15-channel ADC */
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# undef KINETIS_NADC18 /* No 18-channel ADC */
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# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */
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# define KINETIS_NCMP 3 /* Three analog comparators */
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# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
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# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
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# define KINETIS_NVREF 1 /* Voltage reference */
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# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
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# undef KINETIS_NTIMERS20 /* No 20 channel timers */
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# undef KINETIS_NRNG /* No random number generator */
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# define KINETIS_NRTC 1 /* Real time clock */
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# undef KINETIS_NMMCAU /* No hardware encryption */
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# undef KINETIS_NTAMPER /* No tamper detect */
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# define KINETIS_NCRC 1 /* CRC */
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#elif defined(CONFIG_ARCH_CHIP_MK40X128VFX50) || defined(CONFIG_ARCH_CHIP_MK40X128VLH50) || \
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defined(CONFIG_ARCH_CHIP_MK40X128VLK50) || defined(CONFIG_ARCH_CHIP_MK40X128VMB50) || \
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defined(CONFIG_ARCH_CHIP_MK40X128VLL50) || defined(CONFIG_ARCH_CHIP_MK40X128VML50) || \
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defined(CONFIG_ARCH_CHIP_MK40X128VFX72) || defined(CONFIG_ARCH_CHIP_MK40X128VLH72) || \
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defined(CONFIG_ARCH_CHIP_MK40X128VLK72) || defined(CONFIG_ARCH_CHIP_MK40X128VMB72) || \
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defined(CONFIG_ARCH_CHIP_MK40X128VLL72) || defined(CONFIG_ARCH_CHIP_MK40X128VML72)
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# define KINETIS_K40 1 /* Kinetics K40 family */
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# undef KINETIS_K60 /* Not Kinetis K60 family */
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# define KINETIS_FLASH_SIZE (128*1024) /* 128Kb */
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# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */
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# define KINETIS_SRAM_SIZE (32*1024) /* 32Kb */
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# undef KINETIS_MPU /* No memory protection unit */
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# undef KINETIS_EXTBUS /* No external bus interface */
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# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
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# undef KINETIS_NENET /* No Ethernet controller */
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# define KINETIS_NUSBHOST 1 /* One USB host controller */
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# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
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# define KINETIS_NUSBDEV 1 /* One USB device controller */
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# undef KINETIS_NSDHC /* No SD host controller */
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# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */
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# define KINETIS_NI2C 2 /* Two I2C modules */
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# undef KINETIS_NISO7816 /* No UART with ISO-786 */
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# define KINETIS_NUART 6 /* Six UARTs */
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# define KINETIS_NSPI 3 /* Three SPI modules */
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# define KINETIS_NCAN 2 /* Two CAN controllers */
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# define KINETIS_NI2S 1 /* One I2S module */
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# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
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# define KINETIS_NADC16 4 /* Four 16-bit ADC */
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# undef KINETIS_NADC12 /* No 12-channel ADC */
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# undef KINETIS_NADC13 /* No 13-channel ADC */
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# undef KINETIS_NADC15 /* No 15-channel ADC */
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# undef KINETIS_NADC18 /* No 18-channel ADC */
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# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */
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# define KINETIS_NCMP 3 /* Three analog comparators */
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# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
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# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
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# define KINETIS_NVREF 1 /* Voltage reference */
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# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
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# undef KINETIS_NTIMERS20 /* No 20 channel timers */
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# define KINETIS_NRTC 1 /* Real time clock */
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# undef KINETIS_NRNG /* No random number generator */
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# undef KINETIS_NMMCAU /* No hardware encryption */
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# undef KINETIS_NTAMPER /* No tamper detect */
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# define KINETIS_NCRC 1 /* CRC */
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#elif defined(CONFIG_ARCH_CHIP_MK40X256VLK72) || defined(CONFIG_ARCH_CHIP_MK40X256VMB72) || \
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defined(CONFIG_ARCH_CHIP_MK40X256VLL72) || defined(CONFIG_ARCH_CHIP_MK40X256VML72)
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# define KINETIS_K40 1 /* Kinetics K40 family */
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# undef KINETIS_K60 /* Not Kinetis K60 family */
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# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
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# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */
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# define KINETIS_SRAM_SIZE (32*1024) /* 64Kb */
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# undef KINETIS_MPU /* No memory protection unit */
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# undef KINETIS_EXTBUS /* No external bus interface */
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# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
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# undef KINETIS_NENET /* No Ethernet controller */
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# define KINETIS_NUSBHOST 1 /* One USB host controller */
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# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
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# define KINETIS_NUSBDEV 1 /* One USB device controller */
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# undef KINETIS_NSDHC /* No SD host controller */
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# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */
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# define KINETIS_NI2C 2 /* Two I2C modules */
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# undef KINETIS_NISO7816 /* No UART with ISO-786 */
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# define KINETIS_NUART 6 /* Six UARTs */
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# define KINETIS_NSPI 3 /* Three SPI modules */
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# define KINETIS_NCAN 2 /* Two CAN controllers */
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# define KINETIS_NI2S 1 /* One I2S module */
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# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
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# define KINETIS_NADC16 4 /* Four 16-bit ADC */
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# undef KINETIS_NADC12 /* No 12-channel ADC */
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# undef KINETIS_NADC13 /* No 13-channel ADC */
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# undef KINETIS_NADC15 /* No 15-channel ADC */
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# undef KINETIS_NADC18 /* No 18-channel ADC */
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# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */
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# define KINETIS_NCMP 3 /* Three analog comparators */
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# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
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# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
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# define KINETIS_NVREF 1 /* Voltage reference */
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# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
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# undef KINETIS_NTIMERS20 /* No 20 channel timers */
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# define KINETIS_NRTC 1 /* Real time clock */
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# undef KINETIS_NRNG /* No random number generator */
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# undef KINETIS_NMMCAU /* No hardware encryption */
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# undef KINETIS_NTAMPER /* No tamper detect */
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# define KINETIS_NCRC 1 /* CRC */
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#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100)
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# define KINETIS_K40 1 /* Kinetics K40 family */
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# undef KINETIS_K60 /* Not Kinetis K60 family */
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# define KINETIS_FLASH_SIZE (128*1024) /* 128Kb */
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# define KINETIS_FLEXMEM_SIZE (128*1024) /* 128Kb */
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# define KINETIS_SRAM_SIZE (32*1024) /* 32Kb */
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# define KINETIS_MPU 1 /* Memory protection unit */
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# define KINETIS_EXTBUS 1 /* External bus interface */
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# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
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# undef KINETIS_NENET /* No Ethernet controller */
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# define KINETIS_NUSBHOST 1 /* One USB host controller */
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# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
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# define KINETIS_NUSBDEV 1 /* One USB device controller */
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# define KINETIS_NSDHC 1 /* One SD host controller */
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# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */
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# define KINETIS_NI2C 2 /* Two I2C modules */
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# undef KINETIS_NISO7816 /* No UART with ISO-786 */
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# define KINETIS_NUART 6 /* Six UARTs */
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# define KINETIS_NSPI 3 /* Three SPI modules */
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# define KINETIS_NCAN 2 /* Two CAN controllers */
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# define KINETIS_NI2S 1 /* One I2S module */
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# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 40x8/44x4)*/
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# define KINETIS_NADC16 4 /* Four 16-bit ADC */
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# undef KINETIS_NADC12 /* No 12-channel ADC */
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# undef KINETIS_NADC13 /* No 13-channel ADC */
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# undef KINETIS_NADC15 /* No 15-channel ADC */
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# undef KINETIS_NADC18 /* No 18-channel ADC */
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# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */
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# define KINETIS_NCMP 3 /* Three analog comparators */
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# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
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# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
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# define KINETIS_NVREF 1 /* Voltage reference */
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# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
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# undef KINETIS_NTIMERS20 /* No 20 channel timers */
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# define KINETIS_NRTC 1 /* Real time clock */
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# undef KINETIS_NRNG /* No random number generator */
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# undef KINETIS_NMMCAU /* No hardware encryption */
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# undef KINETIS_NTAMPER /* No tamper detect */
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# define KINETIS_NCRC 1 /* CRC */
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#elif defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100)
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# define KINETIS_K40 1 /* Kinetics K40 family */
|
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# undef KINETIS_K60 /* Not Kinetis K60 family */
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# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
|
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# define KINETIS_FLEXMEM_SIZE (256*1024) /* 256Kb */
|
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# define KINETIS_SRAM_SIZE (64*1024) /* 32Kb */
|
||||
# define KINETIS_MPU 1 /* Memory protection unit */
|
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# define KINETIS_EXTBUS 1 /* External bus interface */
|
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# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
|
||||
# undef KINETIS_NENET /* No Ethernet controller */
|
||||
# define KINETIS_NUSBHOST 1 /* One USB host controller */
|
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# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
|
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# define KINETIS_NUSBDEV 1 /* One USB device controller */
|
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# define KINETIS_NSDHC 1 /* One SD host controller */
|
||||
# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */
|
||||
# define KINETIS_NI2C 2 /* Two I2C modules */
|
||||
# undef KINETIS_NISO7816 /* No UART with ISO-786 */
|
||||
# define KINETIS_NUART 6 /* Six UARTs */
|
||||
# define KINETIS_NSPI 3 /* Three SPI modules */
|
||||
# define KINETIS_NCAN 2 /* Two CAN controllers */
|
||||
# define KINETIS_NI2S 1 /* One I2S module */
|
||||
# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 40x8/44x4)*/
|
||||
# define KINETIS_NADC16 4 /* Four 16-bit ADC */
|
||||
# undef KINETIS_NADC12 /* No 12-channel ADC */
|
||||
# undef KINETIS_NADC13 /* No 13-channel ADC */
|
||||
# undef KINETIS_NADC15 /* No 15-channel ADC */
|
||||
# undef KINETIS_NADC18 /* No 18-channel ADC */
|
||||
# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */
|
||||
# define KINETIS_NCMP 3 /* Three analog comparators */
|
||||
# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
|
||||
# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
|
||||
# define KINETIS_NVREF 1 /* Voltage reference */
|
||||
# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
|
||||
# undef KINETIS_NTIMERS20 /* No 20 channel timers */
|
||||
# define KINETIS_NRTC 1 /* Real time clock */
|
||||
# undef KINETIS_NRNG /* No random number generator */
|
||||
# undef KINETIS_NMMCAU /* No hardware encryption */
|
||||
# undef KINETIS_NTAMPER /* No tamper detect */
|
||||
# define KINETIS_NCRC 1 /* CRC */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK40N512VLK100) || defined(CONFIG_ARCH_CHIP_MK40N512VMB100) || \
|
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defined(CONFIG_ARCH_CHIP_MK40N512VLL100) || defined(CONFIG_ARCH_CHIP_MK40N512VML100) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100)
|
||||
# define KINETIS_K40 1 /* Kinetics K40 family */
|
||||
# undef KINETIS_K60 /* Not Kinetis K60 family */
|
||||
# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */
|
||||
# undef KINETIS_FLEXMEM_SIZE /* No FlexMemory */
|
||||
# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */
|
||||
# define KINETIS_MPU 1 /* Memory protection unit */
|
||||
# define KINETIS_EXTBUS 1 /* External bus interface */
|
||||
# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
|
||||
# undef KINETIS_NENET /* No Ethernet controller */
|
||||
# define KINETIS_NUSBHOST 1 /* One USB host controller */
|
||||
# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
|
||||
# define KINETIS_NUSBDEV 1 /* One USB device controller */
|
||||
# define KINETIS_NSDHC 1 /* One SD host controller */
|
||||
# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */
|
||||
# define KINETIS_NI2C 2 /* Two I2C modules */
|
||||
# undef KINETIS_NISO7816 /* No UART with ISO-786 */
|
||||
# define KINETIS_NUART 6 /* Six UARTs */
|
||||
# define KINETIS_NSPI 3 /* Three SPI modules */
|
||||
# define KINETIS_NCAN 2 /* Two CAN controllers */
|
||||
# define KINETIS_NI2S 1 /* One I2S module */
|
||||
# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 40x8/44x4)*/
|
||||
# define KINETIS_NADC16 4 /* Four 16-bit ADC */
|
||||
# undef KINETIS_NADC12 /* No 12-channel ADC */
|
||||
# undef KINETIS_NADC13 /* No 13-channel ADC */
|
||||
# undef KINETIS_NADC15 /* No 15-channel ADC */
|
||||
# undef KINETIS_NADC18 /* No 18-channel ADC */
|
||||
# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */
|
||||
# define KINETIS_NCMP 3 /* Three analog comparators */
|
||||
# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
|
||||
# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
|
||||
# define KINETIS_NVREF 1 /* Voltage reference */
|
||||
# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
|
||||
# undef KINETIS_NTIMERS20 /* No 20 channel timers */
|
||||
# define KINETIS_NRTC 1 /* Real time clock */
|
||||
# undef KINETIS_NRNG /* No random number generator */
|
||||
# undef KINETIS_NMMCAU /* No hardware encryption */
|
||||
# undef KINETIS_NTAMPER /* No tamper detect */
|
||||
# define KINETIS_NCRC 1 /* CRC */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK60N256VLL100)
|
||||
# undef KINETIS_K40 /* Not Kinetics K40 family */
|
||||
# define KINETIS_K60 1 /* Kinetis K60 family */
|
||||
# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
|
||||
# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
|
||||
# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
|
||||
# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */
|
||||
# define KINETIS_MPU 1 /* Memory protection unit */
|
||||
# define KINETIS_EXTBUS 1 /* External bus interface */
|
||||
# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
|
||||
# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
|
||||
# define KINETIS_NUSBHOST 1 /* One USB host controller */
|
||||
# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
|
||||
# define KINETIS_NUSBDEV 1 /* One USB device controller */
|
||||
# define KINETIS_NSDHC 1 /* SD host controller */
|
||||
# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
|
||||
# define KINETIS_NI2C 3 /* Three I2C modules */
|
||||
# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
|
||||
# define KINETIS_NUART 4 /* Four additional UARTs */
|
||||
# define KINETIS_NSPI 3 /* Three SPI modules */
|
||||
# define KINETIS_NCAN 2 /* Two CAN controllers */
|
||||
# define KINETIS_NI2S 2 /* Two I2S modules */
|
||||
# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
|
||||
# define KINETIS_NADC16 4 /* Four 16-bit ADC */
|
||||
# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/
|
||||
# define KINETIS_NADC13 1 /* No 13-channel ADC (ADC1) */
|
||||
# undef KINETIS_NADC15 /* No 15-channel ADC */
|
||||
# undef KINETIS_NADC18 /* No 18-channel ADC */
|
||||
# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
|
||||
# define KINETIS_NCMP 3 /* Three analog comparators */
|
||||
# undef KINETIS_NDAC6 /* No 6-bit DAC */
|
||||
# define KINETIS_NDAC12 1 /* One 12-bit DAC */
|
||||
# define KINETIS_NVREF 1 /* Voltage reference */
|
||||
# undef KINETIS_NTIMERS12 /* No 12 channel timers */
|
||||
# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
|
||||
# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
|
||||
# undef KINETIS_NTIMERS20 /* No 20 channel timers */
|
||||
# define KINETIS_NRTC 1 /* Real time clock */
|
||||
# undef KINETIS_NRNG /* No random number generator */
|
||||
# undef KINETIS_NMMCAU /* No hardware encryption */
|
||||
# undef KINETIS_NTAMPER /* No tamper detect */
|
||||
# define KINETIS_NCRC 1 /* CRC */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK60X256VLL100)
|
||||
# undef KINETIS_K40 /* Not Kinetics K40 family */
|
||||
# define KINETIS_K60 1 /* Kinetis K60 family */
|
||||
# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
|
||||
# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */
|
||||
# define KINETIS_FLEXRAM_SIZE (4*1024) /* 32Kb */
|
||||
# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */
|
||||
# define KINETIS_MPU 1 /* Memory protection unit */
|
||||
# define KINETIS_EXTBUS 1 /* External bus interface */
|
||||
# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
|
||||
# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
|
||||
# define KINETIS_NUSBHOST 1 /* One USB host controller */
|
||||
# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
|
||||
# define KINETIS_NUSBDEV 1 /* One USB device controller */
|
||||
# define KINETIS_NSDHC 1 /* SD host controller */
|
||||
# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
|
||||
# define KINETIS_NI2C 3 /* Three I2C modules */
|
||||
# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
|
||||
# define KINETIS_NUART 4 /* Four additional UARTs */
|
||||
# define KINETIS_NSPI 3 /* Three SPI modules */
|
||||
# define KINETIS_NCAN 2 /* Two CAN controllers */
|
||||
# define KINETIS_NI2S 2 /* Two I2S modules */
|
||||
# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
|
||||
# define KINETIS_NADC16 4 /* Four 16-bit ADC */
|
||||
# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/
|
||||
# define KINETIS_NADC13 1 /* No 13-channel ADC (ADC1) */
|
||||
# undef KINETIS_NADC15 /* No 15-channel ADC */
|
||||
# undef KINETIS_NADC18 /* No 18-channel ADC */
|
||||
# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
|
||||
# define KINETIS_NCMP 3 /* Three analog comparators */
|
||||
# undef KINETIS_NDAC6 /* No 6-bit DAC */
|
||||
# define KINETIS_NDAC12 1 /* One 12-bit DAC */
|
||||
# define KINETIS_NVREF 1 /* Voltage reference */
|
||||
# undef KINETIS_NTIMERS12 /* No 12 channel timers */
|
||||
# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
|
||||
# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
|
||||
# undef KINETIS_NTIMERS20 /* No 20 channel timers */
|
||||
# define KINETIS_NRTC 1 /* Real time clock */
|
||||
# undef KINETIS_NRNG /* No random number generator */
|
||||
# undef KINETIS_NMMCAU /* No hardware encryption */
|
||||
# undef KINETIS_NTAMPER /* No tamper detect */
|
||||
# define KINETIS_NCRC 1 /* CRC */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK60N512VLL100)
|
||||
# undef KINETIS_K40 /* Not Kinetics K40 family */
|
||||
# define KINETIS_K60 1 /* Kinetis K60 family */
|
||||
# define KINETIS_FLASH_SIZE (512*1024) /* 256Kb */
|
||||
# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
|
||||
# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
|
||||
# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */
|
||||
# define KINETIS_MPU 1 /* Memory protection unit */
|
||||
# define KINETIS_EXTBUS 1 /* External bus interface */
|
||||
# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
|
||||
# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
|
||||
# define KINETIS_NUSBHOST 1 /* One USB host controller */
|
||||
# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
|
||||
# define KINETIS_NUSBDEV 1 /* One USB device controller */
|
||||
# define KINETIS_NSDHC 1 /* SD host controller */
|
||||
# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
|
||||
# define KINETIS_NI2C 3 /* Three I2C modules */
|
||||
# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
|
||||
# define KINETIS_NUART 4 /* Four additional UARTs */
|
||||
# define KINETIS_NSPI 3 /* Three SPI modules */
|
||||
# define KINETIS_NCAN 2 /* Two CAN controllers */
|
||||
# define KINETIS_NI2S 2 /* Two I2S modules */
|
||||
# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
|
||||
# define KINETIS_NADC16 4 /* Four 16-bit ADC */
|
||||
# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/
|
||||
# define KINETIS_NADC13 1 /* No 13-channel ADC (ADC1) */
|
||||
# undef KINETIS_NADC15 /* No 15-channel ADC */
|
||||
# undef KINETIS_NADC18 /* No 18-channel ADC */
|
||||
# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
|
||||
# define KINETIS_NCMP 3 /* Three analog comparators */
|
||||
# undef KINETIS_NDAC6 /* No 6-bit DAC */
|
||||
# define KINETIS_NDAC12 1 /* One 12-bit DAC */
|
||||
# define KINETIS_NVREF 1 /* Voltage reference */
|
||||
# undef KINETIS_NTIMERS12 /* No 12 channel timers */
|
||||
# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
|
||||
# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
|
||||
# undef KINETIS_NTIMERS20 /* No 20 channel timers */
|
||||
# define KINETIS_NRTC 1 /* Real time clock */
|
||||
# undef KINETIS_NRNG /* No random number generator */
|
||||
# undef KINETIS_NMMCAU /* No hardware encryption */
|
||||
# undef KINETIS_NTAMPER /* No tamper detect */
|
||||
# define KINETIS_NCRC 1 /* CRC */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK60N256VML100)
|
||||
# undef KINETIS_K40 /* Not Kinetics K40 family */
|
||||
# define KINETIS_K60 1 /* Kinetis K60 family */
|
||||
# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
|
||||
# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
|
||||
# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
|
||||
# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */
|
||||
# define KINETIS_MPU 1 /* Memory protection unit */
|
||||
# define KINETIS_EXTBUS 1 /* External bus interface */
|
||||
# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
|
||||
# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
|
||||
# define KINETIS_NUSBHOST 1 /* One USB host controller */
|
||||
# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
|
||||
# define KINETIS_NUSBDEV 1 /* One USB device controller */
|
||||
# define KINETIS_NSDHC 1 /* SD host controller */
|
||||
# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
|
||||
# define KINETIS_NI2C 3 /* Three I2C modules */
|
||||
# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
|
||||
# define KINETIS_NUART 4 /* Four additional UARTs */
|
||||
# define KINETIS_NSPI 3 /* Three SPI modules */
|
||||
# define KINETIS_NCAN 2 /* Two CAN controllers */
|
||||
# define KINETIS_NI2S 2 /* Two I2S modules */
|
||||
# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
|
||||
# define KINETIS_NADC16 4 /* Four 16-bit ADC */
|
||||
# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/
|
||||
# undef KINETIS_NADC13 /* No 13-channel ADC */
|
||||
# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC1) */
|
||||
# undef KINETIS_NADC18 /* No 18-channel ADC */
|
||||
# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
|
||||
# define KINETIS_NCMP 3 /* Three analog comparators */
|
||||
# undef KINETIS_NDAC6 /* No 6-bit DAC */
|
||||
# define KINETIS_NDAC12 1 /* One 12-bit DAC */
|
||||
# define KINETIS_NVREF 1 /* Voltage reference */
|
||||
# undef KINETIS_NTIMERS12 /* No 12 channel timers */
|
||||
# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
|
||||
# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
|
||||
# undef KINETIS_NTIMERS20 /* No 20 channel timers */
|
||||
# define KINETIS_NRTC 1 /* Real time clock */
|
||||
# undef KINETIS_NRNG /* No random number generator */
|
||||
# undef KINETIS_NMMCAU /* No hardware encryption */
|
||||
# undef KINETIS_NTAMPER /* No tamper detect */
|
||||
# define KINETIS_NCRC 1 /* CRC */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK60X256VML100)
|
||||
# undef KINETIS_K40 /* Not Kinetics K40 family */
|
||||
# define KINETIS_K60 1 /* Kinetis K60 family */
|
||||
# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
|
||||
# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */
|
||||
# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
|
||||
# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */
|
||||
# define KINETIS_MPU 1 /* Memory protection unit */
|
||||
# define KINETIS_EXTBUS 1 /* External bus interface */
|
||||
# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
|
||||
# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
|
||||
# define KINETIS_NUSBHOST 1 /* One USB host controller */
|
||||
# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
|
||||
# define KINETIS_NUSBDEV 1 /* One USB device controller */
|
||||
# define KINETIS_NSDHC 1 /* SD host controller */
|
||||
# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
|
||||
# define KINETIS_NI2C 3 /* Three I2C modules */
|
||||
# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
|
||||
# define KINETIS_NUART 4 /* Four additional UARTs */
|
||||
# define KINETIS_NSPI 3 /* Three SPI modules */
|
||||
# define KINETIS_NCAN 2 /* Two CAN controllers */
|
||||
# define KINETIS_NI2S 2 /* Two I2S modules */
|
||||
# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
|
||||
# define KINETIS_NADC16 4 /* Four 16-bit ADC */
|
||||
# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/
|
||||
# undef KINETIS_NADC13 /* No 13-channel ADC */
|
||||
# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC1) */
|
||||
# undef KINETIS_NADC18 /* No 18-channel ADC */
|
||||
# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
|
||||
# define KINETIS_NCMP 3 /* Three analog comparators */
|
||||
# undef KINETIS_NDAC6 /* No 6-bit DAC */
|
||||
# define KINETIS_NDAC12 1 /* One 12-bit DAC */
|
||||
# define KINETIS_NVREF 1 /* Voltage reference */
|
||||
# undef KINETIS_NTIMERS12 /* No 12 channel timers */
|
||||
# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
|
||||
# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
|
||||
# undef KINETIS_NTIMERS20 /* No 20 channel timers */
|
||||
# define KINETIS_NRTC 1 /* Real time clock */
|
||||
# undef KINETIS_NRNG /* No random number generator */
|
||||
# undef KINETIS_NMMCAU /* No hardware encryption */
|
||||
# undef KINETIS_NTAMPER /* No tamper detect */
|
||||
# define KINETIS_NCRC 1 /* CRC */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK60N512VML100)
|
||||
# undef KINETIS_K40 /* Not Kinetics K40 family */
|
||||
# define KINETIS_K60 1 /* Kinetis K60 family */
|
||||
# define KINETIS_FLASH_SIZE (512*1024) /* 256Kb */
|
||||
# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
|
||||
# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
|
||||
# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */
|
||||
# define KINETIS_MPU 1 /* Memory protection unit */
|
||||
# define KINETIS_EXTBUS 1 /* External bus interface */
|
||||
# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
|
||||
# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
|
||||
# define KINETIS_NUSBHOST 1 /* One USB host controller */
|
||||
# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
|
||||
# define KINETIS_NUSBDEV 1 /* One USB device controller */
|
||||
# define KINETIS_NSDHC 1 /* SD host controller */
|
||||
# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
|
||||
# define KINETIS_NI2C 3 /* Three I2C modules */
|
||||
# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
|
||||
# define KINETIS_NUART 4 /* Four additional UARTs */
|
||||
# define KINETIS_NSPI 3 /* Three SPI modules */
|
||||
# define KINETIS_NCAN 2 /* Two CAN controllers */
|
||||
# define KINETIS_NI2S 2 /* Two I2S modules */
|
||||
# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
|
||||
# define KINETIS_NADC16 4 /* Four 16-bit ADC */
|
||||
# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/
|
||||
# undef KINETIS_NADC13 /* No 13-channel ADC */
|
||||
# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC1) */
|
||||
# undef KINETIS_NADC18 /* No 18-channel ADC */
|
||||
# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
|
||||
# define KINETIS_NCMP 3 /* Three analog comparators */
|
||||
# undef KINETIS_NDAC6 /* No 6-bit DAC */
|
||||
# define KINETIS_NDAC12 1 /* One 12-bit DAC */
|
||||
# define KINETIS_NVREF 1 /* Voltage reference */
|
||||
# undef KINETIS_NTIMERS12 /* No 12 channel timers */
|
||||
# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
|
||||
# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
|
||||
# undef KINETIS_NTIMERS20 /* No 20 channel timers */
|
||||
# define KINETIS_NRTC 1 /* Real time clock */
|
||||
# undef KINETIS_NRNG /* No random number generator */
|
||||
# undef KINETIS_NMMCAU /* No hardware encryption */
|
||||
# undef KINETIS_NTAMPER /* No tamper detect */
|
||||
# define KINETIS_NCRC 1 /* CRC */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100)
|
||||
# undef KINETIS_K40 /* Not Kinetics K40 family */
|
||||
# define KINETIS_K60 1 /* Kinetis K60 family */
|
||||
# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
|
||||
# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
|
||||
# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
|
||||
# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */
|
||||
# define KINETIS_MPU 1 /* Memory protection unit */
|
||||
# define KINETIS_EXTBUS 1 /* External bus interface */
|
||||
# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
|
||||
# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
|
||||
# define KINETIS_NUSBHOST 1 /* One USB host controller */
|
||||
# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
|
||||
# define KINETIS_NUSBDEV 1 /* One USB device controller */
|
||||
# define KINETIS_NSDHC 1 /* SD host controller */
|
||||
# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
|
||||
# define KINETIS_NI2C 3 /* Three I2C modules */
|
||||
# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
|
||||
# define KINETIS_NUART 5 /* Five additional UARTs */
|
||||
# define KINETIS_NSPI 3 /* Three SPI modules */
|
||||
# define KINETIS_NCAN 2 /* Two CAN controllers */
|
||||
# define KINETIS_NI2S 2 /* Two I2S modules */
|
||||
# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
|
||||
# define KINETIS_NADC16 4 /* Four 16-bit ADC */
|
||||
# undef KINETIS_NADC12 /* No 12-channel ADC */
|
||||
# undef KINETIS_NADC13 /* No 13-channel ADC */
|
||||
# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */
|
||||
# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */
|
||||
# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
|
||||
# define KINETIS_NCMP 3 /* Three analog comparators */
|
||||
# undef KINETIS_NDAC6 /* No 6-bit DAC */
|
||||
# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */
|
||||
# define KINETIS_NVREF 1 /* Voltage reference */
|
||||
# undef KINETIS_NTIMERS12 /* No 12 channel timers */
|
||||
# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
|
||||
# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
|
||||
# undef KINETIS_NTIMERS20 /* No 20 channel timers */
|
||||
# define KINETIS_NRTC 1 /* Real time clock */
|
||||
# undef KINETIS_NRNG /* No random number generator */
|
||||
# undef KINETIS_NMMCAU /* No hardware encryption */
|
||||
# undef KINETIS_NTAMPER /* No tamper detect */
|
||||
# define KINETIS_NCRC 1 /* CRC */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK60X256VLQ100)
|
||||
# undef KINETIS_K40 /* Not Kinetics K40 family */
|
||||
# define KINETIS_K60 1 /* Kinetis K60 family */
|
||||
# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
|
||||
# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */
|
||||
# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
|
||||
# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */
|
||||
# define KINETIS_MPU 1 /* Memory protection unit */
|
||||
# define KINETIS_EXTBUS 1 /* External bus interface */
|
||||
# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
|
||||
# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
|
||||
# define KINETIS_NUSBHOST 1 /* One USB host controller */
|
||||
# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
|
||||
# define KINETIS_NUSBDEV 1 /* One USB device controller */
|
||||
# define KINETIS_NSDHC 1 /* SD host controller */
|
||||
# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
|
||||
# define KINETIS_NI2C 3 /* Three I2C modules */
|
||||
# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
|
||||
# define KINETIS_NUART 5 /* Five additional UARTs */
|
||||
# define KINETIS_NSPI 3 /* Three SPI modules */
|
||||
# define KINETIS_NCAN 2 /* Two CAN controllers */
|
||||
# define KINETIS_NI2S 2 /* Two I2S modules */
|
||||
# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
|
||||
# define KINETIS_NADC16 4 /* Four 16-bit ADC */
|
||||
# undef KINETIS_NADC12 /* No 12-channel ADC */
|
||||
# undef KINETIS_NADC13 /* No 13-channel ADC */
|
||||
# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */
|
||||
# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */
|
||||
# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
|
||||
# define KINETIS_NCMP 3 /* Three analog comparators */
|
||||
# undef KINETIS_NDAC6 /* No 6-bit DAC */
|
||||
# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */
|
||||
# define KINETIS_NVREF 1 /* Voltage reference */
|
||||
# undef KINETIS_NTIMERS12 /* No 12 channel timers */
|
||||
# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
|
||||
# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
|
||||
# undef KINETIS_NTIMERS20 /* No 20 channel timers */
|
||||
# define KINETIS_NRTC 1 /* Real time clock */
|
||||
# undef KINETIS_NRNG /* No random number generator */
|
||||
# undef KINETIS_NMMCAU /* No hardware encryption */
|
||||
# undef KINETIS_NTAMPER /* No tamper detect */
|
||||
# define KINETIS_NCRC 1 /* CRC */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK60N512VLQ100)
|
||||
# undef KINETIS_K40 /* Not Kinetics K40 family */
|
||||
# define KINETIS_K60 1 /* Kinetis K60 family */
|
||||
# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */
|
||||
# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
|
||||
# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
|
||||
# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */
|
||||
# define KINETIS_MPU 1 /* Memory protection unit */
|
||||
# define KINETIS_EXTBUS 1 /* External bus interface */
|
||||
# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
|
||||
# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
|
||||
# define KINETIS_NUSBHOST 1 /* One USB host controller */
|
||||
# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
|
||||
# define KINETIS_NUSBDEV 1 /* One USB device controller */
|
||||
# define KINETIS_NSDHC 1 /* SD host controller */
|
||||
# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
|
||||
# define KINETIS_NI2C 3 /* Three I2C modules */
|
||||
# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
|
||||
# define KINETIS_NUART 5 /* Five additional UARTs */
|
||||
# define KINETIS_NSPI 3 /* Three SPI modules */
|
||||
# define KINETIS_NCAN 2 /* Two CAN controllers */
|
||||
# define KINETIS_NI2S 2 /* Two I2S modules */
|
||||
# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
|
||||
# define KINETIS_NADC16 4 /* Four 16-bit ADC */
|
||||
# undef KINETIS_NADC12 /* No 12-channel ADC */
|
||||
# undef KINETIS_NADC13 /* No 13-channel ADC */
|
||||
# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */
|
||||
# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */
|
||||
# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
|
||||
# define KINETIS_NCMP 3 /* Three analog comparators */
|
||||
# undef KINETIS_NDAC6 /* No 6-bit DAC */
|
||||
# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */
|
||||
# define KINETIS_NVREF 1 /* Voltage reference */
|
||||
# undef KINETIS_NTIMERS12 /* No 12 channel timers */
|
||||
# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
|
||||
# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
|
||||
# undef KINETIS_NTIMERS20 /* No 20 channel timers */
|
||||
# define KINETIS_NRTC 1 /* Real time clock */
|
||||
# undef KINETIS_NRNG /* No random number generator */
|
||||
# undef KINETIS_NMMCAU /* No hardware encryption */
|
||||
# undef KINETIS_NTAMPER /* No tamper detect */
|
||||
# define KINETIS_NCRC 1 /* CRC */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK60N256VMD100)
|
||||
# undef KINETIS_K40 /* Not Kinetics K40 family */
|
||||
# define KINETIS_K60 1 /* Kinetis K60 family */
|
||||
# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
|
||||
# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
|
||||
# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
|
||||
# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */
|
||||
# define KINETIS_MPU 1 /* Memory protection unit */
|
||||
# define KINETIS_EXTBUS 1 /* External bus interface */
|
||||
# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
|
||||
# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
|
||||
# define KINETIS_NUSBHOST 1 /* One USB host controller */
|
||||
# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
|
||||
# define KINETIS_NUSBDEV 1 /* One USB device controller */
|
||||
# define KINETIS_NSDHC 1 /* SD host controller */
|
||||
# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
|
||||
# define KINETIS_NI2C 3 /* Three I2C modules */
|
||||
# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
|
||||
# define KINETIS_NUART 5 /* Five additional UARTs */
|
||||
# define KINETIS_NSPI 3 /* Three SPI modules */
|
||||
# define KINETIS_NCAN 2 /* Two CAN controllers */
|
||||
# define KINETIS_NI2S 2 /* Two I2S modules */
|
||||
# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
|
||||
# define KINETIS_NADC16 4 /* Four 16-bit ADC */
|
||||
# undef KINETIS_NADC12 /* No 12-channel ADC */
|
||||
# undef KINETIS_NADC13 /* No 13-channel ADC */
|
||||
# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */
|
||||
# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */
|
||||
# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
|
||||
# define KINETIS_NCMP 3 /* Three analog comparators */
|
||||
# undef KINETIS_NDAC6 /* No 6-bit DAC */
|
||||
# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */
|
||||
# define KINETIS_NVREF 1 /* Voltage reference */
|
||||
# undef KINETIS_NTIMERS12 /* No 12 channel timers */
|
||||
# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
|
||||
# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
|
||||
# undef KINETIS_NTIMERS20 /* No 20 channel timers */
|
||||
# define KINETIS_NRTC 1 /* Real time clock */
|
||||
# undef KINETIS_NRNG /* No random number generator */
|
||||
# undef KINETIS_NMMCAU /* No hardware encryption */
|
||||
# undef KINETIS_NTAMPER /* No tamper detect */
|
||||
# define KINETIS_NCRC 1 /* CRC */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK60X256VMD100)
|
||||
# undef KINETIS_K40 /* Not Kinetics K40 family */
|
||||
# define KINETIS_K60 1 /* Kinetis K60 family */
|
||||
# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
|
||||
# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */
|
||||
# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
|
||||
# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */
|
||||
# define KINETIS_MPU 1 /* Memory protection unit */
|
||||
# define KINETIS_EXTBUS 1 /* External bus interface */
|
||||
# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
|
||||
# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
|
||||
# define KINETIS_NUSBHOST 1 /* One USB host controller */
|
||||
# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
|
||||
# define KINETIS_NUSBDEV 1 /* One USB device controller */
|
||||
# define KINETIS_NSDHC 1 /* SD host controller */
|
||||
# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
|
||||
# define KINETIS_NI2C 3 /* Three I2C modules */
|
||||
# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
|
||||
# define KINETIS_NUART 5 /* Five additional UARTs */
|
||||
# define KINETIS_NSPI 3 /* Three SPI modules */
|
||||
# define KINETIS_NCAN 2 /* Two CAN controllers */
|
||||
# define KINETIS_NI2S 2 /* Two I2S modules */
|
||||
# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
|
||||
# define KINETIS_NADC16 4 /* Four 16-bit ADC */
|
||||
# undef KINETIS_NADC12 /* No 12-channel ADC */
|
||||
# undef KINETIS_NADC13 /* No 13-channel ADC */
|
||||
# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */
|
||||
# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */
|
||||
# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
|
||||
# define KINETIS_NCMP 3 /* Three analog comparators */
|
||||
# undef KINETIS_NDAC6 /* No 6-bit DAC */
|
||||
# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */
|
||||
# define KINETIS_NVREF 1 /* Voltage reference */
|
||||
# undef KINETIS_NTIMERS12 /* No 12 channel timers */
|
||||
# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
|
||||
# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
|
||||
# undef KINETIS_NTIMERS20 /* No 20 channel timers */
|
||||
# define KINETIS_NRTC 1 /* Real time clock */
|
||||
# undef KINETIS_NRNG /* No random number generator */
|
||||
# undef KINETIS_NMMCAU /* No hardware encryption */
|
||||
# undef KINETIS_NTAMPER /* No tamper detect */
|
||||
# define KINETIS_NCRC 1 /* CRC */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK60N512VMD100)
|
||||
# undef KINETIS_K40 /* Not Kinetics K40 family */
|
||||
# define KINETIS_K60 1 /* Kinetis K60 family */
|
||||
# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */
|
||||
# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
|
||||
# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
|
||||
# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */
|
||||
# define KINETIS_MPU 1 /* Memory protection unit */
|
||||
# define KINETIS_EXTBUS 1 /* External bus interface */
|
||||
# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
|
||||
# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
|
||||
# define KINETIS_NUSBHOST 1 /* One USB host controller */
|
||||
# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
|
||||
# define KINETIS_NUSBDEV 1 /* One USB device controller */
|
||||
# define KINETIS_NSDHC 1 /* SD host controller */
|
||||
# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
|
||||
# define KINETIS_NI2C 3 /* Three I2C modules */
|
||||
# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
|
||||
# define KINETIS_NUART 5 /* Five additional UARTs */
|
||||
# define KINETIS_NSPI 3 /* Three SPI modules */
|
||||
# define KINETIS_NCAN 2 /* Two CAN controllers */
|
||||
# define KINETIS_NI2S 2 /* Two I2S modules */
|
||||
# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
|
||||
# define KINETIS_NADC16 4 /* Four 16-bit ADC */
|
||||
# undef KINETIS_NADC12 /* No 12-channel ADC */
|
||||
# undef KINETIS_NADC13 /* No 13-channel ADC */
|
||||
# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */
|
||||
# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */
|
||||
# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
|
||||
# define KINETIS_NCMP 3 /* Three analog comparators */
|
||||
# undef KINETIS_NDAC6 /* No 6-bit DAC */
|
||||
# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */
|
||||
# define KINETIS_NVREF 1 /* Voltage reference */
|
||||
# undef KINETIS_NTIMERS12 /* No 12 channel timers */
|
||||
# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
|
||||
# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
|
||||
# undef KINETIS_NTIMERS20 /* No 20 channel timers */
|
||||
# define KINETIS_NRTC 1 /* Real time clock */
|
||||
# undef KINETIS_NRNG /* No random number generator */
|
||||
# undef KINETIS_NMMCAU /* No hardware encryption */
|
||||
# undef KINETIS_NTAMPER /* No tamper detect */
|
||||
# define KINETIS_NCRC 1 /* CRC */
|
||||
|
||||
#else
|
||||
# error "Unsupported Kinetis chip"
|
||||
#endif
|
||||
|
||||
/* Include only the memory map. Other chip hardware files should then include this
|
||||
* file for the proper setup
|
||||
*/
|
||||
|
||||
#include "kinetis_memorymap.h"
|
||||
|
||||
/* NVIC priority levels *************************************************************/
|
||||
/* Each priority field holds a priority value, 0-15. The lower the value, the greater
|
||||
* the priority of the corresponding interrupt. The processor implements only
|
||||
* bits[7:4] of each field, bits[3:0] read as zero and ignore writes.
|
||||
*/
|
||||
|
||||
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */
|
||||
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
|
||||
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
|
||||
#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Steps between supported priority values */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* arch/arm/src/lpc17/kinetis_irq.c
|
||||
* arch/arm/src/chip/kinetis_irq.c
|
||||
*
|
||||
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@@ -208,6 +208,35 @@ static int kinetis_reserved(int irq, FAR void *context)
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_prioritize_irq
|
||||
*
|
||||
* Description:
|
||||
* Set the priority of an exception. This function may be needed
|
||||
* internally even if support for prioritized interrupts is not enabled.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI)
|
||||
static int up_prioritize_irq(int irq, int priority)
|
||||
{
|
||||
uint32_t regaddr;
|
||||
uint32_t regval;
|
||||
int shift;
|
||||
|
||||
irq -= 4;
|
||||
regaddr = NVIC_SYSH_PRIORITY(irq);
|
||||
regval = getreg32(regaddr);
|
||||
shift = ((irq & 3) << 3);
|
||||
regval &= ~(0xff << shift);
|
||||
regval |= (priority << shift);
|
||||
putreg32(regval, regaddr);
|
||||
|
||||
stm32_dumpnvic("prioritize", irq);
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_irqinfo
|
||||
*
|
||||
@@ -358,6 +387,9 @@ void up_irqinitialize(void)
|
||||
|
||||
#ifdef CONFIG_ARCH_IRQPRIO
|
||||
/* up_prioritize_irq(KINETIS_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
|
||||
#endif
|
||||
#ifdef CONFIG_ARMV7M_USEBASEPRI
|
||||
up_prioritize_irq(KINETIS_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY);
|
||||
#endif
|
||||
|
||||
/* If the MPU is enabled, then attach and enable the Memory Management
|
||||
@@ -486,7 +518,14 @@ int up_prioritize_irq(int irq, int priority)
|
||||
uint32_t regval;
|
||||
int shift;
|
||||
|
||||
DEBUGASSERT(irq >= KINETIS_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
|
||||
#ifdef CONFIG_ARMV7M_USEBASEPRI
|
||||
DEBUGASSERT(irq >= KINETIS_IRQ_MEMFAULT && irq < NR_IRQS &&
|
||||
priority >= NVIC_SYSH_DISABLE_PRIORITY &&
|
||||
priority <= NVIC_SYSH_PRIORITY_MIN);
|
||||
#else
|
||||
DEBUGASSERT(irq >= KINETIS_IRQ_MEMFAULT && irq < NR_IRQS &&
|
||||
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
|
||||
#endif
|
||||
|
||||
if (irq < KINETIS_IRQ_EXTINT)
|
||||
{
|
||||
|
||||
@@ -43,10 +43,6 @@
|
||||
#include <nuttx/config.h>
|
||||
#include <arch/lm/chip.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Then get all of the register definitions */
|
||||
|
||||
#include "chip/lm_memorymap.h" /* Memory map */
|
||||
@@ -58,15 +54,9 @@
|
||||
#include "chip/lm_ethernet.h" /* Ethernet MAC and PHY */
|
||||
#include "chip/lm_flash.h" /* FLASH */
|
||||
|
||||
/* The LM3S69xx only supports 8 priority levels. The hardware priority mechanism
|
||||
* will only look at the upper N bits of the 8-bit priority level (where N is 3 for
|
||||
* the Stellaris family), so any prioritization must be performed in those bits.
|
||||
* The default priority level is set to the middle value
|
||||
*/
|
||||
|
||||
#define NVIC_SYSH_PRIORITY_MIN 0xe0 /* All bits set in minimum priority */
|
||||
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
|
||||
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* arch/arm/src/lm/lm_irq.c
|
||||
* arch/arm/src/chip/lm_irq.c
|
||||
*
|
||||
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@@ -190,6 +190,35 @@ static int lm_reserved(int irq, FAR void *context)
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_prioritize_irq
|
||||
*
|
||||
* Description:
|
||||
* Set the priority of an exception. This function may be needed
|
||||
* internally even if support for prioritized interrupts is not enabled.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI)
|
||||
static int up_prioritize_irq(int irq, int priority)
|
||||
{
|
||||
uint32_t regaddr;
|
||||
uint32_t regval;
|
||||
int shift;
|
||||
|
||||
irq -= 4;
|
||||
regaddr = NVIC_SYSH_PRIORITY(irq);
|
||||
regval = getreg32(regaddr);
|
||||
shift = ((irq & 3) << 3);
|
||||
regval &= ~(0xff << shift);
|
||||
regval |= (priority << shift);
|
||||
putreg32(regval, regaddr);
|
||||
|
||||
stm32_dumpnvic("prioritize", irq);
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lm_irqinfo
|
||||
*
|
||||
@@ -316,6 +345,9 @@ void up_irqinitialize(void)
|
||||
|
||||
#ifdef CONFIG_ARCH_IRQPRIO
|
||||
/* up_prioritize_irq(LM_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
|
||||
#endif
|
||||
#ifdef CONFIG_ARMV7M_USEBASEPRI
|
||||
up_prioritize_irq(LM_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY);
|
||||
#endif
|
||||
|
||||
/* If the MPU is enabled, then attach and enable the Memory Management
|
||||
@@ -433,7 +465,14 @@ int up_prioritize_irq(int irq, int priority)
|
||||
uint32_t regval;
|
||||
int shift;
|
||||
|
||||
DEBUGASSERT(irq >= LM_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
|
||||
#ifdef CONFIG_ARMV7M_USEBASEPRI
|
||||
DEBUGASSERT(irq >= LM_IRQ_MEMFAULT && irq < NR_IRQS &&
|
||||
priority >= NVIC_SYSH_DISABLE_PRIORITY &&
|
||||
priority <= NVIC_SYSH_PRIORITY_MIN);
|
||||
#else
|
||||
DEBUGASSERT(irq >= LM_IRQ_MEMFAULT && irq < NR_IRQS &&
|
||||
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
|
||||
#endif
|
||||
|
||||
if (irq < LM_IRQ_INTERRUPTS)
|
||||
{
|
||||
|
||||
@@ -41,28 +41,18 @@
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <arch/lpc17xx/chip.h>
|
||||
|
||||
/* Include only the memory map. Other chip hardware files should then include this
|
||||
* file for the proper setup
|
||||
/* Include the memory map and the chip definitions file. Other chip hardware files
|
||||
* should then include this file for the proper setup.
|
||||
*/
|
||||
|
||||
#include <arch/lpc17xx/chip.h>
|
||||
#include "chip/lpc17_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* NVIC priority levels *************************************************************/
|
||||
/* Each priority field holds a priority value, 0-31. The lower the value, the greater
|
||||
* the priority of the corresponding interrupt. The processor implements only
|
||||
* bits[7:3] of each field, bits[2:0] read as zero and ignore writes.
|
||||
*/
|
||||
|
||||
#define NVIC_SYSH_PRIORITY_MIN 0xf8 /* All bits[7:3] set is minimum priority */
|
||||
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
|
||||
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* arch/arm/src/lpc17/lpc17_irq.c
|
||||
* arch/arm/src/chip/lpc17_irq.c
|
||||
*
|
||||
* Copyright (C) 2010-2011 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@@ -189,6 +189,35 @@ static int lpc17_reserved(int irq, FAR void *context)
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_prioritize_irq
|
||||
*
|
||||
* Description:
|
||||
* Set the priority of an exception. This function may be needed
|
||||
* internally even if support for prioritized interrupts is not enabled.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI)
|
||||
static int up_prioritize_irq(int irq, int priority)
|
||||
{
|
||||
uint32_t regaddr;
|
||||
uint32_t regval;
|
||||
int shift;
|
||||
|
||||
irq -= 4;
|
||||
regaddr = NVIC_SYSH_PRIORITY(irq);
|
||||
regval = getreg32(regaddr);
|
||||
shift = ((irq & 3) << 3);
|
||||
regval &= ~(0xff << shift);
|
||||
regval |= (priority << shift);
|
||||
putreg32(regval, regaddr);
|
||||
|
||||
stm32_dumpnvic("prioritize", irq);
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_irqinfo
|
||||
*
|
||||
@@ -304,6 +333,9 @@ void up_irqinitialize(void)
|
||||
|
||||
#ifdef CONFIG_ARCH_IRQPRIO
|
||||
/* up_prioritize_irq(LPC17_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
|
||||
#endif
|
||||
#ifdef CONFIG_ARMV7M_USEBASEPRI
|
||||
up_prioritize_irq(LPC17_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY);
|
||||
#endif
|
||||
|
||||
/* If the MPU is enabled, then attach and enable the Memory Management
|
||||
@@ -448,7 +480,14 @@ int up_prioritize_irq(int irq, int priority)
|
||||
uint32_t regval;
|
||||
int shift;
|
||||
|
||||
DEBUGASSERT(irq >= LPC17_IRQ_MEMFAULT && irq < LPC17_IRQ_NIRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
|
||||
#ifdef CONFIG_ARMV7M_USEBASEPRI
|
||||
DEBUGASSERT(irq >= LPC17_IRQ_MEMFAULT && irq < LPC17_IRQ_NIRQS &&
|
||||
priority >= NVIC_SYSH_DISABLE_PRIORITY &&
|
||||
priority <= NVIC_SYSH_PRIORITY_MIN);
|
||||
#else
|
||||
DEBUGASSERT(irq >= LPC17_IRQ_MEMFAULT && irq < LPC17_IRQ_NIRQS &&
|
||||
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
|
||||
#endif
|
||||
|
||||
if (irq < LPC17_IRQ_EXTINT)
|
||||
{
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc43xx/chip.h
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2012-2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@@ -141,23 +141,6 @@
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* NVIC priority levels *************************************************************/
|
||||
/* Each priority field holds a priority value, 0-31. The lower the value, the greater
|
||||
* the priority of the corresponding interrupt.
|
||||
*
|
||||
* The Cortex-M4 core supports up to 53 interrupts an 8 prgrammable interrupt
|
||||
* priority levels; The Cortex-M0 core supports up to 32 interrupts with 4
|
||||
* programmable interrupt priorities.
|
||||
*/
|
||||
|
||||
#define LPC43M4_SYSH_PRIORITY_MIN 0xe0 /* All bits[7:5] set is minimum priority */
|
||||
#define LPC43M4_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
|
||||
#define LPC43M4_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
|
||||
|
||||
#define LPC43M0_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */
|
||||
#define LPC43M0_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
|
||||
#define LPC43M0_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* arch/arm/src/lpc43/lpc43_irq.c
|
||||
* arch/arm/src/chip/lpc43_irq.c
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2012-2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@@ -191,6 +191,35 @@ static int lpc43_reserved(int irq, FAR void *context)
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_prioritize_irq
|
||||
*
|
||||
* Description:
|
||||
* Set the priority of an exception. This function may be needed
|
||||
* internally even if support for prioritized interrupts is not enabled.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI)
|
||||
static int up_prioritize_irq(int irq, int priority)
|
||||
{
|
||||
uint32_t regaddr;
|
||||
uint32_t regval;
|
||||
int shift;
|
||||
|
||||
irq -= 4;
|
||||
regaddr = NVIC_SYSH_PRIORITY(irq);
|
||||
regval = getreg32(regaddr);
|
||||
shift = ((irq & 3) << 3);
|
||||
regval &= ~(0xff << shift);
|
||||
regval |= (priority << shift);
|
||||
putreg32(regval, regaddr);
|
||||
|
||||
stm32_dumpnvic("prioritize", irq);
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc43_irqinfo
|
||||
*
|
||||
@@ -333,6 +362,9 @@ void up_irqinitialize(void)
|
||||
|
||||
#ifdef CONFIG_ARCH_IRQPRIO
|
||||
/* up_prioritize_irq(LPC43_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
|
||||
#endif
|
||||
#ifdef CONFIG_ARMV7M_USEBASEPRI
|
||||
up_prioritize_irq(LPC43_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY);
|
||||
#endif
|
||||
|
||||
/* If the MPU is enabled, then attach and enable the Memory Management
|
||||
@@ -477,8 +509,14 @@ int up_prioritize_irq(int irq, int priority)
|
||||
uint32_t regval;
|
||||
int shift;
|
||||
|
||||
#ifdef CONFIG_ARMV7M_USEBASEPRI
|
||||
DEBUGASSERT(irq >= LPC43_IRQ_MEMFAULT && irq < NR_IRQS &&
|
||||
(unsigned)priority <= LPC43M4_SYSH_PRIORITY_MIN);
|
||||
priority >= NVIC_SYSH_DISABLE_PRIORITY &&
|
||||
priority <= NVIC_SYSH_PRIORITY_MIN);
|
||||
#else
|
||||
DEBUGASSERT(irq >= LPC43_IRQ_MEMFAULT && irq < NR_IRQS &&
|
||||
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
|
||||
#endif
|
||||
|
||||
if (irq < LPC43_IRQ_EXTINT)
|
||||
{
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/sam3u/chip.h
|
||||
*
|
||||
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@@ -42,46 +42,17 @@
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/* Include the memory map and the chip definitions file. Other chip hardware files
|
||||
* should then include this file for the proper setup.
|
||||
*/
|
||||
|
||||
#include <arch/sam3u/chip.h>
|
||||
#include "sam3u_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Get customizations for each supported chip */
|
||||
|
||||
#ifdef CONFIG_ARCH_CHIP_AT91SAM3U4E
|
||||
/* Internal memory */
|
||||
|
||||
# define CONFIG_SAM3U_SRAM0_SIZE 0x00008000 /* 32Kb */
|
||||
# define CONFIG_SAM3U_SRAM1_SIZE 0x00004000 /* 16Kb */
|
||||
# define CONFIG_SAM3U_NFCSRAM_SIZE 0x00001000 /* 4Kb */
|
||||
|
||||
/* DMA */
|
||||
|
||||
# define CONFIG_SAM3U_NDMACHAN 4 /* 4 DMA Channels */
|
||||
|
||||
/* Memory card interface */
|
||||
|
||||
# define CONFIG_SAM3U_MCI2 1
|
||||
#else
|
||||
# error "Unknown SAM3U chip type"
|
||||
#endif
|
||||
|
||||
/* Include only the memory map. Other chip hardware files should then include this
|
||||
* file for the proper setup
|
||||
*/
|
||||
|
||||
#include "sam3u_memorymap.h"
|
||||
|
||||
/* NVIC priority levels *************************************************************/
|
||||
/* Each priority field holds a priority value, 0-15. The lower the value, the greater
|
||||
* the priority of the corresponding interrupt. The processor implements only
|
||||
* bits[7:4] of each field, bits[3:0] read as zero and ignore writes.
|
||||
*/
|
||||
|
||||
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */
|
||||
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
|
||||
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* arch/arm/src/sam3u/sam3u_irq.c
|
||||
* arch/arm/src/chip/sam3u_irq.c
|
||||
*
|
||||
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@@ -184,6 +184,35 @@ static int sam3u_reserved(int irq, FAR void *context)
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_prioritize_irq
|
||||
*
|
||||
* Description:
|
||||
* Set the priority of an exception. This function may be needed
|
||||
* internally even if support for prioritized interrupts is not enabled.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI)
|
||||
static int up_prioritize_irq(int irq, int priority)
|
||||
{
|
||||
uint32_t regaddr;
|
||||
uint32_t regval;
|
||||
int shift;
|
||||
|
||||
irq -= 4;
|
||||
regaddr = NVIC_SYSH_PRIORITY(irq);
|
||||
regval = getreg32(regaddr);
|
||||
shift = ((irq & 3) << 3);
|
||||
regval &= ~(0xff << shift);
|
||||
regval |= (priority << shift);
|
||||
putreg32(regval, regaddr);
|
||||
|
||||
stm32_dumpnvic("prioritize", irq);
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam3u_irqinfo
|
||||
*
|
||||
@@ -295,6 +324,9 @@ void up_irqinitialize(void)
|
||||
|
||||
#ifdef CONFIG_ARCH_IRQPRIO
|
||||
/* up_prioritize_irq(SAM3U_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
|
||||
#endif
|
||||
#ifdef CONFIG_ARMV7M_USEBASEPRI
|
||||
up_prioritize_irq(SAM3U_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY);
|
||||
#endif
|
||||
|
||||
/* If the MPU is enabled, then attach and enable the Memory Management
|
||||
@@ -436,7 +468,14 @@ int up_prioritize_irq(int irq, int priority)
|
||||
uint32_t regval;
|
||||
int shift;
|
||||
|
||||
DEBUGASSERT(irq >= SAM3U_IRQ_MEMFAULT && irq < SAM3U_IRQ_NIRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
|
||||
#ifdef CONFIG_ARMV7M_USEBASEPRI
|
||||
DEBUGASSERT(irq >= SAM3U_IRQ_MEMFAULT && irq < SAM3U_IRQ_NIRQS &&
|
||||
priority >= NVIC_SYSH_DISABLE_PRIORITY &&
|
||||
priority <= NVIC_SYSH_PRIORITY_MIN);
|
||||
#else
|
||||
DEBUGASSERT(irq >= SAM3U_IRQ_MEMFAULT && irq < SAM3U_IRQ_NIRQS &&
|
||||
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
|
||||
#endif
|
||||
|
||||
if (irq < SAM3U_IRQ_EXTINT)
|
||||
{
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
||||
@@ -68,12 +68,6 @@
|
||||
# undef CONFIG_DEBUG_QENCODER
|
||||
#endif
|
||||
|
||||
/* NVIC priority levels *************************************************************/
|
||||
|
||||
#define NVIC_SYSH_PRIORITY_MIN 0xff /* All bits set in minimum priority */
|
||||
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
|
||||
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
|
||||
|
||||
/* Peripherals **********************************************************************/
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* arch/arm/src/stm32/stm32_irq.c
|
||||
* arch/arm/src/chip/stm32_irq.c
|
||||
*
|
||||
* Copyright (C) 2009-2012 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2009-2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@@ -194,6 +194,35 @@ static int stm32_reserved(int irq, FAR void *context)
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_prioritize_irq
|
||||
*
|
||||
* Description:
|
||||
* Set the priority of an exception. This function may be needed
|
||||
* internally even if support for prioritized interrupts is not enabled.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if !defined(CONFIG_ARCH_IRQPRIO) && defined(CONFIG_ARMV7M_USEBASEPRI)
|
||||
static int up_prioritize_irq(int irq, int priority)
|
||||
{
|
||||
uint32_t regaddr;
|
||||
uint32_t regval;
|
||||
int shift;
|
||||
|
||||
irq -= 4;
|
||||
regaddr = NVIC_SYSH_PRIORITY(irq);
|
||||
regval = getreg32(regaddr);
|
||||
shift = ((irq & 3) << 3);
|
||||
regval &= ~(0xff << shift);
|
||||
regval |= (priority << shift);
|
||||
putreg32(regval, regaddr);
|
||||
|
||||
stm32_dumpnvic("prioritize", irq);
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_irqinfo
|
||||
*
|
||||
@@ -334,6 +363,9 @@ void up_irqinitialize(void)
|
||||
|
||||
#ifdef CONFIG_ARCH_IRQPRIO
|
||||
/* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
|
||||
#endif
|
||||
#ifdef CONFIG_ARMV7M_USEBASEPRI
|
||||
up_prioritize_irq(STM32_IRQ_SVCALL, NVIC_SYSH_SVCALL_PRIORITY);
|
||||
#endif
|
||||
|
||||
/* If the MPU is enabled, then attach and enable the Memory Management
|
||||
@@ -451,7 +483,14 @@ int up_prioritize_irq(int irq, int priority)
|
||||
uint32_t regval;
|
||||
int shift;
|
||||
|
||||
DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
|
||||
#ifdef CONFIG_ARMV7M_USEBASEPRI
|
||||
DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS &&
|
||||
priority >= NVIC_SYSH_DISABLE_PRIORITY &&
|
||||
priority <= NVIC_SYSH_PRIORITY_MIN);
|
||||
#else
|
||||
DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS &&
|
||||
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
|
||||
#endif
|
||||
|
||||
if (irq < STM32_IRQ_INTERRUPTS)
|
||||
{
|
||||
|
||||
Reference in New Issue
Block a user