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Add support for STM32F100x value line. Contributed by Mike Smith. Still missing a file
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4955 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
@@ -49,7 +49,9 @@
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/* Include the chip pin configuration file */
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#if defined(CONFIG_STM32_STM32F10XX)
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# if defined(CONFIG_ARCH_CHIP_STM32F103ZET6)
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# if defined(CONFIG_STM32_VALUELINE)
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# include "chip/stm32f100_pinmap.h"
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# elif defined(CONFIG_ARCH_CHIP_STM32F103ZET6)
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# include "chip/stm32f103ze_pinmap.h"
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# elif defined(CONFIG_ARCH_CHIP_STM32F103RET6)
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# include "chip/stm32f103re_pinmap.h"
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@@ -52,6 +52,9 @@
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#define STM32_RCC_APB1ENR_OFFSET 0x001c /* APB1 Peripheral Clock enable register */
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#define STM32_RCC_BDCR_OFFSET 0x0020 /* Backup domain control register */
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#define STM32_RCC_CSR_OFFSET 0x0024 /* Control/status register */
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#ifdef CONFIG_STM32_VALUELINE
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# define STM32_RCC_CFGR2_OFFSET 0x002c /* Clock configuration register 2 */
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#endif
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/* Register Addresses ***************************************************************/
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@@ -65,6 +68,9 @@
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#define STM32_RCC_APB1ENR (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET)
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#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET)
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#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET)
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#ifdef CONFIG_STM32_VALUELINE
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# define STM32_RCC_CFGR2 (STM32_RCC_BASE+STM32_RCC_CFGR2_OFFSET)
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#endif
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/* Register Bitfield Definitions ****************************************************/
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@@ -295,5 +301,28 @@
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#define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: Window watchdog reset flag */
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#define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-Power reset flag */
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#ifdef CONFIG_STM32_VALUELINE
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/* Clock configuration register 2 */
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# define RCC_CFGR2_PREDIV1d1 0 /* HSE input not divided */
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# define RCC_CFGR2_PREDIV1d2 1 /* HSE input divided by 2 */
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# define RCC_CFGR2_PREDIV1d3 2 /* HSE input divided by 3 */
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# define RCC_CFGR2_PREDIV1d4 3 /* HSE input divided by 4 */
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# define RCC_CFGR2_PREDIV1d5 4 /* HSE input divided by 5 */
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# define RCC_CFGR2_PREDIV1d6 5 /* HSE input divided by 6 */
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# define RCC_CFGR2_PREDIV1d7 6 /* HSE input divided by 7 */
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# define RCC_CFGR2_PREDIV1d8 7 /* HSE input divided by 8 */
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# define RCC_CFGR2_PREDIV1d9 8 /* HSE input divided by 9 */
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# define RCC_CFGR2_PREDIV1d10 9 /* HSE input divided by 10 */
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# define RCC_CFGR2_PREDIV1d11 10 /* HSE input divided by 11 */
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# define RCC_CFGR2_PREDIV1d12 11 /* HSE input divided by 12 */
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# define RCC_CFGR2_PREDIV1d13 12 /* HSE input divided by 13 */
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# define RCC_CFGR2_PREDIV1d14 13 /* HSE input divided by 14 */
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# define RCC_CFGR2_PREDIV1d15 14 /* HSE input divided by 15 */
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# define RCC_CFGR2_PREDIV1d16 15 /* HSE input divided by 16 */
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#endif
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#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_RCC_H */
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@@ -43,7 +43,23 @@
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* the interrupt vectors and handlers in their final form.
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*/
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#ifdef CONFIG_STM32_CONNECTIVITY_LINE
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#if defined(CONFIG_STM32_VALUELINE)
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/* If the common ARMv7-M vector handling is used, then all it needs is the following
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* definition that provides the number of supported vectors.
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*/
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#ifdef CONFIG_ARMV7M_CMNVECTOR
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/* Reserve 60 interrupt table entries for I/O interrupts. */
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# define ARMV7M_PERIPHERAL_INTERRUPTS 60
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#else
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# error This target requires CONFIG_ARMV7M_CMNVECTOR
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#endif /* CONFIG_ARMV7M_CMNVECTOR */
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#elif defined(CONFIG_STM32_CONNECTIVITYLINE)
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/* If the common ARMv7-M vector handling is used, then all it needs is the following
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* definition that provides the number of supported vectors.
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@@ -119,7 +135,7 @@ VECTOR(stm32_can2sce, STM32_IRQ_CAN2SCE) /* Vector 16+66: CAN2 SCE inter
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VECTOR(stm32_otgfs, STM32_IRQ_OTGFS) /* Vector 16+67: USB On The Go FS global interrupt */
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#endif /* CONFIG_ARMV7M_CMNVECTOR */
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#else /* CONFIG_STM32_CONNECTIVITY_LINE */
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#else /* CONFIG_STM32_CONNECTIVITYLINE */
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/* If the common ARMv7-M vector handling is used, then all it needs is the following
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* definition that provides the number of supported vectors.
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@@ -195,4 +211,4 @@ VECTOR(stm32_dma2ch3, STM32_IRQ_DMA2CH3) /* Vector 16+58: DMA2 Channel 3
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VECTOR(stm32_dma2ch45, STM32_IRQ_DMA2CH45) /* Vector 16+59: DMA2 Channel 4&5 global interrupt */
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#endif /* CONFIG_ARMV7M_CMNVECTOR */
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#endif /* CONFIG_STM32_CONNECTIVITY_LINE */
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#endif /* CONFIG_STM32_CONNECTIVITYLINE */
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@@ -415,92 +415,128 @@ static inline void rcc_enableapb2(void)
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static inline void stm32_stdclockconfig(void)
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{
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uint32_t regval;
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volatile int32_t timeout;
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/* Enable External High-Speed Clock (HSE) */
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regval = getreg32(STM32_RCC_CR);
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regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */
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regval |= RCC_CR_HSEON; /* Enable HSE */
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putreg32(regval, STM32_RCC_CR);
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/* Wait until the HSE is ready (or until a timeout elapsed) */
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/* If the PLL is using the HSE, or the HSE is the system clock */
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#if (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE)
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for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
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{
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/* Check if the HSERDY flag is the set in the CR */
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volatile int32_t timeout;
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if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
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/* Enable External High-Speed Clock (HSE) */
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regval = getreg32(STM32_RCC_CR);
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regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */
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regval |= RCC_CR_HSEON; /* Enable HSE */
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putreg32(regval, STM32_RCC_CR);
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/* Wait until the HSE is ready (or until a timeout elapsed) */
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for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
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{
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/* If so, then break-out with timeout > 0 */
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/* Check if the HSERDY flag is the set in the CR */
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break;
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if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
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{
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/* If so, then break-out with timeout > 0 */
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break;
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}
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}
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if (timeout == 0)
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{
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/* In the case of a timeout starting the HSE, we really don't have a
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* strategy. This is almost always a hardware failure or misconfiguration.
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*/
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return;
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}
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}
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/* Check for a timeout. If this timeout occurs, then we are hosed. We
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* have no real back-up plan, although the following logic makes it look
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* as though we do.
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*/
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/* If this is a value-line part and we are using the HSE as the PLL */
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if (timeout > 0)
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{
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/* Enable FLASH prefetch buffer and 2 wait states */
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# if defined(CONFIG_STM32_VALUELINE) && (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC)
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regval = getreg32(STM32_FLASH_ACR);
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regval &= ~FLASH_ACR_LATENCY_MASK;
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regval |= (FLASH_ACR_LATENCY_2|FLASH_ACR_PRTFBE);
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putreg32(regval, STM32_FLASH_ACR);
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# if (STM32_CFGR_PLLXTPRE >> 17) != (STM32_CFGR2_PREDIV1 & 1)
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# error STM32_CFGR_PLLXTPRE must match the LSB of STM32_CFGR2_PREDIV1
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# endif
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/* Set the HCLK source/divider */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_HPRE_MASK;
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regval |= STM32_RCC_CFGR_HPRE;
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putreg32(regval, STM32_RCC_CFGR);
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/* Set the HSE prescaler */
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/* Set the PCLK2 divider */
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regval = STM32_CFGR2_PREDIV1;
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putreg32(regval, STM32_RCC_CFGR2);
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_PPRE2_MASK;
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regval |= STM32_RCC_CFGR_PPRE2;
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putreg32(regval, STM32_RCC_CFGR);
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/* Set the PCLK1 divider */
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# endif
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#endif
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_PPRE1_MASK;
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regval |= STM32_RCC_CFGR_PPRE1;
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putreg32(regval, STM32_RCC_CFGR);
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/* Set the PLL divider and multipler */
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/* Value-line devices don't implement flash prefetch/waitstates */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~(RCC_CFGR_PLLSRC|RCC_CFGR_PLLXTPRE|RCC_CFGR_PLLMUL_MASK);
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regval |= (STM32_CFGR_PLLSRC|STM32_CFGR_PLLXTPRE|STM32_CFGR_PLLMUL);
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putreg32(regval, STM32_RCC_CFGR);
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/* Enable the PLL */
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#ifndef CONFIG_STM32_VALUELINE
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regval = getreg32(STM32_RCC_CR);
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regval |= RCC_CR_PLLON;
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putreg32(regval, STM32_RCC_CR);
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/* Wait until the PLL is ready */
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while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
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/* Select the system clock source (probably the PLL) */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_SW_MASK;
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regval |= STM32_SYSCLK_SW;
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putreg32(regval, STM32_RCC_CFGR);
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/* Enable FLASH prefetch buffer and 2 wait states */
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/* Wait until the selected source is used as the system clock source */
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while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
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}
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regval = getreg32(STM32_FLASH_ACR);
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regval &= ~FLASH_ACR_LATENCY_MASK;
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regval |= (FLASH_ACR_LATENCY_2|FLASH_ACR_PRTFBE);
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putreg32(regval, STM32_FLASH_ACR);
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#endif
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/* Set the HCLK source/divider */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_HPRE_MASK;
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regval |= STM32_RCC_CFGR_HPRE;
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putreg32(regval, STM32_RCC_CFGR);
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/* Set the PCLK2 divider */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_PPRE2_MASK;
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regval |= STM32_RCC_CFGR_PPRE2;
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putreg32(regval, STM32_RCC_CFGR);
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/* Set the PCLK1 divider */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_PPRE1_MASK;
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regval |= STM32_RCC_CFGR_PPRE1;
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putreg32(regval, STM32_RCC_CFGR);
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/* If we are using the PLL, configure and start it */
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#if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL
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/* Set the PLL divider and multipler */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~(RCC_CFGR_PLLSRC|RCC_CFGR_PLLXTPRE|RCC_CFGR_PLLMUL_MASK);
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regval |= (STM32_CFGR_PLLSRC|STM32_CFGR_PLLXTPRE|STM32_CFGR_PLLMUL);
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putreg32(regval, STM32_RCC_CFGR);
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/* Enable the PLL */
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regval = getreg32(STM32_RCC_CR);
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regval |= RCC_CR_PLLON;
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putreg32(regval, STM32_RCC_CR);
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/* Wait until the PLL is ready */
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while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
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#endif
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/* Select the system clock source (probably the PLL) */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_SW_MASK;
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regval |= STM32_SYSCLK_SW;
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putreg32(regval, STM32_RCC_CFGR);
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/* Wait until the selected source is used as the system clock source */
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while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
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}
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#endif
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