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STM32 demo - bxCAN GPIO initialization fixed

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This commit is contained in:
Pavel Kirienko 2015-10-10 17:09:52 +03:00
parent 076104877a
commit 3dffcc007b
2 changed files with 21 additions and 4 deletions
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15
libuavcan_drivers/stm32/test_stm32f107/src/board/board.cpp
View File

@ -28,7 +28,9 @@ namespace board
void init()
{
halInit();
chibios_rt::System::init();
sdStart(&STDOUT_SD, NULL);
}
@ -79,6 +81,19 @@ void boardInit(void)
AFIO_MAPR_CAN_REMAP_REMAP3 |
AFIO_MAPR_CAN2_REMAP |
AFIO_MAPR_USART2_REMAP;
/*
* Enabling the CAN controllers, then configuring GPIO functions for CAN_TX.
* Order matters, otherwise the CAN_TX pins will twitch, disturbing the CAN bus.
* This is why we can't perform this initialization using ChibiOS GPIO configuration.
*/
RCC->APB1ENR |= RCC_APB1ENR_CAN1EN;
#if UAVCAN_STM32_NUM_IFACES > 1
RCC->APB1ENR |= RCC_APB1ENR_CAN2EN;
#endif
palSetPadMode(GPIOD, 1, PAL_MODE_STM32_ALTERNATE_PUSHPULL);
palSetPadMode(GPIOB, 6, PAL_MODE_STM32_ALTERNATE_PUSHPULL);
}
}

10
libuavcan_drivers/stm32/test_stm32f107/src/sys/board.h
View File

@ -20,6 +20,8 @@
#define GPIO_PORT_LED GPIOB
#define GPIO_PIN_LED 9
// GPIOD 10 is configured as OUTPUT, it is used as board reboot monitor.
/*
* I/O ports initial setup, this configuration is established soon after reset
* in the initialization code.
@ -48,7 +50,7 @@
#define VAL_GPIOACRH 0x88888888 // 15..8
#define VAL_GPIOAODR 0x00000000
#define VAL_GPIOBCRL 0x8B488888
#define VAL_GPIOBCRL 0x84488888 // CAN2 TX initialized as INPUT, it must be configured later!
#define VAL_GPIOBCRH 0x88888828
#define VAL_GPIOBODR 0x00000000
@ -56,9 +58,9 @@
#define VAL_GPIOCCRH 0x88888888
#define VAL_GPIOCODR 0x00000000
#define VAL_GPIODCRL 0x88b888B4
#define VAL_GPIODCRH 0x88888888
#define VAL_GPIODODR 0x00000000
#define VAL_GPIODCRL 0x88b88844 // CAN1 TX initialized as INPUT, it must be configured later!
#define VAL_GPIODCRH 0x88888288
#define VAL_GPIODODR ((1 << 10))
#define VAL_GPIOECRL 0x88888888
#define VAL_GPIOECRH 0x88888888