mirror of
https://gitee.com/mirrors_PX4/PX4-Autopilot.git
synced 2026-10-27 09:43:34 +08:00
Merge Nuttx r5554
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px4dev
@@ -60,6 +60,10 @@
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# include <arch/armv7-m/irq_lazyfpu.h>
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#endif
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#ifdef CONFIG_ARMV7M_USEBASEPRI
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# include <arch/chip/chip.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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@@ -114,7 +118,11 @@ struct xcptcontext
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*/
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uint32_t saved_pc;
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#ifdef CONFIG_ARMV7M_USEBASEPRI
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uint32_t saved_basepri;
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#else
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uint32_t saved_primask;
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#endif
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uint32_t saved_xpsr;
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#endif
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@@ -130,65 +138,7 @@ struct xcptcontext
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#ifndef __ASSEMBLY__
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/* Disable IRQs */
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static inline void irqdisable(void) inline_function;
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static inline void irqdisable(void)
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{
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__asm__ __volatile__ ("\tcpsid i\n");
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}
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/* Save the current primask state & disable IRQs */
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static inline irqstate_t irqsave(void) inline_function;
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static inline irqstate_t irqsave(void)
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{
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unsigned short primask;
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/* Return the current value of primask register and set
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* bit 0 of the primask register to disable interrupts
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*/
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__asm__ __volatile__
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(
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"\tmrs %0, primask\n"
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"\tcpsid i\n"
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: "=r" (primask)
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:
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: "memory");
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return primask;
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}
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/* Enable IRQs */
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static inline void irqenable(void) inline_function;
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static inline void irqenable(void)
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{
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__asm__ __volatile__ ("\tcpsie i\n");
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}
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/* Restore saved primask state */
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static inline void irqrestore(irqstate_t primask) inline_function;
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static inline void irqrestore(irqstate_t primask)
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{
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/* If bit 0 of the primask is 0, then we need to restore
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* interupts.
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*/
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__asm__ __volatile__
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(
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"\ttst %0, #1\n"
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"\tbne 1f\n"
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"\tcpsie i\n"
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"1:\n"
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:
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: "r" (primask)
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: "memory");
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}
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/* Get/set the primask register */
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/* Get/set the PRIMASK register */
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static inline uint8_t getprimask(void) inline_function;
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static inline uint8_t getprimask(void)
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@@ -215,7 +165,11 @@ static inline void setprimask(uint32_t primask)
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: "memory");
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}
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/* Get/set the basepri register */
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/* Get/set the BASEPRI register. The BASEPRI register defines the minimum
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* priority for exception processing. When BASEPRI is set to a nonzero
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* value, it prevents the activation of all exceptions with the same or
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* lower priority level as the BASEPRI value.
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*/
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static inline uint8_t getbasepri(void) inline_function;
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static inline uint8_t getbasepri(void)
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@@ -243,6 +197,82 @@ static inline void setbasepri(uint32_t basepri)
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: "memory");
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}
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/* Disable IRQs */
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static inline void irqdisable(void) inline_function;
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static inline void irqdisable(void)
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{
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#ifdef CONFIG_ARMV7M_USEBASEPRI
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setbasepri(NVIC_SYSH_DISABLE_PRIORITY);
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#else
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__asm__ __volatile__ ("\tcpsid i\n");
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#endif
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}
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/* Save the current primask state & disable IRQs */
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static inline irqstate_t irqsave(void) inline_function;
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static inline irqstate_t irqsave(void)
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{
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#ifdef CONFIG_ARMV7M_USEBASEPRI
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uint8_t basepri = getbasepri();
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setbasepri(NVIC_SYSH_DISABLE_PRIORITY);
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return (irqstate_t)basepri;
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#else
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unsigned short primask;
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/* Return the current value of primask register and set
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* bit 0 of the primask register to disable interrupts
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*/
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__asm__ __volatile__
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(
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"\tmrs %0, primask\n"
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"\tcpsid i\n"
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: "=r" (primask)
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:
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: "memory");
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return primask;
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#endif
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}
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/* Enable IRQs */
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static inline void irqenable(void) inline_function;
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static inline void irqenable(void)
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{
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setbasepri(0);
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__asm__ __volatile__ ("\tcpsie i\n");
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}
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/* Restore saved primask state */
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static inline void irqrestore(irqstate_t flags) inline_function;
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static inline void irqrestore(irqstate_t flags)
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{
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#ifdef CONFIG_ARMV7M_USEBASEPRI
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setbasepri((uint32_t)flags);
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#else
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/* If bit 0 of the primask is 0, then we need to restore
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* interupts.
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*/
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__asm__ __volatile__
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(
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"\ttst %0, #1\n"
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"\tbne 1f\n"
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"\tcpsie i\n"
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"1:\n"
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:
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: "r" (flags)
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: "memory");
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#endif
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}
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/* Get/set IPSR */
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static inline uint32_t getipsr(void) inline_function;
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@@ -51,7 +51,11 @@
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*/
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#define REG_R13 (0) /* R13 = SP at time of interrupt */
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#define REG_PRIMASK (1) /* PRIMASK */
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#ifdef CONFIG_ARMV7M_USEBASEPRI
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# define REG_BASEPRI (1) /* BASEPRI */
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#else
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# define REG_PRIMASK (1) /* PRIMASK */
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#endif
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#define REG_R4 (2) /* R4 */
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#define REG_R5 (3) /* R5 */
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#define REG_R6 (4) /* R6 */
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@@ -51,7 +51,11 @@
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*/
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#define REG_R13 (0) /* R13 = SP at time of interrupt */
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#define REG_PRIMASK (1) /* PRIMASK */
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#ifdef CONFIG_ARMV7M_USEBASEPRI
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# define REG_BASEPRI (1) /* BASEPRI */
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#else
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# define REG_PRIMASK (1) /* PRIMASK */
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#endif
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#define REG_R4 (2) /* R4 */
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#define REG_R5 (3) /* R5 */
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#define REG_R6 (4) /* R6 */
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@@ -183,9 +183,43 @@
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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/* STM32 F103 Medium Density Family *************************************************/
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/* STM32F103RB is in the Medium-density performance line and is provided in 64 pin
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* packages with 128K Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces
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*/
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#elif defined(CONFIG_ARCH_CHIP_STM32F103RBT6)
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# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
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# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
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# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
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# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
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# undef CONFIG_STM32_VALUELINE /* STM32F100x */
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# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
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# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
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# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
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# define STM32_NFSMC 0 /* FSMC */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM 3 /* General timers TIM2,3,4 */
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# define STM32_NBTIM 0 /* Two basic timers TIM6 and TIM7 */
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# define STM32_NDMA 1 /* DMA1 */
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# define STM32_NSPI 2 /* SPI1-2 */
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# define STM32_NI2S 0 /* No I2S (?) */
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# define STM32_NUSART 3 /* USART1-3 */
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# define STM32_NI2C 2 /* I2C1-2 */
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# define STM32_NCAN 1 /* bxCAN1 */
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# define STM32_NSDIO 0 /* No SDIO */
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# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
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# define STM32_NGPIO 51 /* GPIOA-E */
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# define STM32_NADC 2 /* ADC1-2 */
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# define STM32_NDAC 0 /* No DAC */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NTHERNET 0 /* No ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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/* STM32 F103 High Density Family ***************************************************/
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/* STM32F103RC, STM32F103RD, and STM32F103RE are all provided in 64 pin packages and differ
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* only in the available FLASH and SRAM.
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/* STM32F103RC, STM32F103RD, and STM32F103RE are all provided in 64 pin packages and
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* differ only in the available FLASH and SRAM.
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*/
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#elif defined(CONFIG_ARCH_CHIP_STM32F103RET6)
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@@ -658,5 +692,15 @@
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# error "Unsupported STM32 chip"
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#endif
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/* NVIC priority levels *************************************************************/
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#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
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#define NVIC_SYSH_DISABLE_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
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#define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
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#endif /* __ARCH_ARM_INCLUDE_STM32_CHIP_H */
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@@ -44,6 +44,8 @@
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Definitions
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****************************************************************************/
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@@ -87,7 +89,11 @@ typedef unsigned int _uintptr_t;
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*/
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#ifdef __thumb2__
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#ifdef CONFIG_ARMV7M_USEBASEPRI
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typedef unsigned char irqstate_t;
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#else
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typedef unsigned short irqstate_t;
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#endif
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#else /* __thumb2__ */
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typedef unsigned int irqstate_t;
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#endif /* __thumb2__ */
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