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For STM32 PWM output on TIM1/8, need to set master output enable (MOE)
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4296 7fd9a85b-ad96-42d3-883c-3090e2eb8679
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@@ -825,6 +825,8 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
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#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM)
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#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM)
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if (priv->timtype == TIMTYPE_ADVANCED)
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if (priv->timtype == TIMTYPE_ADVANCED)
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{
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{
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uint16_t bdtr;
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/* Reset output N polarity level, output N state, output compare state,
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/* Reset output N polarity level, output N state, output compare state,
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* output compare N idle state.
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* output compare N idle state.
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*/
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*/
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@@ -841,6 +843,15 @@ static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
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cr2 &= ~(ATIM_CR2_OIS1 | ATIM_CR2_OIS1N | ATIM_CR2_OIS2 | ATIM_CR2_OIS2N |
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cr2 &= ~(ATIM_CR2_OIS1 | ATIM_CR2_OIS1N | ATIM_CR2_OIS2 | ATIM_CR2_OIS2N |
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ATIM_CR2_OIS3 | ATIM_CR2_OIS3N | ATIM_CR2_OIS4);
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ATIM_CR2_OIS3 | ATIM_CR2_OIS3N | ATIM_CR2_OIS4);
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/* Set the main output enable (MOE) bit and clear the OSSI and OSSR
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* bits in the BDTR register.
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*/
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bdtr = pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET);
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bdtr &= ~(ATIM_BDTR_OSSI | ATIM_BDTR_OSSR);
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bdtr |= ATIM_BDTR_MOE;
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pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr);
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}
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}
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#ifdef CONFIG_STM32_STM32F40XX
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#ifdef CONFIG_STM32_STM32F40XX
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else
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else
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@@ -209,17 +209,45 @@ PWM
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===
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===
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The STM3240G-Eval has no real on-board PWM devices, but the board can be
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The STM3240G-Eval has no real on-board PWM devices, but the board can be
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configured to output a pulse train using TIM4 CH2. This pin is used by
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configured to output a pulse train using timer output pins. The following
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FSMC is but is also connected to the Motor Control Connector (CN5) just
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pins have been use to generate PWM output (see board.h for some other
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for this purpose:
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candidates):
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PD13 FSMC_A18 / MC_TIM4_CH2OUT pin 33 (EnB)
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TIM4 CH2. Pin PD13 is used by the FSMC (FSMC_A18) and is also connected
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to the Motor Control Connector (CN5) just for this purpose. If FSMC is
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not enabled, then FSMC_A18 will not be used (and will be tri-stated from
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the LCD).
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FSMC must be disabled in this case! PD13 is available at:
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CONFIGURATION:
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CONFIG_STM32_TIM4=y
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CONFIG_PWM=n
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CONFIG_PWM_PULSECOUNT=n
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CONFIG_STM32_TIM4_PWM=y
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CONFIG_STM32_TIM4_CHANNEL=2
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Daughterboard Extension Connector, CN3, pin 32 - available
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ACCESS:
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TFT LCD Connector, CN19, pin 17 -- not available without removing the LCD.
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Motor Control Connector CN15, pin 33 -- not available unless you bridge SB14.
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Daughterboard Extension Connector, CN3, pin 32
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Ground is available on CN3, pin1
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NOTE: TIM4 hardware will not support pulse counting.
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TIM8 CH4: Pin PC9 is used by the microSD card (MicroSDCard_D1) and I2S
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(I2S_CKIN) but can be completely disconnected from both by opening JP16.
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CONFIGURATION:
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CONFIG_STM32_TIM8=y
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CONFIG_PWM=n
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CONFIG_PWM_PULSECOUNT=y
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CONFIG_STM32_TIM8_PWM=y
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CONFIG_STM32_TIM8_CHANNEL=4
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ACCESS:
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Daughterboard Extension Connector, CN3, pin 17
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Ground is available on CN3, pin1
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CAN
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CAN
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===
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===
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@@ -592,27 +620,27 @@ Where <subdir> is one of the following:
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CONFIG_DEBUG_ANALOG
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CONFIG_DEBUG_ANALOG
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3. This example supports the PWM test (apps/examples/pwm) but this must
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3. This example supports the PWM test (apps/examples/pwm) but this must
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be manually enabled by selecting:
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be manually enabled by selecting eeither
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CONFIG_PWM=y : Enable the generic PWM infrastructure
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CONFIG_PWM=y : Enable the generic PWM infrastructure
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CONFIG_PWM_PULSECOUNT=n : Disable to support for TIM1/8 pulse counts
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CONFIG_PWM_PULSECOUNT=n : Disable to support for TIM1/8 pulse counts
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CONFIG_STM32_TIM4=y : Enable TIM4
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CONFIG_STM32_TIM4=y : Enable TIM4
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CONFIG_STM32_TIM4_PWM=y : Use TIM4 to generate PWM output
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CONFIG_STM32_TIM4_PWM=y : Use TIM4 to generate PWM output
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CONFIG_STM32_TIM4_CHANNEL=2
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CONFIG_STM32_TIM4_CHANNEL=2 : Select output on TIM4, channel 2
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If CONFIG_STM32_FSMC is disabled, output will appear on CN3, pin 32.
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If CONFIG_STM32_FSMC is disabled, output will appear on CN3, pin 32.
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Ground is available on CN3, pin1.
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Ground is available on CN3, pin1.
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Or..
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Or..
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CONFIG_PWM=y : Enable the generic PWM infrastructure
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CONFIG_PWM=y : Enable the generic PWM infrastructure
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CONFIG_PWM_PULSECOUNT=y : Enable to support for TIM1/8 pulse counts
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CONFIG_PWM_PULSECOUNT=y : Enable to support for TIM1/8 pulse counts
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CONFIG_STM32_TIM1=y : Enable TIM1
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CONFIG_STM32_TIM8=y : Enable TIM8
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CONFIG_STM32_TIM1_PWM=y : Use TIM1 to generate PWM output
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CONFIG_STM32_TIM8_PWM=y : Use TIM8 to generate PWM output
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CONFIG_STM32_TIM1_CHANNEL=1
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CONFIG_STM32_TIM8_CHANNEL=4 : Select output on TIM8, channel 4
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If CONFIG_STM32_FSMC is disabled, output will appear on CN2, pin 24
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If CONFIG_STM32_FSMC is disabled, output will appear on CN3, pin 17
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Ground is available on CN2, pin1.
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Ground is available on CN23 pin1.
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See also include/board.h and apps/examples/README.txt
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See also include/board.h and apps/examples/README.txt
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@@ -349,13 +349,13 @@ CONFIG_STM32_ADC3_SAMPLE_FREQUENCY=100
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# PWM configuration
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# PWM configuration
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#
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#
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# The STM3240G-Eval has no real on-board PWM devices, but the board can be configured to output
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# The STM3240G-Eval has no real on-board PWM devices, but the board can be configured to output
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# a pulse train using several options (see board.h). Here the default setup is for TIM4, CH2.
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# a pulse train using several options (see board.h). Here the default setup is for TIM8, CH4.
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# Don't forget to enable CONFIG_STM32_TIM4
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# Don't forget to enable CONFIG_STM32_TIM8.
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#
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#
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CONFIG_PWM=n
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CONFIG_PWM=y
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CONFIG_PWM_PULSECOUNT=n
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CONFIG_PWM_PULSECOUNT=y
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CONFIG_STM32_TIM4_PWM=y
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CONFIG_STM32_TIM8_PWM=y
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CONFIG_STM32_TIM4_CHANNEL=2
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CONFIG_STM32_TIM8_CHANNEL=4
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#
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#
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# General build options
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# General build options
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