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stm32h7: Reset USART clock selection (#23498)

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This resets the USARTs' clock source selection to the default, in case
it has been changed by the bootloader.

This is required if booting from the ArduPilot bootloader which happens
to reset the clock selection to PLL.

Without this fix, UARTs (including the console) is garbled, so
presumably at an invalid baudrate.
This commit is contained in:
Julian Oes 2024-08-08 03:41:50 +12:00 committed by GitHub
parent 086c044f47
commit 2d99ae18ad
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GPG Key ID: B5690EEEBB952194
5 changed files with 25 additions and 1 deletions
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6
boards/cubepilot/cubeorange/nuttx-config/include/board.h
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@ -194,6 +194,12 @@
#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2 /* ADC 1 2 3 clock source */
/* UART clock selection */
/* reset to default to overwrite any changes done by any bootloader */
#define STM32_RCC_D2CCIP2R_USART234578_SEL RCC_D2CCIP2R_USART234578SEL_RCC
#define STM32_RCC_D2CCIP2R_USART16_SEL RCC_D2CCIP2R_USART16SEL_RCC
/* FLASH wait states */
#define BOARD_FLASH_WAITSTATES 2

6
boards/cubepilot/cubeorangeplus/nuttx-config/include/board.h
View File

@ -195,6 +195,12 @@
#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2 /* ADC 1 2 3 clock source */
/* UART clock selection */
/* reset to default to overwrite any changes done by any bootloader */
#define STM32_RCC_D2CCIP2R_USART234578_SEL RCC_D2CCIP2R_USART234578SEL_RCC
#define STM32_RCC_D2CCIP2R_USART16_SEL RCC_D2CCIP2R_USART16SEL_RCC
/* FLASH wait states */
#define BOARD_FLASH_WAITSTATES 2

6
boards/px4/fmu-v6c/nuttx-config/include/board.h
View File

@ -246,6 +246,12 @@
#define STM32_RCC_D2CCIP2R_USBSRC RCC_D2CCIP2R_USBSEL_PLL3
/* UART clock selection */
/* reset to default to overwrite any changes done by any bootloader */
#define STM32_RCC_D2CCIP2R_USART234578_SEL RCC_D2CCIP2R_USART234578SEL_RCC
#define STM32_RCC_D2CCIP2R_USART16_SEL RCC_D2CCIP2R_USART16SEL_RCC
/* ADC 1 2 3 clock source */
#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2

6
boards/px4/fmu-v6x/nuttx-config/include/board.h
View File

@ -250,6 +250,12 @@
#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2
/* UART clock selection */
/* reset to default to overwrite any changes done by any bootloader */
#define STM32_RCC_D2CCIP2R_USART234578_SEL RCC_D2CCIP2R_USART234578SEL_RCC
#define STM32_RCC_D2CCIP2R_USART16_SEL RCC_D2CCIP2R_USART16SEL_RCC
/* FDCAN 1 2 clock source */
#define STM32_RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_HSE /* FDCAN 1 2 clock source */

2
platforms/nuttx/NuttX/nuttx

@ -1 +1 @@
Subproject commit d3b85f3e545de3692c100143f4a9ae67762ce679
Subproject commit 5d74bc138955e6f010a38e0f87f34e9a9019aecc