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replace flexio number with actual base value

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Signed-off-by: dirksavage88 <dirksavage88@gmail.com>
This commit is contained in:
dirksavage88 2025-07-17 09:45:31 -04:00
parent e5b2584da7
commit 2d0eedc71d
4 changed files with 42 additions and 22 deletions
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12
boards/nxp/tropic-community/src/timer_config.cpp
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@ -86,12 +86,12 @@ constexpr io_timers_t io_timers[MAX_IO_TIMERS] = {
//TODO: distinguish between the different FlexIO instances
//
constexpr timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
initIOTimerChannelDshot(io_timers, {PWM::PWM2_PWM_A, PWM::Submodule0}, IOMUX::Pad::GPIO_EMC_06, GPIO_FLEXIO1_FLEXIO06_1 | FXIO_IOMUX, 1, 6), /* RevA. PWM_1 RevB. PWM1 */
initIOTimerChannelDshot(io_timers, {PWM::PWM2_PWM_B, PWM::Submodule0}, IOMUX::Pad::GPIO_EMC_07, GPIO_FLEXIO1_FLEXIO07_1 | FXIO_IOMUX, 1, 7), /* RevA. PWM_5 RevB. PWM2 */
initIOTimerChannelDshot(io_timers, {PWM::PWM2_PWM_A, PWM::Submodule1}, IOMUX::Pad::GPIO_EMC_08, GPIO_FLEXIO1_FLEXIO08_1 | FXIO_IOMUX, 1, 8), /* RevA. PWM_0 RevB. PWM3 */
initIOTimerChannelDshot(io_timers, {PWM::PWM2_PWM_B, PWM::Submodule2}, IOMUX::Pad::GPIO_B0_11, GPIO_FLEXIO2_FLEXIO11_1 | FXIO_IOMUX, 2, 11), /* RevA. PWM_4 RevB. PWM4 */
initIOTimerChannelDshot(io_timers, {PWM::PWM4_PWM_A, PWM::Submodule2}, IOMUX::Pad::GPIO_EMC_04, GPIO_FLEXIO1_FLEXIO04_1 | FXIO_IOMUX, 1, 4), /* RevA. PWM_3 RevB. PWM5 */
initIOTimerChannelDshot(io_timers, {PWM::PWM4_PWM_B, PWM::Submodule2}, IOMUX::Pad::GPIO_EMC_05, GPIO_FLEXIO1_FLEXIO05_1 | FXIO_IOMUX, 1, 5), /* RevA. PWM_2 RevB. PWM6 */
initIOTimerChannelDshot(io_timers, {PWM::PWM2_PWM_A, PWM::Submodule0}, IOMUX::Pad::GPIO_EMC_06, GPIO_FLEXIO1_FLEXIO06_1 | FXIO_IOMUX, IMXRT_FLEXIO1_BASE, 6), /* RevA. PWM_1 RevB. PWM1 */
initIOTimerChannelDshot(io_timers, {PWM::PWM2_PWM_B, PWM::Submodule0}, IOMUX::Pad::GPIO_EMC_07, GPIO_FLEXIO1_FLEXIO07_1 | FXIO_IOMUX, IMXRT_FLEXIO1_BASE, 7), /* RevA. PWM_5 RevB. PWM2 */
initIOTimerChannelDshot(io_timers, {PWM::PWM2_PWM_A, PWM::Submodule1}, IOMUX::Pad::GPIO_EMC_08, GPIO_FLEXIO1_FLEXIO08_1 | FXIO_IOMUX, IMXRT_FLEXIO1_BASE, 8), /* RevA. PWM_0 RevB. PWM3 */
initIOTimerChannelDshot(io_timers, {PWM::PWM2_PWM_B, PWM::Submodule2}, IOMUX::Pad::GPIO_B0_11, GPIO_FLEXIO2_FLEXIO11_1 | FXIO_IOMUX, IMXRT_FLEXIO2_BASE, 11), /* RevA. PWM_4 RevB. PWM4 */
initIOTimerChannelDshot(io_timers, {PWM::PWM4_PWM_A, PWM::Submodule2}, IOMUX::Pad::GPIO_EMC_04, GPIO_FLEXIO1_FLEXIO04_1 | FXIO_IOMUX, IMXRT_FLEXIO1_BASE, 4), /* RevA. PWM_3 RevB. PWM5 */
initIOTimerChannelDshot(io_timers, {PWM::PWM4_PWM_B, PWM::Submodule2}, IOMUX::Pad::GPIO_EMC_05, GPIO_FLEXIO1_FLEXIO05_1 | FXIO_IOMUX, IMXRT_FLEXIO1_BASE, 5), /* RevA. PWM_2 RevB. PWM6 */
};

48
platforms/nuttx/src/px4/nxp/imxrt/dshot/dshot.c
View File

@ -100,8 +100,6 @@ static uint32_t dshot_mask;
static uint32_t bdshot_recv_mask;
static uint32_t bdshot_parsed_recv_mask;
bool flexio1_channels = false;
bool flexio2_channels = false;
static inline uint32_t flexio_getreg32(uint32_t flexio_base, uint32_t offset)
{
@ -212,7 +210,7 @@ static int flexio1_irq_handler(int irq, void *context, void *arg)
//TODO: only do this for flexio 1 base
for (channel = 0; flags && channel < DSHOT_TIMERS; channel++) {
if ((flags & (1 << channel)) && timer_io_channels[channel].flex_io_base == 1) {
if ((flags & (1 << channel)) && timer_io_channels[channel].flex_io_base == FLEXIO1_BASE) {
disable_shifter_status_interrupts(FLEXIO1_BASE, 1 << channel);
if (dshot_inst[channel].state == DSHOT_START) {
@ -238,7 +236,7 @@ static int flexio1_irq_handler(int irq, void *context, void *arg)
for (channel = 0; flags; (channel = (channel + 1) % DSHOT_TIMERS)) {
flags = get_timer_status_flags(FLEXIO1_BASE);
if ((flags & (1 << channel)) && timer_io_channels[channel].flex_io_base == 1) {
if ((flags & (1 << channel)) && timer_io_channels[channel].flex_io_base == FLEXIO1_BASE) {
clear_timer_status_flags(FLEXIO1_BASE, 1 << channel);
if (dshot_inst[channel].state == DSHOT_12BIT_FIFO) {
@ -312,7 +310,7 @@ static int flexio2_irq_handler(int irq, void *context, void *arg)
uint32_t channel;
for (channel = 0; flags && channel < DSHOT_TIMERS; channel++) {
if ((flags & (1 << channel)) && timer_io_channels[channel].flex_io_base == 2) {
if ((flags & (1 << channel)) && timer_io_channels[channel].flex_io_base == FLEXIO2_BASE) {
disable_shifter_status_interrupts(FLEXIO2_BASE, 1 << channel);
if (dshot_inst[channel].state == DSHOT_START) {
@ -338,7 +336,7 @@ static int flexio2_irq_handler(int irq, void *context, void *arg)
for (channel = 0; flags; (channel = (channel + 1) % DSHOT_TIMERS)) {
flags = get_timer_status_flags(FLEXIO2_BASE);
if ((flags & (1 << channel)) && timer_io_channels[channel].flex_io_base == 2) {
if ((flags & (1 << channel)) && timer_io_channels[channel].flex_io_base == FLEXIO2_BASE) {
clear_timer_status_flags(FLEXIO2_BASE, 1 << channel);
if (dshot_inst[channel].state == DSHOT_12BIT_FIFO) {
@ -412,13 +410,16 @@ int up_dshot_init(uint32_t channel_mask, unsigned dshot_pwm_freq, bool enable_bi
dshot_tcmp = 0x2F00 | (((BOARD_FLEXIO_PREQ / (dshot_pwm_freq * 3) / 2) - 1) & 0xFF);
bdshot_tcmp = 0x2900 | (((BOARD_FLEXIO_PREQ / (dshot_pwm_freq * 5 / 4) / 2) - 3) & 0xFF);
bool flexio1_channels = false;
bool flexio2_channels = false;
for (unsigned i = 0; (channel_mask != 0) && (i < DSHOT_TIMERS); i++) {
if (channel_mask & (1 << i)) {
if (timer_io_channels[i].flex_io_base == 1) {
if (timer_io_channels[i].flex_io_base == FLEXIO1_BASE) {
PX4_INFO("Flexio1 channel found");
flexio1_channels = true;
} else if (timer_io_channels[i].flex_io_base == 2) {
} else if (timer_io_channels[i].flex_io_base == FLEXIO2_BASE) {
PX4_INFO("Flexio2 channel found");
flexio2_channels = true;
@ -485,12 +486,12 @@ int up_dshot_init(uint32_t channel_mask, unsigned dshot_pwm_freq, bool enable_bi
dshot_inst[channel].bdshot = enable_bidirectional_dshot;
if (timer_io_channels[channel].flex_io_base == 1) {
if (timer_io_channels[channel].flex_io_base == FLEXIO1_BASE) {
flexio_dshot_output(FLEXIO1_BASE, channel, timer_io_channels[channel].dshot.flexio_pin, dshot_tcmp,
dshot_inst[channel].bdshot);
} else if (timer_io_channels[channel].flex_io_base == 2) {
} else if (timer_io_channels[channel].flex_io_base == FLEXIO2_BASE) {
flexio_dshot_output(FLEXIO2_BASE, channel, timer_io_channels[channel].dshot.flexio_pin, dshot_tcmp,
dshot_inst[channel].bdshot);
@ -629,6 +630,25 @@ void up_bdshot_status(void)
void up_dshot_trigger(void)
{
bool flexio1_channels = false;
bool flexio2_channels = false;
for (unsigned i = 0; (i < DSHOT_TIMERS); i++) {
if (dshot_inst[i].init && dshot_inst[i].data_seg1 != 0) {
if (timer_io_channels[i].flex_io_base == FLEXIO1_BASE) {
flexio1_channels = true;
PX4_INFO("Dshot trigger channels: Flexio1");
} else if (timer_io_channels[i].flex_io_base == FLEXIO2_BASE) {
flexio2_channels = true;
PX4_INFO("Dshot trigger channels: Flexio2");
} else {PX4_ERR("Invalid flexio base defined");}
}
}
// Calc data now since we're not event driven
if (bdshot_recv_mask != 0x0) {
up_bdshot_erpm();
@ -649,10 +669,10 @@ void up_dshot_trigger(void)
}
if (dshot_inst[channel].init && dshot_inst[channel].data_seg1 != 0) {
if (timer_io_channels[channel].flex_io_base == 1) {
if (timer_io_channels[channel].flex_io_base == FLEXIO1_BASE) {
flexio_putreg32(FLEXIO1_BASE, dshot_inst[channel].data_seg1, IMXRT_FLEXIO_SHIFTBUF0_OFFSET + channel * 0x4);
} else if (timer_io_channels[channel].flex_io_base == 2) {
} else if (timer_io_channels[channel].flex_io_base == FLEXIO2_BASE) {
flexio_putreg32(FLEXIO2_BASE, dshot_inst[channel].data_seg1, IMXRT_FLEXIO_SHIFTBUF0_OFFSET + channel * 0x4);
}
@ -738,7 +758,7 @@ void dshot_motor_data_set(unsigned channel, uint16_t throttle, bool telemetry)
if (dshot_inst[channel].bdshot) {
if (timer_io_channels[channel].flex_io_base == 1) {
if (timer_io_channels[channel].flex_io_base == FLEXIO1_BASE) {
flexio_putreg32(FLEXIO1_BASE, 0x0, IMXRT_FLEXIO_TIMCTL0_OFFSET + channel * 0x4);
disable_shifter_status_interrupts(FLEXIO1_BASE, 1 << channel);
@ -747,7 +767,7 @@ void dshot_motor_data_set(unsigned channel, uint16_t throttle, bool telemetry)
clear_timer_status_flags(FLEXIO1_BASE, 0xFF);
} else if (timer_io_channels[channel].flex_io_base == 2) {
} else if (timer_io_channels[channel].flex_io_base == FLEXIO2_BASE) {
flexio_putreg32(FLEXIO2_BASE, 0x0, IMXRT_FLEXIO_TIMCTL0_OFFSET + channel * 0x4);
disable_shifter_status_interrupts(FLEXIO2_BASE, 1 << channel);

2
platforms/nuttx/src/px4/nxp/rt106x/include/px4_arch/io_timer.h
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@ -107,12 +107,12 @@ typedef struct timer_io_channels_t {
uint32_t gpio_out; /* The timer valn_offset GPIO for PWM (this is the IOMUX Pad, e.g. PWM_IOMUX | GPIO_FLEXPWM2_PWMA00_2) */
uint32_t gpio_in; /* The timer valn_offset GPIO for Capture */
uint32_t gpio_portpin; /* The GPIO Port + Pin (e.g. GPIO_PORT2 | GPIO_PIN6) */
uint32_t flex_io_base;
uint8_t timer_index; /* 0 based index in the io_timers_t table */
uint8_t val_offset; /* IMXRT_FLEXPWM_SM0VAL3_OFFSET or IMXRT_FLEXPWM_SM0VAL5_OFFSET */
uint8_t sub_module; /* 0 based sub module offset */
uint8_t sub_module_bits; /* LDOK and CLDOK bits */
uint8_t timer_channel;/* Unused */
uint8_t flex_io_base;
dshot_conf_t dshot;
} timer_io_channels_t;

2
platforms/nuttx/src/px4/nxp/rt106x/include/px4_arch/io_timer_hw_description.h
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@ -601,7 +601,7 @@ static inline constexpr timer_io_channels_t initIOTimerChannel(const io_timers_t
return ret;
}
static inline constexpr timer_io_channels_t initIOTimerChannelDshot(const io_timers_t io_timers_conf[MAX_IO_TIMERS],
PWM::FlexPWMConfig pwm_config, IOMUX::Pad pad, uint32_t dshot_pinmux, uint8_t flexio, uint32_t flexio_pin)
PWM::FlexPWMConfig pwm_config, IOMUX::Pad pad, uint32_t dshot_pinmux, uint32_t flexio, uint32_t flexio_pin)
{
timer_io_channels_t ret = initIOTimerChannel(io_timers_conf, pwm_config, pad);
ret.dshot.pinmux = dshot_pinmux;