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STM32 GPIO fix; Fixes for PIC32 USB term example

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git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4241 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
2011-12-30 14:54:43 +00:00
parent 79e67d26b3
commit 2901574aff
13 changed files with 342 additions and 42 deletions
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nuttx/arch/arm/src/stm32/stm32_gpio.c
+10 -10
View File
@@ -563,9 +563,17 @@ int stm32_configgpio(uint32_t cfgset)
putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET);
/* If it is an input pin, hould it configured as an EXTI interrupt? */
/* If it is an output... set the pin to the correct initial state. */
if ((cfgset & GPIO_EXTI) != 0)
if (pinmode == GPIO_MODER_OUTPUT)
{
bool value = ((cfgset & GPIO_OUTPUT_SET) != 0);
stm32_gpiowrite(cfgset, value);
}
/* Otherwise, it is an input pin. Should it configured as an EXTI interrupt? */
else if ((cfgset & GPIO_EXTI) != 0)
{
/* "In STM32 F1 the selection of the EXTI line source is performed through
* the EXTIx bits in the AFIO_EXTICRx registers, while in F2 series this
@@ -590,14 +598,6 @@ int stm32_configgpio(uint32_t cfgset)
putreg32(regval, regaddr);
}
/* If it is an output... set the pin to the correct initial state. */
else if (pinmode == GPIO_MODER_OUTPUT)
{
bool value = ((cfgset & GPIO_OUTPUT_SET) != 0);
stm32_gpiowrite(cfgset, value);
}
irqrestore(flags);
return OK;
nuttx/arch/arm/src/stm32/stm32_start.c
-3
View File
@@ -78,9 +78,6 @@
* Configure the FPU. The the MCU has an FPU, then enable full access
* to coprocessors CP10 and CP11.
*
* This is implemented as a macro because the stack has not yet been
* initialized.
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU