mirror of
https://gitee.com/mirrors_PX4/PX4-Autopilot.git
synced 2026-04-14 10:07:39 +08:00
tropic-community: Fix RWW race condition and enet stability
This commit is contained in:
Peter van der Perk
Daniel Agar
parent
e30a30d768
commit
24572cf358
@ -14,6 +14,7 @@ CONFIG_DRIVERS_CAMERA_TRIGGER=y
|
||||
CONFIG_DRIVERS_CDCACM_AUTOSTART=y
|
||||
CONFIG_COMMON_DIFFERENTIAL_PRESSURE=y
|
||||
CONFIG_COMMON_DISTANCE_SENSOR=y
|
||||
CONFIG_DRIVERS_DISTANCE_SENSOR_LIGHTWARE_SF45_SERIAL=y
|
||||
CONFIG_DRIVERS_DSHOT=y
|
||||
CONFIG_DRIVERS_GNSS_SEPTENTRIO=y
|
||||
CONFIG_DRIVERS_GPS=y
|
||||
@ -26,12 +27,12 @@ CONFIG_COMMON_LIGHT=y
|
||||
CONFIG_DRIVERS_LIGHTS_RGBLED_PWM=y
|
||||
CONFIG_COMMON_MAGNETOMETER=y
|
||||
CONFIG_COMMON_OPTICAL_FLOW=y
|
||||
CONFIG_COMMON_OSD=y
|
||||
CONFIG_DRIVERS_OSD_MSP_OSD=y
|
||||
CONFIG_DRIVERS_POWER_MONITOR_INA226=y
|
||||
CONFIG_DRIVERS_POWER_MONITOR_INA228=y
|
||||
CONFIG_DRIVERS_POWER_MONITOR_INA238=y
|
||||
CONFIG_DRIVERS_PWM_OUT=y
|
||||
CONFIG_DRIVERS_RC_INPUT=y
|
||||
CONFIG_COMMON_RC=y
|
||||
CONFIG_DRIVERS_SAFETY_BUTTON=y
|
||||
CONFIG_COMMON_TELEMETRY=y
|
||||
CONFIG_DRIVERS_TONE_ALARM=y
|
||||
@ -44,13 +45,15 @@ CONFIG_MODULES_CAMERA_FEEDBACK=y
|
||||
CONFIG_MODULES_COMMANDER=y
|
||||
CONFIG_MODULES_CONTROL_ALLOCATOR=y
|
||||
CONFIG_MODULES_DATAMAN=y
|
||||
CONFIG_NUM_MISSION_ITMES_SUPPORTED=1000
|
||||
CONFIG_MODULES_EKF2=y
|
||||
CONFIG_MODULES_ESC_BATTERY=y
|
||||
CONFIG_MODULES_EVENTS=y
|
||||
CONFIG_MODULES_FLIGHT_MODE_MANAGER=y
|
||||
CONFIG_MODULES_FW_ATT_CONTROL=y
|
||||
CONFIG_MODULES_FW_AUTOTUNE_ATTITUDE_CONTROL=y
|
||||
CONFIG_MODULES_FW_POS_CONTROL=y
|
||||
CONFIG_MODULES_FW_LATERAL_LONGITUDINAL_CONTROL=y
|
||||
CONFIG_MODULES_FW_MODE_MANAGER=y
|
||||
CONFIG_MODULES_FW_RATE_CONTROL=y
|
||||
CONFIG_MODULES_GIMBAL=y
|
||||
CONFIG_MODULES_GYRO_CALIBRATION=y
|
||||
@ -100,3 +103,4 @@ CONFIG_SYSTEMCMDS_UORB=y
|
||||
CONFIG_SYSTEMCMDS_USB_CONNECTED=y
|
||||
CONFIG_SYSTEMCMDS_VER=y
|
||||
CONFIG_SYSTEMCMDS_WORK_QUEUE=y
|
||||
CONFIG_ARCH_CHIP_IMXRT=y
|
||||
|
||||
@ -62,7 +62,9 @@ CONFIG_FS_CROMFS=y
|
||||
CONFIG_FS_FAT=y
|
||||
CONFIG_FS_FATTIME=y
|
||||
CONFIG_FS_LITTLEFS=y
|
||||
CONFIG_FS_LITTLEFS_PROGRAM_SIZE_FACTOR=2
|
||||
CONFIG_FS_LITTLEFS_CACHE_SIZE_FACTOR=2
|
||||
CONFIG_FS_LITTLEFS_LOOKAHEAD_SIZE=64
|
||||
CONFIG_FS_LITTLEFS_PROGRAM_SIZE_FACTOR=1
|
||||
CONFIG_FS_PROCFS=y
|
||||
CONFIG_FS_PROCFS_MAX_TASKS=64
|
||||
CONFIG_FS_PROCFS_REGISTER=y
|
||||
@ -75,6 +77,7 @@ CONFIG_I2C=y
|
||||
CONFIG_I2C_RESET=y
|
||||
CONFIG_IDLETHREAD_STACKSIZE=2048
|
||||
CONFIG_IMXRT_DTCM_HEAP=y
|
||||
CONFIG_IMXRT_DTCM_HEAP_SIZE=127
|
||||
CONFIG_IMXRT_EDMA=y
|
||||
CONFIG_IMXRT_EDMA_EDBG=y
|
||||
CONFIG_IMXRT_EDMA_ELINK=y
|
||||
@ -84,8 +87,6 @@ CONFIG_IMXRT_ENET_NTXBUFFERS=8
|
||||
CONFIG_IMXRT_ENET_PHYINIT=y
|
||||
CONFIG_IMXRT_FLEXCAN3=y
|
||||
CONFIG_IMXRT_FLEXCAN_TXMB=1
|
||||
CONFIG_IMXRT_FLEXSPI1=y
|
||||
CONFIG_IMXRT_FLEXSPI1_XIP=y
|
||||
CONFIG_IMXRT_GPIO1_0_15_IRQ=y
|
||||
CONFIG_IMXRT_GPIO1_16_31_IRQ=y
|
||||
CONFIG_IMXRT_GPIO2_0_15_IRQ=y
|
||||
|
||||
@ -115,18 +115,29 @@
|
||||
*(.text.work_thread)
|
||||
*(.text.work_queue)
|
||||
|
||||
/* Flash Storage */
|
||||
*(.text.imxrt_flexspi_transfer_blocking)
|
||||
*(.text.imxrt_flexspi_transfer_blocking_private)
|
||||
*(.text.imxrt_flexspi_write_blocking)
|
||||
*(.text.imxrt_flexspi_read_blocking)
|
||||
*(.text.imxrt_flexspi_check_and_clear_error)
|
||||
*(.text.imxrt_flexspi_get_bus_idle_status)
|
||||
*(.text.imxrt_flexspi_configure_prefetch)
|
||||
*(.text.imxrt_flexspi_configure_prefetch_private)
|
||||
*(.text.imxrt_flexspi_storage_write_enable)
|
||||
*(.text.imxrt_flexspi_storage_wait_bus_busy)
|
||||
*(.text.imxrt_flexspi_storage_read_status)
|
||||
*(.text.imxrt_flexspi_storage_erase)
|
||||
*(.text.imxrt_flexspi_storage_bwrite)
|
||||
*(.text.imxrt_flexspi_storage_page_program)
|
||||
/* BMI088 */
|
||||
*(.text._ZN5Bosch6BMI08813Accelerometer20BMI088_Accelerometer12RegisterReadENS1_8RegisterE)
|
||||
*(.text._ZN5Bosch6BMI08813Accelerometer20BMI088_Accelerometer13FIFOReadCountEv)
|
||||
*(.text._ZN5Bosch6BMI08813Accelerometer20BMI088_Accelerometer8FIFOReadERKyh)
|
||||
*(.text._ZN5Bosch6BMI08813Accelerometer20BMI088_Accelerometer13RegisterCheckERKNS2_17register_config_tE)
|
||||
*(.text._ZN5Bosch6BMI08813Accelerometer20BMI088_Accelerometer13RegisterWriteENS1_8RegisterEh)
|
||||
*(.text._ZN5Bosch6BMI08813Accelerometer20BMI088_Accelerometer17UpdateTemperatureEv)
|
||||
*(.text._ZN5Bosch6BMI08813Accelerometer20BMI088_Accelerometer23RegisterSetAndClearBitsENS1_8RegisterEhh)
|
||||
*(.text._ZN5Bosch6BMI08813Accelerometer20BMI088_Accelerometer26DataReadyInterruptCallbackEiPvS3_)
|
||||
*(.text._ZN5Bosch6BMI08813Accelerometer20BMI088_Accelerometer7RunImplEv)
|
||||
*(.text._ZN5Bosch6BMI08813Accelerometer20BMI088_Accelerometer9DataReadyEv)
|
||||
*(.text._ZN5Bosch6BMI08813Accelerometer20BMI088_AccelerometerD0Ev)
|
||||
*(.text._ZN5Bosch6BMI08813Accelerometer20BMI088_AccelerometerD1Ev)
|
||||
*(.text._ZN5Bosch6BMI08813Accelerometer20BMI088_AccelerometerD2Ev)
|
||||
*(.text._ZN5Bosch6BMI0889Gyroscope16BMI088_Gyroscope12RegisterReadENS1_8RegisterE)
|
||||
*(.text._ZN5Bosch6BMI0889Gyroscope16BMI088_Gyroscope13RegisterCheckERKNS2_17register_config_tE)
|
||||
*(.text._ZN5Bosch6BMI0889Gyroscope16BMI088_Gyroscope13RegisterWriteENS1_8RegisterEh)
|
||||
*(.text._ZN5Bosch6BMI0889Gyroscope16BMI088_Gyroscope23RegisterSetAndClearBitsENS1_8RegisterEhh)
|
||||
*(.text._ZN5Bosch6BMI0889Gyroscope16BMI088_Gyroscope26DataReadyInterruptCallbackEiPvS3_)
|
||||
*(.text._ZN5Bosch6BMI0889Gyroscope16BMI088_Gyroscope7RunImplEv)
|
||||
*(.text._ZN5Bosch6BMI0889Gyroscope16BMI088_Gyroscope8FIFOReadERKyh)
|
||||
*(.text._ZN5Bosch6BMI0889Gyroscope16BMI088_Gyroscope9DataReadyEv)
|
||||
*(.text._ZN5Bosch6BMI0889Gyroscope16BMI088_GyroscopeD0Ev)
|
||||
*(.text._ZN5Bosch6BMI0889Gyroscope16BMI088_GyroscopeD1Ev)
|
||||
*(.text._ZN5Bosch6BMI0889Gyroscope16BMI088_GyroscopeD2Ev)
|
||||
*(.text._ZN12I2CSPIDriverI6BMI088E3RunEv)
|
||||
|
||||
@ -22,10 +22,11 @@
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flash (rx) : ORIGIN = 0x60000000, LENGTH = 7936K - 128K
|
||||
flash (rx) : ORIGIN = 0x60000000, LENGTH = 7936K - 256K
|
||||
sram (rwx) : ORIGIN = 0x20200000, LENGTH = 512K
|
||||
itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 384K
|
||||
dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
|
||||
dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 127K
|
||||
dtcm_nocache (rwx) : ORIGIN = 0x2001FC00, LENGTH = 1K
|
||||
}
|
||||
|
||||
OUTPUT_ARCH(arm)
|
||||
@ -55,6 +56,12 @@ SECTIONS
|
||||
. = 0x2000 ;
|
||||
} >flash
|
||||
|
||||
/* Workaround for ethernet issue, by placing g_desc_pool into DTCM,
|
||||
which effectively puts it into a no-cache region */
|
||||
.dtcm_nocache : {
|
||||
*(.bss.g_desc_pool)
|
||||
} > dtcm_nocache
|
||||
|
||||
.vectors :
|
||||
{
|
||||
KEEP(*(.vectors))
|
||||
@ -162,6 +169,10 @@ SECTIONS
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
|
||||
_boot_loadaddr = ORIGIN(flash);
|
||||
_boot_size = LENGTH(flash);
|
||||
_ram_size = LENGTH(sram);
|
||||
_sdtcm = ORIGIN(dtcm);
|
||||
_edtcm = ORIGIN(dtcm) + LENGTH(dtcm);
|
||||
}
|
||||
|
||||
@ -51,6 +51,8 @@ set_source_files_properties(imxrt_ocram_initialize.c PROPERTIES COMPILE_FLAGS -f
|
||||
|
||||
target_link_libraries(drivers_board
|
||||
PRIVATE
|
||||
arch_board_romapi
|
||||
arch_spi
|
||||
nuttx_arch # sdio
|
||||
nuttx_drivers # sdio
|
||||
px4_layer
|
||||
|
||||
@ -112,7 +112,6 @@
|
||||
|
||||
#define GPIO_DRDY_OFF_SPI4_DRDY7_EXTERNAL1 _PIN_OFF(GPIO_SPI4_DRDY7_EXTERNAL1)
|
||||
|
||||
|
||||
#define ADC_IOMUX (IOMUX_CMOS_INPUT | IOMUX_PULL_NONE | IOMUX_DRIVE_HIZ)
|
||||
|
||||
#define ADC1_CH(n) (n)
|
||||
@ -262,6 +261,10 @@ static inline int board_read_usb2_vbus_state(void)
|
||||
}
|
||||
|
||||
#define BOARD_ENABLE_CONSOLE_BUFFER
|
||||
|
||||
/* Flash instance for storage */
|
||||
#define NOR_INSTANCE 0
|
||||
|
||||
__BEGIN_DECLS
|
||||
|
||||
/****************************************************************************************************
|
||||
@ -316,6 +319,8 @@ extern int imxrt1062_spi_bus_initialize(void);
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
extern void imxrt_spiinitialize(void);
|
||||
|
||||
extern int imxrt_usb_initialize(void);
|
||||
|
||||
extern void imxrt_usbinitialize(void);
|
||||
@ -326,6 +331,8 @@ extern void fmurt1062_timer_initialize(void);
|
||||
|
||||
#include <px4_platform_common/board_common.h>
|
||||
|
||||
void imxrt_flash_romapi_initialize(void);
|
||||
|
||||
int imxrt_flexspi_storage_initialize(void);
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
@ -28,55 +28,71 @@
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
enum {
|
||||
/* SPI instructions */
|
||||
|
||||
READ_FAST = 0,
|
||||
READ_STATUS_REG = 1,
|
||||
WRITE_ENABLE = 3,
|
||||
SECTOR_ERASE_4K = 5,
|
||||
READ_FAST_QUAD_OUTPUT = 6,
|
||||
PAGE_PROGRAM_QUAD_INPUT = 7,
|
||||
ERASE_BLOCK = 8,
|
||||
PAGE_PROGRAM = 9,
|
||||
CHIP_ERASE = 11,
|
||||
};
|
||||
|
||||
locate_data(".boot_hdr.conf")
|
||||
const struct flexspi_nor_config_s g_flash_config = {
|
||||
.mem_config =
|
||||
{
|
||||
.tag = FLEXSPI_CFG_BLK_TAG,
|
||||
.version = FLEXSPI_CFG_BLK_VERSION,
|
||||
.read_sample_clksrc = FLASH_READ_SAMPLE_CLK_LOOPBACK_FROM_SCKPAD,
|
||||
.cs_hold_time = 1u,
|
||||
.cs_setup_time = 1u,
|
||||
.column_address_width = 0u,
|
||||
.device_type = FLEXSPI_DEVICE_TYPE_SERIAL_NOR,
|
||||
.sflash_pad_type = SERIAL_FLASH_4PADS,
|
||||
.serial_clk_freq = FLEXSPI_SERIAL_CLKFREQ_133MHz,
|
||||
.sflash_a1size = 8u * 1024u * 1024u,
|
||||
.data_valid_time =
|
||||
.tag = FLEXSPI_CFG_BLK_TAG,
|
||||
.version = FLEXSPI_CFG_BLK_VERSION,
|
||||
.read_sample_clksrc = FLASH_READ_SAMPLE_CLK_LOOPBACK_FROM_SCKPAD,
|
||||
.cs_hold_time = 1u,
|
||||
.cs_setup_time = 1u,
|
||||
.column_address_width = 0u,
|
||||
.device_type = FLEXSPI_DEVICE_TYPE_SERIAL_NOR,
|
||||
.sflash_pad_type = SERIAL_FLASH_4PADS,
|
||||
.serial_clk_freq = FLEXSPI_SERIAL_CLKFREQ_133MHz,
|
||||
.sflash_a1size = 8u * 1024u * 1024u,
|
||||
.lookup_table =
|
||||
{
|
||||
0u, 0u
|
||||
},
|
||||
.lookup_table =
|
||||
{
|
||||
/* Fast Read Quad I/O */
|
||||
[0 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xeb,
|
||||
RADDR_SDR, FLEXSPI_4PAD, 0x18),
|
||||
[0 + 1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06,
|
||||
READ_SDR, FLEXSPI_4PAD, 0x04),
|
||||
[4 * READ_FAST] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xeb,
|
||||
RADDR_SDR, FLEXSPI_4PAD, 0x18),
|
||||
[4 * READ_FAST + 1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06,
|
||||
READ_SDR, FLEXSPI_4PAD, 0x04),
|
||||
|
||||
/* Read Status Register-1 */
|
||||
[4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05,
|
||||
READ_SDR, FLEXSPI_1PAD, 0x04),
|
||||
[4 * READ_STATUS_REG] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05,
|
||||
READ_SDR, FLEXSPI_1PAD, 0x04),
|
||||
|
||||
/* Write Status Register-1 */
|
||||
[4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01, STOP, FLEXSPI_1PAD, 0x0),
|
||||
[4 * WRITE_ENABLE] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06,
|
||||
STOP, FLEXSPI_1PAD, 0),
|
||||
|
||||
/* Sector Erase (4KB) */
|
||||
[4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20,
|
||||
RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
[4 * SECTOR_ERASE_4K] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20,
|
||||
RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
|
||||
/* Block Erase (64KB) */
|
||||
[4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xd8,
|
||||
RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
[4 * CHIP_ERASE] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60,
|
||||
STOP, FLEXSPI_1PAD, 0),
|
||||
|
||||
/* Page Program */
|
||||
[4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02,
|
||||
RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
[4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04,
|
||||
STOP, FLEXSPI_1PAD, 0x0),
|
||||
[4 * ERASE_BLOCK] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xd8,
|
||||
RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
|
||||
[4 * PAGE_PROGRAM] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02,
|
||||
RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
[4 * PAGE_PROGRAM + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04,
|
||||
STOP, FLEXSPI_1PAD, 0x0),
|
||||
|
||||
[4 * READ_FAST_QUAD_OUTPUT] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x6b,
|
||||
RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
[4 * READ_FAST_QUAD_OUTPUT + 1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x08,
|
||||
READ_SDR, FLEXSPI_4PAD, 0x04),
|
||||
|
||||
[4 * PAGE_PROGRAM_QUAD_INPUT] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x32,
|
||||
RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
[4 * PAGE_PROGRAM_QUAD_INPUT + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_4PAD, 0x04,
|
||||
STOP, FLEXSPI_1PAD, 0),
|
||||
|
||||
/* Chip Erase */
|
||||
[4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0x0),
|
||||
},
|
||||
},
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/****************************************************************************
|
||||
* boards/px4/fmu-v6xrt/src/imxrt_flexspi_storage.c
|
||||
* boards/nxp/tropic-community/src/imxrt_flexspi_storage.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
@ -36,104 +36,28 @@
|
||||
#include <px4_platform_common/px4_mtd.h>
|
||||
#include "px4_log.h"
|
||||
|
||||
#include "imxrt_flexspi.h"
|
||||
#include <px4_arch/imxrt_flexspi_nor_flash.h>
|
||||
#include <px4_arch/imxrt_romapi.h>
|
||||
#include "board_config.h"
|
||||
#include "hardware/imxrt_pinmux.h"
|
||||
|
||||
#ifdef CONFIG_IMXRT_FLEXSPI
|
||||
#include "barriers.h"
|
||||
|
||||
/* Used sectors must be multiple of the flash block size
|
||||
* i.e. W25Q32JV has a block size of 64KB
|
||||
*/
|
||||
|
||||
#define NOR_USED_SECTORS (0x20U) /* 32 * 4KB = 128KB */
|
||||
#define NOR_USED_SECTORS (0x40U) /* 64 * 4KB = 256KB */
|
||||
#define NOR_TOTAL_SECTORS (0x0800U)
|
||||
#define NOR_PAGE_SIZE (0x0100U) /* 256 bytes */
|
||||
#define NOR_SECTOR_SIZE (0x1000U) /* 4KB */
|
||||
#define NOR_START_SECTOR (NOR_TOTAL_SECTORS - NOR_USED_SECTORS)
|
||||
#define NOR_START_PAGE ((NOR_START_SECTOR * NOR_SECTOR_SIZE) / NOR_PAGE_SIZE)
|
||||
#define NOR_STORAGE_ADDR (IMXRT_FLEXCIPHER_BASE + NOR_START_SECTOR * NOR_SECTOR_SIZE)
|
||||
#define NOR_STORAGE_END (IMXRT_FLEXCIPHER_BASE + (NOR_START_SECTOR + NOR_TOTAL_SECTORS) * NOR_SECTOR_SIZE)
|
||||
|
||||
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
|
||||
|
||||
enum {
|
||||
/* SPI instructions */
|
||||
|
||||
READ_FAST = 0,
|
||||
READ_STATUS_REG = 1,
|
||||
WRITE_STATUS_REG = 3,
|
||||
WRITE_ENABLE = 4,
|
||||
SECTOR_ERASE_4K = 5,
|
||||
READ_FAST_QUAD_OUTPUT = 6,
|
||||
PAGE_PROGRAM_QUAD_INPUT = 7,
|
||||
PAGE_PROGRAM = 9,
|
||||
CHIP_ERASE = 11,
|
||||
};
|
||||
|
||||
static const uint32_t g_flexspi_nor_lut[][4] = {
|
||||
[READ_FAST] =
|
||||
{
|
||||
FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_SDR, FLEXSPI_1PAD, 0xeb,
|
||||
FLEXSPI_COMMAND_RADDR_SDR, FLEXSPI_4PAD, 0x18),
|
||||
FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_DUMMY_SDR, FLEXSPI_4PAD, 0x06,
|
||||
FLEXSPI_COMMAND_READ_SDR, FLEXSPI_4PAD, 0x04),
|
||||
},
|
||||
|
||||
[READ_STATUS_REG] =
|
||||
{
|
||||
FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_SDR, FLEXSPI_1PAD, 0x05,
|
||||
FLEXSPI_COMMAND_READ_SDR, FLEXSPI_1PAD, 0x04),
|
||||
},
|
||||
|
||||
[WRITE_STATUS_REG] =
|
||||
{
|
||||
FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_SDR, FLEXSPI_1PAD, 0x01,
|
||||
FLEXSPI_COMMAND_WRITE_SDR, FLEXSPI_1PAD, 0x04),
|
||||
},
|
||||
|
||||
[WRITE_ENABLE] =
|
||||
{
|
||||
FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_SDR, FLEXSPI_1PAD, 0x06,
|
||||
FLEXSPI_COMMAND_STOP, FLEXSPI_1PAD, 0),
|
||||
},
|
||||
|
||||
[SECTOR_ERASE_4K] =
|
||||
{
|
||||
FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_SDR, FLEXSPI_1PAD, 0x20,
|
||||
FLEXSPI_COMMAND_RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
},
|
||||
|
||||
[CHIP_ERASE] =
|
||||
{
|
||||
FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_SDR, FLEXSPI_1PAD, 0xc7,
|
||||
FLEXSPI_COMMAND_STOP, FLEXSPI_1PAD, 0),
|
||||
},
|
||||
|
||||
[PAGE_PROGRAM] =
|
||||
{
|
||||
FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_SDR, FLEXSPI_1PAD, 0x02,
|
||||
FLEXSPI_COMMAND_RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_WRITE_SDR, FLEXSPI_1PAD, 0x04,
|
||||
FLEXSPI_COMMAND_STOP, FLEXSPI_1PAD, 0x0),
|
||||
},
|
||||
|
||||
[READ_FAST_QUAD_OUTPUT] =
|
||||
{
|
||||
FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_SDR, FLEXSPI_1PAD, 0x6b,
|
||||
FLEXSPI_COMMAND_RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_DUMMY_SDR, FLEXSPI_4PAD, 0x08,
|
||||
FLEXSPI_COMMAND_READ_SDR, FLEXSPI_4PAD, 0x04),
|
||||
},
|
||||
|
||||
[PAGE_PROGRAM_QUAD_INPUT] =
|
||||
{
|
||||
FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_SDR, FLEXSPI_1PAD, 0x32,
|
||||
FLEXSPI_COMMAND_RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
FLEXSPI_LUT_SEQ(FLEXSPI_COMMAND_WRITE_SDR, FLEXSPI_4PAD, 0x04,
|
||||
FLEXSPI_COMMAND_STOP, FLEXSPI_1PAD, 0),
|
||||
},
|
||||
|
||||
};
|
||||
extern struct flexspi_nor_config_s g_bootConfig;
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
@ -143,10 +67,7 @@ static const uint32_t g_flexspi_nor_lut[][4] = {
|
||||
|
||||
struct imxrt_flexspi_storage_dev_s {
|
||||
struct mtd_dev_s mtd;
|
||||
struct flexspi_dev_s *flexspi; /* Saved FlexSPI interface instance */
|
||||
uint8_t *ahb_base;
|
||||
enum flexspi_port_e port;
|
||||
struct flexspi_device_config_s *config;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
@ -178,26 +99,6 @@ static int imxrt_flexspi_storage_ioctl(struct mtd_dev_s *dev,
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
static struct flexspi_device_config_s g_flexspi_device_config = {
|
||||
.flexspi_root_clk = 4000000,
|
||||
.is_sck2_enabled = 0,
|
||||
.flash_size = NOR_USED_SECTORS * NOR_SECTOR_SIZE / 4,
|
||||
.cs_interval_unit = FLEXSPI_CS_INTERVAL_UNIT1_SCK_CYCLE,
|
||||
.cs_interval = 0,
|
||||
.cs_hold_time = 3,
|
||||
.cs_setup_time = 3,
|
||||
.data_valid_time = 0,
|
||||
.columnspace = 0,
|
||||
.enable_word_address = 0,
|
||||
.awr_seq_index = 0,
|
||||
.awr_seq_number = 0,
|
||||
.ard_seq_index = READ_FAST,
|
||||
.ard_seq_number = 1,
|
||||
.ahb_write_wait_unit = FLEXSPI_AHB_WRITE_WAIT_UNIT2_AHB_CYCLE,
|
||||
.ahb_write_wait_interval = 0,
|
||||
.rx_sample_clock = FLEXSPI_READ_SAMPLE_CLK_LOOPBACK_FROM_DQS_PAD,
|
||||
};
|
||||
|
||||
static struct imxrt_flexspi_storage_dev_s g_flexspi_nor = {
|
||||
.mtd =
|
||||
{
|
||||
@ -211,90 +112,17 @@ static struct imxrt_flexspi_storage_dev_s g_flexspi_nor = {
|
||||
#endif
|
||||
.name = "imxrt_flexspi_storage"
|
||||
},
|
||||
.flexspi = (void *)0,
|
||||
.ahb_base = (uint8_t *) NOR_STORAGE_ADDR,
|
||||
.port = FLEXSPI_PORT_A1,
|
||||
.config = &g_flexspi_device_config
|
||||
};
|
||||
|
||||
/* Ensure exclusive access to the driver */
|
||||
|
||||
static sem_t g_exclsem = SEM_INITIALIZER(1);
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
static int imxrt_flexspi_storage_read_status(
|
||||
const struct imxrt_flexspi_storage_dev_s *dev,
|
||||
uint32_t *status)
|
||||
{
|
||||
int stat;
|
||||
|
||||
struct flexspi_transfer_s transfer = {
|
||||
.device_address = 0,
|
||||
.port = dev->port,
|
||||
.cmd_type = FLEXSPI_READ,
|
||||
.seq_number = 1,
|
||||
.seq_index = READ_STATUS_REG,
|
||||
.data = status,
|
||||
.data_size = 1,
|
||||
};
|
||||
|
||||
stat = FLEXSPI_TRANSFER(dev->flexspi, &transfer);
|
||||
|
||||
if (stat != 0) {
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int imxrt_flexspi_storage_write_enable(
|
||||
const struct imxrt_flexspi_storage_dev_s *dev)
|
||||
{
|
||||
int stat;
|
||||
|
||||
struct flexspi_transfer_s transfer = {
|
||||
.device_address = 0,
|
||||
.port = dev->port,
|
||||
.cmd_type = FLEXSPI_COMMAND,
|
||||
.seq_number = 1,
|
||||
.seq_index = WRITE_ENABLE,
|
||||
.data = NULL,
|
||||
.data_size = 0,
|
||||
};
|
||||
|
||||
stat = FLEXSPI_TRANSFER(dev->flexspi, &transfer);
|
||||
|
||||
if (stat != 0) {
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int imxrt_flexspi_storage_erase_sector(
|
||||
const struct imxrt_flexspi_storage_dev_s *dev,
|
||||
off_t offset)
|
||||
{
|
||||
int stat;
|
||||
struct flexspi_transfer_s transfer = {
|
||||
.device_address = offset,
|
||||
.port = dev->port,
|
||||
.cmd_type = FLEXSPI_COMMAND,
|
||||
.seq_number = 1,
|
||||
.seq_index = SECTOR_ERASE_4K,
|
||||
.data = NULL,
|
||||
.data_size = 0,
|
||||
};
|
||||
|
||||
stat = FLEXSPI_TRANSFER(dev->flexspi, &transfer);
|
||||
|
||||
if (stat != 0) {
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int imxrt_flexspi_storage_erase_chip(
|
||||
const struct imxrt_flexspi_storage_dev_s *dev)
|
||||
{
|
||||
@ -302,69 +130,38 @@ static int imxrt_flexspi_storage_erase_chip(
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int imxrt_flexspi_storage_page_program(
|
||||
const struct imxrt_flexspi_storage_dev_s *dev,
|
||||
off_t offset,
|
||||
const void *buffer,
|
||||
size_t len)
|
||||
{
|
||||
int stat;
|
||||
|
||||
struct flexspi_transfer_s transfer = {
|
||||
.device_address = offset,
|
||||
.port = dev->port,
|
||||
.cmd_type = FLEXSPI_WRITE,
|
||||
.seq_number = 1,
|
||||
.seq_index = PAGE_PROGRAM_QUAD_INPUT,
|
||||
.data = (uint32_t *) buffer,
|
||||
.data_size = len,
|
||||
};
|
||||
|
||||
stat = FLEXSPI_TRANSFER(dev->flexspi, &transfer);
|
||||
|
||||
if (stat != 0) {
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int imxrt_flexspi_storage_wait_bus_busy(
|
||||
const struct imxrt_flexspi_storage_dev_s *dev)
|
||||
{
|
||||
uint32_t status = 0;
|
||||
int ret;
|
||||
|
||||
do {
|
||||
ret = imxrt_flexspi_storage_read_status(dev, &status);
|
||||
|
||||
if (ret) {
|
||||
return ret;
|
||||
}
|
||||
} while (status & 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static ssize_t imxrt_flexspi_storage_read(struct mtd_dev_s *dev,
|
||||
off_t offset,
|
||||
size_t nbytes,
|
||||
uint8_t *buffer)
|
||||
{
|
||||
ssize_t ret;
|
||||
struct imxrt_flexspi_storage_dev_s *priv =
|
||||
(struct imxrt_flexspi_storage_dev_s *)dev;
|
||||
uint8_t *src;
|
||||
|
||||
finfo("offset: %08lx nbytes: %d\n", (long)offset, (int)nbytes);
|
||||
|
||||
if (priv->port >= FLEXSPI_PORT_COUNT) {
|
||||
if (offset < 0) {
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
src = priv->ahb_base + offset;
|
||||
|
||||
if (src + nbytes > (uint8_t *)NOR_STORAGE_END) {
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
ret = nxsem_wait(&g_exclsem);
|
||||
|
||||
if (ret < 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
memcpy(buffer, src, nbytes);
|
||||
|
||||
nxsem_post(&g_exclsem);
|
||||
|
||||
finfo("return nbytes: %d\n", (int)nbytes);
|
||||
return (ssize_t)nbytes;
|
||||
}
|
||||
@ -392,85 +189,102 @@ static ssize_t imxrt_flexspi_storage_bread(struct mtd_dev_s *dev,
|
||||
return nbytes;
|
||||
}
|
||||
|
||||
locate_code(".ramfunc")
|
||||
static ssize_t imxrt_flexspi_storage_bwrite(struct mtd_dev_s *dev,
|
||||
off_t startblock,
|
||||
size_t nblocks,
|
||||
const uint8_t *buffer)
|
||||
{
|
||||
struct imxrt_flexspi_storage_dev_s *priv =
|
||||
(struct imxrt_flexspi_storage_dev_s *)dev;
|
||||
ssize_t ret;
|
||||
struct flexspi_nor_config_s *pConfig = &g_bootConfig;
|
||||
size_t len = nblocks * NOR_PAGE_SIZE;
|
||||
off_t offset = (startblock + NOR_START_PAGE) * NOR_PAGE_SIZE;
|
||||
uint8_t *src = (uint8_t *) buffer;
|
||||
#ifdef CONFIG_ARMV7M_DCACHE
|
||||
struct imxrt_flexspi_storage_dev_s *priv =
|
||||
(struct imxrt_flexspi_storage_dev_s *)dev;
|
||||
uint8_t *dst = priv->ahb_base + startblock * NOR_PAGE_SIZE;
|
||||
#endif
|
||||
int i;
|
||||
|
||||
if (((uintptr_t)buffer % 4) != 0) {
|
||||
return -EINVAL; // Byte aligned write not supported
|
||||
}
|
||||
|
||||
finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
|
||||
|
||||
FLEXSPI_CONFIGURE_PREFETCH(priv->flexspi, false);
|
||||
ret = nxsem_wait(&g_exclsem);
|
||||
|
||||
irqstate_t flags = enter_critical_section();
|
||||
if (ret < 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
while (len) {
|
||||
i = MIN(NOR_PAGE_SIZE, len);
|
||||
imxrt_flexspi_storage_write_enable(priv);
|
||||
imxrt_flexspi_storage_page_program(priv, offset, src, i);
|
||||
imxrt_flexspi_storage_wait_bus_busy(priv);
|
||||
cpsid(); // Disable interrupts
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wcast-align"
|
||||
volatile uint32_t status = ROM_FLEXSPI_NorFlash_ProgramPage(NOR_INSTANCE, pConfig, offset, (const uint32_t *)src);
|
||||
#pragma GCC diagnostic pop
|
||||
cpsie(); // Enable interrupts
|
||||
usleep(0); // Yield to scheduler
|
||||
UNUSED(status);
|
||||
|
||||
offset += i;
|
||||
src += i;
|
||||
len -= i;
|
||||
}
|
||||
|
||||
FLEXSPI_CONFIGURE_PREFETCH(priv->flexspi, true);
|
||||
|
||||
leave_critical_section(flags);
|
||||
|
||||
#ifdef CONFIG_ARMV7M_DCACHE
|
||||
up_invalidate_dcache((uintptr_t)dst,
|
||||
(uintptr_t)dst + nblocks * NOR_PAGE_SIZE);
|
||||
#endif
|
||||
|
||||
nxsem_post(&g_exclsem);
|
||||
|
||||
return nblocks;
|
||||
}
|
||||
|
||||
locate_code(".ramfunc")
|
||||
static int imxrt_flexspi_storage_erase(struct mtd_dev_s *dev,
|
||||
off_t startblock,
|
||||
size_t nblocks)
|
||||
{
|
||||
struct imxrt_flexspi_storage_dev_s *priv =
|
||||
(struct imxrt_flexspi_storage_dev_s *)dev;
|
||||
struct flexspi_nor_config_s *pConfig = &g_bootConfig;
|
||||
size_t blocksleft = nblocks;
|
||||
#ifdef CONFIG_ARMV7M_DCACHE
|
||||
struct imxrt_flexspi_storage_dev_s *priv =
|
||||
(struct imxrt_flexspi_storage_dev_s *)dev;
|
||||
uint8_t *dst = priv->ahb_base + startblock * NOR_SECTOR_SIZE;
|
||||
#endif
|
||||
ssize_t ret;
|
||||
|
||||
startblock += NOR_START_SECTOR;
|
||||
|
||||
finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
|
||||
|
||||
FLEXSPI_CONFIGURE_PREFETCH(priv->flexspi, false);
|
||||
ret = nxsem_wait(&g_exclsem);
|
||||
|
||||
irqstate_t flags = enter_critical_section();
|
||||
if (ret < 0) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
while (blocksleft-- > 0) {
|
||||
/* Erase each sector */
|
||||
|
||||
imxrt_flexspi_storage_write_enable(priv);
|
||||
imxrt_flexspi_storage_erase_sector(priv, startblock * NOR_SECTOR_SIZE);
|
||||
imxrt_flexspi_storage_wait_bus_busy(priv);
|
||||
cpsid(); // Disable interrupts
|
||||
volatile uint32_t status = ROM_FLEXSPI_NorFlash_Erase(NOR_INSTANCE, pConfig,
|
||||
(startblock * NOR_SECTOR_SIZE), NOR_SECTOR_SIZE);
|
||||
cpsie(); // Enable interrupts
|
||||
usleep(0); // Yield to scheduler
|
||||
UNUSED(status);
|
||||
startblock++;
|
||||
}
|
||||
|
||||
FLEXSPI_CONFIGURE_PREFETCH(priv->flexspi, true);
|
||||
|
||||
leave_critical_section(flags);
|
||||
|
||||
#ifdef CONFIG_ARMV7M_DCACHE
|
||||
up_invalidate_dcache((uintptr_t)dst,
|
||||
(uintptr_t)dst + nblocks * NOR_SECTOR_SIZE);
|
||||
#endif
|
||||
nxsem_post(&g_exclsem);
|
||||
|
||||
return (int)nblocks;
|
||||
}
|
||||
@ -530,9 +344,7 @@ static int imxrt_flexspi_storage_ioctl(struct mtd_dev_s *dev,
|
||||
case MTDIOC_BULKERASE: {
|
||||
/* Erase the entire device */
|
||||
|
||||
imxrt_flexspi_storage_write_enable(priv);
|
||||
imxrt_flexspi_storage_erase_chip(priv);
|
||||
imxrt_flexspi_storage_wait_bus_busy(priv);
|
||||
ret = OK;
|
||||
}
|
||||
break;
|
||||
@ -569,20 +381,6 @@ int imxrt_flexspi_storage_initialize(void)
|
||||
struct mtd_dev_s *mtd_dev = &g_flexspi_nor.mtd;
|
||||
int ret = -ENODEV;
|
||||
|
||||
/* Select FlexSPI1 */
|
||||
|
||||
g_flexspi_nor.flexspi = imxrt_flexspi_initialize(0);
|
||||
|
||||
if (g_flexspi_nor.flexspi) {
|
||||
ret = OK;
|
||||
|
||||
|
||||
FLEXSPI_UPDATE_LUT(g_flexspi_nor.flexspi,
|
||||
0,
|
||||
(const uint32_t *)g_flexspi_nor_lut,
|
||||
sizeof(g_flexspi_nor_lut) / 4);
|
||||
}
|
||||
|
||||
/* Register the MTD driver so that it can be accessed from the
|
||||
* VFS.
|
||||
*/
|
||||
@ -611,4 +409,3 @@ int imxrt_flexspi_storage_initialize(void)
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif /* CONFIG_IMXRT_FLEXSPI */
|
||||
|
||||
@ -64,9 +64,9 @@
|
||||
#include <nuttx/analog/adc.h>
|
||||
#include <nuttx/mm/gran.h>
|
||||
|
||||
#include "arm_internal.h"
|
||||
#include "arm_internal.h"
|
||||
#include "imxrt_flexspi_nor_boot.h"
|
||||
#include <px4_arch/imxrt_flexspi_nor_flash.h>
|
||||
#include "imxrt_iomuxc.h"
|
||||
#include "imxrt_flexcan.h"
|
||||
#include "imxrt_enet.h"
|
||||
@ -84,6 +84,7 @@
|
||||
#include <drivers/drv_board_led.h>
|
||||
#include <systemlib/px4_macros.h>
|
||||
#include <px4_arch/io_timer.h>
|
||||
#include <px4_arch/imxrt_romapi.h>
|
||||
#include <px4_platform_common/init.h>
|
||||
#include <px4_platform/gpio.h>
|
||||
#include <px4_platform/board_dma_alloc.h>
|
||||
@ -144,6 +145,30 @@ __EXPORT void board_on_reset(int status)
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imxrt_flash_romapi_initialize
|
||||
*
|
||||
* Description:
|
||||
*
|
||||
****************************************************************************/
|
||||
struct flexspi_nor_config_s g_bootConfig;
|
||||
|
||||
locate_code(".ramfunc")
|
||||
void imxrt_flash_romapi_initialize(void)
|
||||
{
|
||||
memcpy((struct flexspi_nor_config_s *)&g_bootConfig, &g_flash_config,
|
||||
sizeof(struct flexspi_nor_config_s));
|
||||
g_bootConfig.memConfig.tag = FLEXSPI_CFG_BLK_TAG;
|
||||
|
||||
ROM_API_Init();
|
||||
|
||||
ROM_FLEXSPI_NorFlash_Init(NOR_INSTANCE, (struct flexspi_nor_config_s *)&g_bootConfig);
|
||||
ROM_FLEXSPI_NorFlash_ClearCache(NOR_INSTANCE);
|
||||
|
||||
ARM_DSB();
|
||||
ARM_ISB();
|
||||
ARM_DMB();
|
||||
}
|
||||
|
||||
locate_code(".ramfunc")
|
||||
void imxrt_flash_setup_prefetch_partition(void)
|
||||
@ -207,6 +232,8 @@ __EXPORT void imxrt_boardinitialize(void)
|
||||
{
|
||||
imxrt_flash_setup_prefetch_partition();
|
||||
|
||||
imxrt_flash_romapi_initialize();
|
||||
|
||||
board_on_reset(-1); /* Reset PWM first thing */
|
||||
|
||||
/* configure LEDs */
|
||||
@ -218,10 +245,6 @@ __EXPORT void imxrt_boardinitialize(void)
|
||||
const uint32_t gpio[] = PX4_GPIO_INIT_LIST;
|
||||
px4_gpio_init(gpio, arraySize(gpio));
|
||||
|
||||
/* configure SPI interfaces */
|
||||
|
||||
imxrt_spidev_initialize();
|
||||
|
||||
imxrt_usb_initialize();
|
||||
|
||||
fmurt1062_timer_initialize();
|
||||
@ -330,14 +353,18 @@ void imxrt_flexio_clocking(void)
|
||||
****************************************************************************/
|
||||
__EXPORT int board_app_initialize(uintptr_t arg)
|
||||
{
|
||||
int ret = OK;
|
||||
|
||||
#if !defined(BOOTLOADER)
|
||||
|
||||
imxrt_flexio_clocking();
|
||||
|
||||
/* Power on Interfaces */
|
||||
|
||||
board_spi_reset(10, 0xffff);
|
||||
|
||||
px4_platform_init();
|
||||
|
||||
imxrt_spiinitialize();
|
||||
|
||||
/* configure the DMA allocator */
|
||||
|
||||
if (board_dma_alloc_init() < 0) {
|
||||
@ -350,14 +377,13 @@ __EXPORT int board_app_initialize(uintptr_t arg)
|
||||
hrt_call_every(&serial_dma_call, 1000, 1000, (hrt_callout)imxrt_serial_dma_poll, NULL);
|
||||
#endif
|
||||
|
||||
int ret = OK;
|
||||
#if defined(CONFIG_IMXRT_USDHC)
|
||||
ret = fmurt1062_usdhc_initialize();
|
||||
#endif
|
||||
|
||||
/* Configure SPI-based devices */
|
||||
imxrt_spiinitialize();
|
||||
|
||||
ret = imxrt1062_spi_bus_initialize();
|
||||
board_spi_reset(10, 0xffff);
|
||||
|
||||
#ifdef CONFIG_IMXRT_ENET
|
||||
imxrt_netinitialize(0);
|
||||
@ -367,7 +393,6 @@ __EXPORT int board_app_initialize(uintptr_t arg)
|
||||
imxrt_caninitialize(3);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMXRT_FLEXSPI
|
||||
ret = imxrt_flexspi_storage_initialize();
|
||||
|
||||
if (ret < 0) {
|
||||
@ -375,7 +400,7 @@ __EXPORT int board_app_initialize(uintptr_t arg)
|
||||
"ERROR: imxrt_flexspi_nor_initialize failed: %d\n", ret);
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif /* !defined(BOOTLOADER) */
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -62,7 +62,6 @@
|
||||
|
||||
#if defined(CONFIG_IMXRT_LPSPI3) || defined(CONFIG_IMXRT_LPSPI4)
|
||||
|
||||
|
||||
constexpr px4_spi_bus_t px4_spi_buses[SPI_BUS_MAX_BUS_ITEMS] = {
|
||||
initSPIBus(SPI::Bus::LPSPI3, {
|
||||
initSPIDevice(DRV_IMU_DEVTYPE_ICM42688P, SPI::CS{GPIO::Port1, GPIO::Pin28}), /* GPIO_AD_B1_12 GPIO1_IO28 */
|
||||
@ -75,241 +74,4 @@ constexpr px4_spi_bus_t px4_spi_buses[SPI_BUS_MAX_BUS_ITEMS] = {
|
||||
|
||||
static constexpr bool unused = validateSPIConfig(px4_spi_buses);
|
||||
|
||||
#define _PIN_OFF(def) (((def) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | (GPIO_INPUT | IOMUX_PULL_DOWN_100K | IOMUX_CMOS_INPUT))
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
/************************************************************************************
|
||||
* Name: fmurt1062_spidev_initialize
|
||||
*
|
||||
* Description:
|
||||
* Called to configure SPI chip select GPIO pins for the NXP FMUKRT1062-V1 board.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void imxrt_spidev_initialize(void)
|
||||
{
|
||||
for (int bus = 0; bus < SPI_BUS_MAX_BUS_ITEMS; ++bus) {
|
||||
for (int i = 0; i < SPI_BUS_MAX_DEVICES; ++i) {
|
||||
if (px4_spi_buses[bus].devices[i].cs_gpio != 0) {
|
||||
px4_arch_configgpio(px4_spi_buses[bus].devices[i].cs_gpio);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: imxrt_spi_bus_initialize
|
||||
*
|
||||
* Description:
|
||||
* Called to configure SPI chip select GPIO pins for the NXP FMUKRT1062-V1 board.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
static const px4_spi_bus_t *_spi_bus3;
|
||||
static const px4_spi_bus_t *_spi_bus4;
|
||||
|
||||
__EXPORT int imxrt1062_spi_bus_initialize(void)
|
||||
{
|
||||
for (int i = 0; i < SPI_BUS_MAX_BUS_ITEMS; ++i) {
|
||||
switch (px4_spi_buses[i].bus) {
|
||||
case 3: _spi_bus3 = &px4_spi_buses[i]; break;
|
||||
|
||||
case 4: _spi_bus4 = &px4_spi_buses[i]; break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Configure SPI-based devices */
|
||||
|
||||
struct spi_dev_s *spi_icm = px4_spibus_initialize(3);
|
||||
|
||||
if (!spi_icm) {
|
||||
PX4_ERR("[boot] FAILED to initialize SPI port %d\n", 1);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Default bus 1 to 8MHz and de-assert the known chip selects.
|
||||
*/
|
||||
|
||||
SPI_SETFREQUENCY(spi_icm, 8 * 1000 * 1000);
|
||||
SPI_SETBITS(spi_icm, 8);
|
||||
SPI_SETMODE(spi_icm, SPIDEV_MODE3);
|
||||
|
||||
/* Get the SPI port for the BMI088 */
|
||||
|
||||
struct spi_dev_s *spi_bmi = px4_spibus_initialize(4);
|
||||
|
||||
if (!spi_bmi) {
|
||||
PX4_ERR("[boot] FAILED to initialize SPI port %d\n", 4);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Default ext bus to 8MHz and de-assert the known chip selects.
|
||||
*/
|
||||
|
||||
SPI_SETFREQUENCY(spi_bmi, 8 * 1000 * 1000);
|
||||
SPI_SETBITS(spi_bmi, 8);
|
||||
SPI_SETMODE(spi_bmi, SPIDEV_MODE3);
|
||||
|
||||
/* deselect all */
|
||||
for (int bus = 0; bus < SPI_BUS_MAX_BUS_ITEMS; ++bus) {
|
||||
for (int i = 0; i < SPI_BUS_MAX_DEVICES; ++i) {
|
||||
if (px4_spi_buses[bus].devices[i].cs_gpio != 0) {
|
||||
SPI_SELECT(spi_bmi, px4_spi_buses[bus].devices[i].devid, false);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return OK;
|
||||
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imxrt_lpspi1/2/3select and imxrt_lpspi1/2/3status
|
||||
*
|
||||
* Description:
|
||||
* The external functions, imxrt_lpspi1/2/3select and imxrt_lpspi1/2/3status must be
|
||||
* provided by board-specific logic. They are implementations of the select
|
||||
* and status methods of the SPI interface defined by struct spi_ops_s (see
|
||||
* include/nuttx/spi/spi.h). All other methods (including imxrt_lpspibus_initialize())
|
||||
* are provided by common STM32 logic. To use this common SPI logic on your
|
||||
* board:
|
||||
*
|
||||
* 1. Provide logic in imxrt_boardinitialize() to configure SPI chip select
|
||||
* pins.
|
||||
* 2. Provide imxrt_lpspi1/2/3select() and imxrt_lpspi1/2/3status() functions in your
|
||||
* board-specific logic. These functions will perform chip selection and
|
||||
* status operations using GPIOs in the way your board is configured.
|
||||
* 3. Add a calls to imxrt_lpspibus_initialize() in your low level application
|
||||
* initialization logic
|
||||
* 4. The handle returned by imxrt_lpspibus_initialize() may then be used to bind the
|
||||
* SPI driver to higher level logic (e.g., calling
|
||||
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
|
||||
* the SPI MMC/SD driver).
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void imxrt_spixselect(const px4_spi_bus_t *bus, struct spi_dev_s *dev, uint32_t devid, bool selected)
|
||||
{
|
||||
for (int i = 0; i < SPI_BUS_MAX_DEVICES; ++i) {
|
||||
if (bus->devices[i].cs_gpio == 0) {
|
||||
break;
|
||||
}
|
||||
|
||||
if (devid == bus->devices[i].devid) {
|
||||
// SPI select is active low, so write !selected to select the device
|
||||
imxrt_gpio_write(bus->devices[i].cs_gpio, !selected);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_IMXRT_LPSPI3)
|
||||
__EXPORT void imxrt_lpspi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
|
||||
{
|
||||
imxrt_spixselect(_spi_bus3, dev, devid, selected);
|
||||
}
|
||||
|
||||
__EXPORT uint8_t imxrt_lpspi3status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
{
|
||||
return SPI_STATUS_PRESENT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_IMXRT_LPSPI4)
|
||||
__EXPORT void imxrt_lpspi4select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
|
||||
{
|
||||
imxrt_spixselect(_spi_bus4, dev, devid, selected);
|
||||
}
|
||||
|
||||
__EXPORT uint8_t imxrt_lpspi4status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
{
|
||||
return SPI_STATUS_PRESENT;
|
||||
}
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: board_spi_reset
|
||||
*
|
||||
* Description:
|
||||
*
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
__EXPORT void board_spi_reset(int ms, int bus_mask)
|
||||
{
|
||||
#ifdef CONFIG_IMXRT_LPSPI1
|
||||
|
||||
/* Goal not to back feed the chips on the bus via IO lines */
|
||||
for (int bus = 0; bus < SPI_BUS_MAX_BUS_ITEMS; ++bus) {
|
||||
if (px4_spi_buses[bus].bus == 1 || px4_spi_buses[bus].bus == 3) {
|
||||
for (int i = 0; i < SPI_BUS_MAX_DEVICES; ++i) {
|
||||
if (px4_spi_buses[bus].devices[i].cs_gpio != 0) {
|
||||
imxrt_config_gpio(_PIN_OFF(px4_spi_buses[bus].devices[i].cs_gpio));
|
||||
}
|
||||
|
||||
if (px4_spi_buses[bus].devices[i].drdy_gpio != 0) {
|
||||
imxrt_config_gpio(_PIN_OFF(px4_spi_buses[bus].devices[i].drdy_gpio));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
imxrt_config_gpio(GPIO_SPI1_SCK_OFF);
|
||||
imxrt_config_gpio(GPIO_SPI1_MISO_OFF);
|
||||
imxrt_config_gpio(GPIO_SPI1_MOSI_OFF);
|
||||
|
||||
imxrt_config_gpio(GPIO_SPI3_SCK_OFF);
|
||||
imxrt_config_gpio(GPIO_SPI3_MISO_OFF);
|
||||
imxrt_config_gpio(GPIO_SPI3_MOSI_OFF);
|
||||
|
||||
|
||||
imxrt_config_gpio(_PIN_OFF(GPIO_LPI2C3_SDA_RESET));
|
||||
imxrt_config_gpio(_PIN_OFF(GPIO_LPI2C3_SCL_RESET));
|
||||
|
||||
/* set the sensor rail off */
|
||||
imxrt_gpio_write(GPIO_VDD_3V3_SENSORS_EN, 0);
|
||||
|
||||
/* wait for the sensor rail to reach GND */
|
||||
usleep(ms * 1000);
|
||||
warnx("reset done, %d ms", ms);
|
||||
|
||||
/* re-enable power */
|
||||
|
||||
/* switch the sensor rail back on */
|
||||
imxrt_gpio_write(GPIO_VDD_3V3_SENSORS_EN, 1);
|
||||
|
||||
/* wait a bit before starting SPI, different times didn't influence results */
|
||||
usleep(100);
|
||||
|
||||
/* reconfigure the SPI pins */
|
||||
for (int bus = 0; bus < SPI_BUS_MAX_BUS_ITEMS; ++bus) {
|
||||
if (px4_spi_buses[bus].bus == 1 || px4_spi_buses[bus].bus == 3) {
|
||||
for (int i = 0; i < SPI_BUS_MAX_DEVICES; ++i) {
|
||||
if (px4_spi_buses[bus].devices[i].cs_gpio != 0) {
|
||||
imxrt_config_gpio(px4_spi_buses[bus].devices[i].cs_gpio);
|
||||
}
|
||||
|
||||
if (px4_spi_buses[bus].devices[i].drdy_gpio != 0) {
|
||||
imxrt_config_gpio(px4_spi_buses[bus].devices[i].drdy_gpio);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
imxrt_config_gpio(GPIO_LPSPI1_SCK);
|
||||
imxrt_config_gpio(GPIO_LPSPI1_MISO);
|
||||
imxrt_config_gpio(GPIO_LPSPI1_MOSI);
|
||||
|
||||
imxrt_config_gpio(GPIO_LPSPI3_SCK);
|
||||
imxrt_config_gpio(GPIO_LPSPI3_MISO);
|
||||
imxrt_config_gpio(GPIO_LPSPI3_MOSI);
|
||||
|
||||
imxrt_config_gpio(GPIO_LPI2C3_SDA);
|
||||
imxrt_config_gpio(GPIO_LPI2C3_SCL);
|
||||
|
||||
#endif /* CONFIG_IMXRT_LPSPI1 */
|
||||
|
||||
}
|
||||
|
||||
#endif /* CONFIG_IMXRT_LPSPI3 || CONFIG_IMXRT_LPSPI4 */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user